arch/all-pc/kernel/apic_ia32.h

   1 #ifndef APIC_IA32_H
   2 #define APIC_IA32_H
   3 /*
   4     Copyright © 1995-2018, The AROS Development Team. All rights reserved.
   5     $Id$
   6
   7     Desc: IA-32 APIC hardware definitions.
   8     Lang: english
   9 */
  10
  11 #include "i8259a.h"
  12
  13 // From CPU and LAPIC point of view we have 256 interrupt vectors. The first 32 are reserved
  14 // for CPU exceptions. Further, there are 16 vectors reserved for legacy XT-PIC (which can be
  15 // eventually remapped to LAPIC with help of IOAPIC). Official APIC IRQ base starts right
  16 // after legacy XT-PIC
  17 #define APIC_IRQ_MAX            256
  18 #define X86_CPU_EXCEPT_COUNT    32
  19 #define APIC_IRQ_BASE           (X86_CPU_EXCEPT_COUNT + I8259A_IRQCOUNT)
  20
  21 // Local APIC exceptions, with SysCall being the last (int $0xff)! The numeric values start
  22 // at X86_CPU_EXCEPT_COUNT in order to make the handler simplier
  23 enum
  24 {
  25     APIC_EXCEPT_HEARTBEAT = X86_CPU_EXCEPT_COUNT,
  26     APIC_EXCEPT_IPI_NOP,
  27     APIC_EXCEPT_IPI_IPI_STOP,
  28     APIC_EXCEPT_IPI_RESUME,
  29     APIC_EXCEPT_IPI_RESCHEDULE,
  30     APIC_EXCEPT_IPI_CALL_HOOK,
  31     APIC_EXCEPT_IPI_CAUSE,
  32     APIC_EXCEPT_ERROR,
  33     APIC_EXCEPT_SYSCALL,
  34     APIC_EXCEPT_SPURIOUS,
  35     APIC_EXCEPT_TOP
  36 };
  37
  38 #define APIC_CPU_EXCEPT_COUNT   (APIC_EXCEPT_TOP - X86_CPU_EXCEPT_COUNT)
  39 #define APIC_CPU_EXCEPT_BASE    (APIC_IRQ_MAX - APIC_CPU_EXCEPT_COUNT)
  40 #define APIC_IRQ_COUNT          (APIC_CPU_EXCEPT_BASE - APIC_IRQ_BASE)
  41
  42 #define APIC_CPU_EXCEPT_TO_VECTOR(num)  ((num) - X86_CPU_EXCEPT_COUNT + APIC_CPU_EXCEPT_BASE)
  43 #define GET_EXCEPTION_NUMBER(irq) \
  44     ((irq) < X86_CPU_EXCEPT_COUNT ? (irq) : ((irq) - APIC_CPU_EXCEPT_BASE + X86_CPU_EXCEPT_COUNT))
  45 #define GET_DEVICE_IRQ(irq)     ((irq) - X86_CPU_EXCEPT_COUNT)
  46 #define IS_APIC_EXCEPTION(irq)  (((irq) >= APIC_CPU_EXCEPT_BASE) && ((irq) < APIC_EXCEPT_SYSCALL))
  47 #define IS_EXCEPTION(irq)       ((irq) < X86_CPU_EXCEPT_COUNT || (irq) >= APIC_CPU_EXCEPT_BASE)
  48
  49
  50 /* Local APIC base address register (MSR #27) */
  51 #define MSR_LAPIC_BASE 0x1B
  52
  53 #define APIC_BOOTSTRAP (1 << 8)
  54 #define APIC_ENABLE    (1 << 11)
  55
  56 /* APIC hardware registers */
  57
  58 #define APIC_ID          0x20
  59 #define APIC_VERSION     0x30
  60 #define APIC_TPR         0x80   /* Task Priority Register                       */
  61 #define APIC_APR         0x90   /* Arbitration Priority Register                */
  62 #define APIC_PPR         0xA0   /* Processor Priority Register                  */
  63 #define APIC_EOI         0xB0   /* End Of Interrupt Register                    */
  64 #define APIC_REMOTE_READ 0xC0
  65 #define APIC_LDR         0xD0   /* Logical Destination Register                 */
  66 #define APIC_DFR         0xE0   /* Destination Format Register                  */
  67 #define APIC_SVR         0xF0   /* Spurious Interrupt Vector Register           */
  68 #define APIC_ISR         0x100  /* In Service Register                          */
  69 #define APIC_TMR         0x180  /* Trigger Mode Register                        */
  70 #define APIC_IRR         0x200  /* Interrupt Request Register                   */
  71 #define APIC_ESR         0x280  /* Error Status Register                        */
  72 #define APIC_ICRL        0x300  /* Interrupt Command Register low part          */
  73 #define APIC_ICRH        0x310  /* Interrupt Command Register high part         */
  74 #define APIC_TIMER_VEC   0x320  /* Timer local vector table entry               */
  75 #define APIC_THERMAL_VEC 0x330  /* Thermal local vector table entry             */
  76 #define APIC_PCOUNT_VEC  0x340  /* Performance counter local vector table entry */
  77 #define APIC_LINT0_VEC   0x350  /* Local interrupt 0 vector table entry         */
  78 #define APIC_LINT1_VEC   0x360  /* Local interrupt 1 vector table entry         */
  79 #define APIC_ERROR_VEC   0x370  /* Error vector table entry                     */
  80 #define APIC_TIMER_ICR   0x380  /* Timer initial count                          */
  81 #define APIC_TIMER_CCR   0x390  /* Timer current count                          */
  82 #define APIC_TIMER_DIV   0x3E0  /* Timer divide configuration register          */
  83
  84 /* ID shift value */
  85 #define APIC_ID_SHIFT 24
  86
  87 /* Version register */
  88 #define APIC_VERSION_MASK 0x000000FF    /* The actual version number                         */
  89 #define APIC_LVT_MASK     0x00FF0000    /* Number of entries in local vector table minus one */
  90 #define APIC_LVT_SHIFT    16
  91 #define APIC_EAS          (1 << 31)     /* Whether this APIC has extended address space      */
  92
  93 /* Macros to help parsing version */
  94 #define APIC_INTEGRATED(ver) (ver & 0x000000F0)
  95 #define APIC_LVT(ver)        ((ver & APIC_LVT_MASK) >> APIC_LVT_SHIFT)
  96
  97 /* LDR shift value */
  98 #define LDR_ID_SHIFT 24
  99
 100 /* Destination format (interrupt model) */
 101 #define DFR_CLUSTER (0x0 << 28)
 102 #define DFR_FLAT    (0xF << 28)
 103
 104 #define SVR_VEC_MASK 0xFF
 105 #define SVR_ASE      (1 << 8)
 106 #define SVR_FCC      (1 << 9)
 107
 108 /* Error register */
 109 #define ERR_SAE (1 << 2) /* Sent accept error        */
 110 #define ERR_RAE (1 << 3) /* Receive accept error     */
 111 #define ERR_SIV (1 << 5) /* Sent illegal vector      */
 112 #define ERR_RIV (1 << 6) /* Received illegal vector  */
 113 #define ERR_IRA (1 << 7) /* Illegal register address */
 114
 115 /* ICRL register */
 116 #define ICR_VEC_MASK      0x000000FF    /* Vector number (request argument) mask        */
 117 #define ICR_DM_INIT       0x0500        /* INIT request (reset the CPU)                 */
 118 #define ICR_DM_STARTUP    0x0600        /* STARTUP request (run from specified address) */
 119 #define ICR_DS            0x1000        /* Delivery status flag                         */
 120 #define ICR_INT_LEVELTRIG 0x8000        /* Send level-triggered interrupt               */
 121 #define ICR_INT_ASSERT    0x4000        /* Assert (set) or deassert (reset)             */
 122
 123 /* Local vector table entry fields */
 124 #define LVT_VEC_MASK   0x0000FF         /* Vector no                            */
 125 #define LVT_MT_MASK    0x000700         /* Message type                         */
 126 #define LVT_MT_FIXED   0x000000
 127 #define LVT_MT_SMI     0x000200
 128 #define LVT_MT_NMI     0x000400
 129 #define LVT_MT_EXT     0x000700
 130 #define LVT_DS         0x001000         /* Delivery status bit                  */
 131 #define LVT_ACTIVE_LOW 0x002000         /* Polarity flag (1 = low active)       */
 132 #define LVT_RIR        0x004000         /* Remote IRR                           */
 133 #define LVT_TGM_LEVEL  0x008000         /* Level-trigger mode                   */
 134 #define LVT_MASK       0x010000         /* Mask bit                             */
 135 #define LVT_TMM_PERIOD 0x020000         /* Periodic timer mode                  */
 136
 137 /* Timer divisors */
 138 #define TIMER_DIV_1   0x0B
 139 #define TIMER_DIV_2   0x00
 140 #define TIMER_DIV_4   0x01
 141 #define TIMER_DIV_8   0x02
 142 #define TIMER_DIV_16  0x03
 143 #define TIMER_DIV_32  0x08
 144 #define TIMER_DIV_64  0x09
 145 #define TIMER_DIV_128 0x0A
 146
 147 /* Register access macro to make the code more readable */
 148 #define APIC_REG(base, reg) *((volatile ULONG *)(base + reg))
 149
 150 #endif /* !APIC_IA32_H */