arch/all-pc/processor/processor_frequency.c

   1 /*
   2     Copyright © 2010-2017, The AROS Development Team. All rights reserved.
   3     $Id$
   4 */
   5
   6 #define DEBUG 0
   7
   8 #include <aros/config.h>
   9 #include <aros/debug.h>
  10 #include <proto/exec.h>
  11 #include <resources/processor.h>
  12
  13 #include "processor_arch_intern.h"
  14
  15 /*
  16  * This code can't work on hosted because rdmsr instruction requires supervisor privilege.
  17  * Hosted ports could have host-specific version of this code which would utilize host OS services.
  18  */
  19 #if (AROS_FLAVOUR & AROS_FLAVOUR_STANDALONE)
  20
  21 #define MSR_IA32_MPERF              0xE7
  22 #define MSR_IA32_APERF              0xE8
  23 #define MSR_P4_EBC_FREQUENCY_ID     0x2C
  24 #define MSR_CORE_FSB_FREQ           0xCD
  25 #define MSR_CORE_EBL_CR_POWERON     0x2A
  26 #define MSR_NAHALEM_PLATFORM_INFO   0xCE
  27 #define MSR_K10_PSTATE_P0           0xC0010064
  28 #define MSR_K8_FIDVID_STATUS        0xC0010042
  29
  30 #define FSB_100 100000000ULL
  31 #define FSB_133 133330000ULL
  32 #define FSB_166 166670000ULL
  33 #define FSB_200 200000000ULL
  34 #define FSB_266 266670000ULL
  35 #define FSB_333 333330000ULL
  36 #define FSB_400 400000000ULL
  37
  38 static VOID ReadIntelMaxFrequencyInformation(struct X86ProcessorInformation * info)
  39 {
  40     APTR ssp;
  41
  42     D(bug("[processor.x86] :%s()\n", __func__));
  43
  44     ssp = SuperState();
  45
  46     /* Procedure for Pentium 4 family (NetBurst) */
  47     if ((info->Family == CPUFAMILY_INTEL_PENTIUM4) && (info->Model >= 2))
  48     {
  49         ULONG eax, edx;
  50         UQUAD fsb = 0;
  51         ULONG mult = 0;
  52
  53         /* This procedure calculates the maximum frequency */
  54
  55         rdmsr(MSR_P4_EBC_FREQUENCY_ID, &eax, &edx);
  56
  57         /*Intel 64 and IA-32 Architectures
  58           Software Developer's Manual
  59           Volume 3B:System Programming Guide, Part 2
  60           Table B-12 */
  61         switch((eax >> 16) & 0x07)
  62         {
  63             case(0):
  64                 if (info->Model == 2)
  65                     fsb = FSB_100;
  66                 else
  67                     fsb = FSB_266;
  68                 break;
  69             case(1): fsb = FSB_133; break;
  70             case(2): fsb = FSB_200; break;
  71             case(3): fsb = FSB_166; break;
  72             case(4): fsb = FSB_333; break;
  73             default: fsb = 0; break;
  74         }
  75
  76         /* Getting multiplier at reset time */
  77         mult = eax >> 24;
  78
  79         info->MaxCPUFrequency = fsb * mult;
  80         info->MaxFSBFrequency = fsb * 4;
  81     }
  82
  83     /* Procedure for Pentium M (part of Pentium Pro) family */
  84     if ((info->Family == CPUFAMILY_INTEL_PENTIUM_PRO) &&
  85         (
  86         (info->Model == 0x09) || /* Pentium M */
  87         (info->Model == 0x0D)   /* Pentium M */
  88         )
  89         )
  90     {
  91         ULONG eax, edx;
  92         ULONG mult = 0;
  93
  94         /*Intel 64 and IA-32 Architectures
  95           Software Developer's Manual
  96           Volume 3B:System Programming Guide, Part 2
  97           Table B-16 */
  98
  99         rdmsr(MSR_CORE_EBL_CR_POWERON, &eax, &edx);
 100
 101         mult = (eax >> 22) & 0x1F;
 102
 103         info->MaxCPUFrequency = FSB_100 * mult;
 104         info->MaxFSBFrequency = FSB_100 * 4;
 105     }
 106
 107     /* Procedure for Core (part of Pentium Pro) family (ATOM, Core, Core Duo) */
 108     if ((info->Family == CPUFAMILY_INTEL_PENTIUM_PRO) &&
 109         (
 110         (info->Model == 0x0E) || /* Core Duo */
 111         (info->Model == 0x0F) || /* Core 2 Duo */
 112         (info->Model == 0x16) || /* Core Celeron */
 113         (info->Model == 0x17) || /* Core 2 Extreme */
 114         (info->Model == 0x1C)   /* ATOM */
 115         )
 116         )
 117     {
 118         ULONG eax, edx;
 119         UQUAD fsb = 0;
 120         ULONG mult = 0;
 121
 122         /* This procedure calculates the maximum frequency */
 123
 124         rdmsr(MSR_CORE_FSB_FREQ, &eax, &edx);
 125
 126         /*Intel 64 and IA-32 Architectures
 127           Software Developer's Manual
 128           Volume 3B:System Programming Guide, Part 2
 129           Table B-3 */
 130         switch(eax & 0x07)
 131         {
 132             case(5): fsb = FSB_100; break;
 133             case(1): fsb = FSB_133; break;
 134             case(3): fsb = FSB_166; break;
 135             case(2): fsb = FSB_200; break;
 136             case(0): fsb = FSB_266; break;
 137             case(4): fsb = FSB_333; break;
 138             case(6): fsb = FSB_400; break;
 139             default: fsb = 0; break;
 140         }
 141
 142         rdmsr(MSR_CORE_EBL_CR_POWERON, &eax, &edx);
 143         /* Getting multiplier at reset time */
 144         mult = (eax >> 22) & 0x1F;
 145
 146         info->MaxCPUFrequency = fsb * mult;
 147         info->MaxFSBFrequency = fsb * 4;
 148     }
 149
 150     /* Procedure for Nahalem (part of Pentium Pro) family (i7, i5, i3) */
 151     if ((info->Family == CPUFAMILY_INTEL_PENTIUM_PRO) &&
 152         (
 153         (info->Model == 0x1A) || /* Core i7 */
 154         (info->Model == 0x1E) || /* ? */
 155         (info->Model == 0x1F) || /* ? */
 156         (info->Model == 0x2E)    /* ? */
 157         )
 158         )
 159     {
 160         ULONG mult = 0;
 161
 162         /* This procedure calculates the maximum frequency */
 163         mult = rdmsri(MSR_NAHALEM_PLATFORM_INFO);
 164
 165         /*Intel 64 and IA-32 Architectures
 166           Software Developer's Manual
 167           Volume 3B:System Programming Guide, Part 2
 168           Table B-5 */
 169         mult = (mult >> 8) & 0xFF;
 170
 171         info->MaxCPUFrequency = FSB_133 * mult;
 172         /* Note: FSB is not a valid concept with iX (Nahalem) processors */
 173         info->MaxFSBFrequency = 0;
 174     }
 175
 176     /* Procedure for SandyBridge and newer (part of Pentium Pro) family (i7, i5, i3) */
 177     if ((info->Family == CPUFAMILY_INTEL_PENTIUM_PRO) &&
 178         (
 179             (info->Model == 0x2A) || /* SandyBridge */
 180             (info->Model == 0x2D) || /* SandyBridge */
 181             (info->Model == 0x3A) || /* IvyBridge */
 182             (info->Model == 0x3C) || /* Haswell */
 183             (info->Model == 0x45) || /* Haswell */
 184             (info->Model == 0x46) || /* Haswell */
 185             (info->Model == 0x3F)  /* Haswell-E */
 186             /* More to come... */
 187         )
 188         )
 189     {
 190         ULONG mult = 0;
 191
 192         /* This procedure calculates the maximum frequency */
 193         mult = rdmsri(MSR_NAHALEM_PLATFORM_INFO);
 194
 195         /*Intel 64 and IA-32 Architectures
 196           Software Developer's Manual
 197           Volume 3B:System Programming Guide, Part 2
 198           Table B-5 */
 199         mult = (mult >> 8) & 0xFF;
 200
 201         info->MaxCPUFrequency = FSB_100 * mult;
 202         /* Note: FSB is not a valid concept with iX (Nahalem) processors */
 203         info->MaxFSBFrequency = 0;
 204     }
 205
 206     UserState(ssp);
 207 }
 208
 209 static VOID ReadAMDMaxFrequencyInformation(struct X86ProcessorInformation * info)
 210 {
 211     APTR ssp;
 212
 213     D(bug("[processor.x86] :%s()\n", __func__));
 214
 215     ssp = SuperState();
 216
 217     if (info->Family == CPUFAMILY_AMD_K10)
 218     {
 219         ULONG eax, edx;
 220         ULONG cpufid = 0, cpudid = 0;
 221
 222         /* AMD Family 10h Processor BKDG, page 425 */
 223         rdmsr(MSR_K10_PSTATE_P0, &eax, &edx);
 224
 225         cpufid = eax & 0x1F;
 226         cpudid = (eax >> 6) & 0x07;
 227
 228         info->MaxCPUFrequency = FSB_100 * (cpufid + 0x10) / (1 << cpudid);
 229         /* Note: FSB is not a valid concept with K10 processors */
 230         info->MaxFSBFrequency = 0;
 231     }
 232
 233     if ((info->Family == CPUFAMILY_AMD_K9)
 234         || (info->Family == CPUFAMILY_AMD_K8))
 235     {
 236         ULONG eax, ebx, ecx, edx;
 237         ULONG cpufid = 0;
 238         BOOL success = TRUE;
 239
 240         /* BIOS and Kernel Developer's Guide for the AMD AthlonTM 64 and
 241             AMD OpteronTM Processors, page 382 */
 242
 243         /* Check for power management features */
 244         if (info->CPUIDHighestExtendedFunction < 0x80000007)
 245             success = FALSE;
 246
 247         if (success)
 248         {
 249             cpuid(0x80000007);
 250
 251             /* Check avalability of FID */
 252             if ((edx & 0x02) == 0)
 253                 success = FALSE;
 254         }
 255
 256         if (success)
 257         {
 258             /* It should be safe to read MSR_K8_FIDVID_STATUS */
 259             rdmsr(MSR_K8_FIDVID_STATUS, &eax, &edx);
 260
 261             cpufid = (eax >> 16) & 0x3F;
 262
 263             /* Note: K8 has only even multipliers, but they match K9 ones */
 264             info->MaxCPUFrequency = FSB_200 * (4 * 2 + cpufid) / 2;
 265
 266             /* Note: FSB is not a valid concept with K8, K9 processors */
 267             info->MaxFSBFrequency = 0;
 268         }
 269     }
 270
 271     UserState(ssp);
 272 }
 273
 274 #endif /* AROS_FLAVOUR_STANDALONE */
 275
 276 VOID ReadMaxFrequencyInformation(struct X86ProcessorInformation * info)
 277 {
 278     D(bug("[processor.x86] :%s()\n", __func__));
 279
 280     info->MaxCPUFrequency = 0;
 281     info->MaxFSBFrequency = 0;
 282
 283 #if (AROS_FLAVOUR & AROS_FLAVOUR_STANDALONE)
 284
 285     switch(info->Vendor)
 286     {
 287     case(VENDOR_INTEL):
 288         ReadIntelMaxFrequencyInformation(info);
 289         break;
 290     case(VENDOR_AMD):
 291         ReadAMDMaxFrequencyInformation(info);
 292         break;
 293     default:
 294         break;
 295     };
 296
 297 #endif
 298 }
 299
 300 /* Currently the only method of calculating CPU Frequency is based on
 301    using performance counter. Other methods might include reading power state
 302    and checking with ACPI power tables or hardcoded power tables */
 303
 304 UQUAD GetCurrentProcessorFrequency(struct X86ProcessorInformation * info)
 305 {
 306     UQUAD retFreq = info->MaxCPUFrequency;
 307
 308     D(bug("[processor.x86] :%s()\n", __func__));
 309
 310 #if (AROS_FLAVOUR & AROS_FLAVOUR_STANDALONE)
 311
 312     /*
 313     Check if APERF/MPERF is available
 314     Notes: K10, K9 - rdmsr can be used to read current PState/cpufid/cpudid
 315     */
 316     if (info->APERFMPERF)
 317     {
 318         APTR ssp;
 319         ULONG eax, edx;
 320         UQUAD startaperf, endaperf, diffaperf = 0;
 321         UQUAD startmperf, endmperf, diffmperf = 0;
 322         LONG i;
 323
 324         ssp = SuperState();
 325
 326         for(i = 0; i < 10; i++)
 327         {
 328             rdmsr(MSR_IA32_MPERF, &eax, &edx);
 329             startmperf = (UQUAD)edx << 32 | eax;
 330             rdmsr(MSR_IA32_APERF, &eax, &edx);
 331             startaperf = (UQUAD)edx << 32 | eax;
 332
 333             rdmsr(MSR_IA32_MPERF, &eax, &edx);
 334             endmperf = (UQUAD)edx << 32 | eax;
 335             rdmsr(MSR_IA32_APERF, &eax, &edx);
 336             endaperf = (UQUAD)edx << 32 | eax;
 337
 338             if ((startmperf > endmperf) || (startaperf > endaperf))
 339                 continue; /* Overflow error. Skip */
 340
 341             diffmperf += endmperf - startmperf;
 342             diffaperf += endaperf - startaperf;
 343         }
 344
 345         UserState(ssp);
 346
 347         D(bug("[processor.x86] %s: max: %x, diffa: %x, diffm %x\n", __func__, info->MaxCPUFrequency, diffaperf, diffmperf));
 348
 349         if (info->MaxCPUFrequency == 0)
 350             ReadMaxFrequencyInformation(info);
 351
 352         /* Use ratio between MPERF and APERF */
 353         if (diffmperf)
 354             retFreq = info->MaxCPUFrequency * diffaperf / diffmperf;
 355         else
 356             retFreq = info->MaxCPUFrequency;
 357     }
 358     else
 359     {
 360         /* use PStates? */
 361     }
 362
 363 #endif
 364
 365     return retFreq;
 366 }