arch/arm-native/kernel/mmu.c

   1 /*
   2     Copyright © 2013, The AROS Development Team. All rights reserved.
   3     $Id$
   4 */
   5
   6 #include <inttypes.h>
   7 #include <aros/kernel.h>
   8 #include <aros/libcall.h>
   9 #include <hardware/bcm2708_boot.h>
  10 #include <stddef.h>
  11 #include <string.h>
  12
  13 #include <proto/exec.h>
  14 #include <proto/kernel.h>
  15
  16 #include "kernel_intern.h"
  17 #include "mmu.h"
  18
  19 void core_MMUUpdatePageTables(void)
  20 {
  21     static pde_t *pde = (pde_t *)BOOTMEMADDR(bm_pde);
  22
  23     /* Invalidate caches */
  24     asm volatile("mcr   p15, 0, %[r], c8, c7, 0" : : [r] "r" (0x0));   //Invalidate entire unified TLB
  25     asm volatile("mcr   p15, 0, %[r], c8, c6, 0" : : [r] "r" (0x0));   //Invalidate entire data TLB
  26     asm volatile("mcr   p15, 0, %[r], c8, c5, 0" : : [r] "r" (0x0));   //Invalidate entire instruction TLB
  27     asm volatile("mcr   p15, 0, %[r], c7, c5, 6" : : [r] "r" (0x0));   //Invalidate entire branch prediction array
  28     asm volatile("mcr   p15, 0, %[r], c7, c5, 0" : : [r] "r" (0x0));   //Invalidate icache
  29
  30     /* setup_ttbr0/1 */
  31     asm volatile("mcr   p15, 0, %[addr], c2, c0, 1" : : [addr] "r" (pde));
  32     /* setup_ttbrc */
  33     asm volatile("mcr   p15, 0, %[n], c2, c0, 2" : : [n] "r" (7));
  34 }
  35
  36 void core_SetupMMU(struct TagItem *msg)
  37 {
  38     register unsigned int control;
  39
  40     core_MMUUpdatePageTables();
  41
  42     /* Set the domain access control to all-supervisor */
  43     asm volatile("mcr   p15, 0, %[r], c3, c0, 0" : : [r] "r" (~0));
  44
  45     /* Enable L1 caches (I-cache and D-cache) and MMU.*/
  46     asm volatile("mrc   p15, 0, %[control], c1, c0, 0" : [control] "=r" (control));
  47     control |= ( ENABLE_I_CACHE | ENABLE_D_CACHE | ENABLE_MMU );
  48     asm volatile ("mcr  p15, 0, %[r], c7, c10, 4" : : [r] "r" (0)); /* dsb */
  49     asm volatile ("mcr  p15, 0, %0, c1, c0, 0" : : "r" (control) : "cc" );
  50     asm volatile ("mcr  p15, 0, %[r], c7, c5, 4" : : [r] "r" (0)); /* isb */
  51
  52     D(bug("[Kernel] core_SetupMMU: Done\n"));
  53 }
  54
  55 void core_ProtPage(intptr_t addr, char p, char rw, char us)
  56 {
  57     D(bug("[Kernel] Marking page 0x%p as read-only\n", addr));
  58
  59     core_MMUUpdatePageTables();
  60 }
  61
  62 void core_ProtKernelArea(intptr_t addr, intptr_t length, char p, char rw, char us)
  63 {
  64     D(bug("[Kernel] Protecting area 0x%p - 0x%p\n", addr, addr + length - 1));
  65     while (length > 0)
  66     {
  67         core_ProtPage(addr, p, rw, us);
  68         addr += 4096;
  69         length -= 4096;
  70     }
  71 }