arch/arm-raspi/boot/serialdebug.c

   1 /*
   2     Copyright © 2013-2019, The AROS Development Team. All rights reserved.
   3     $Id$
   4 */
   5
   6 #include <aros/macros.h>
   7 #include <inttypes.h>
   8 #include <stdio.h>
   9 #include <stdint.h>
  10
  11 #include <hardware/bcm2708.h>
  12 #include <hardware/bcm2708_boot.h>
  13 #include <hardware/videocore.h>
  14 #include <hardware/pl011uart.h>
  15
  16 #include "serialdebug.h"
  17 #include "bootconsole.h"
  18 #include "vc_mb.h"
  19 #include "io.h"
  20
  21 #undef ARM_PERIIOBASE
  22 #define ARM_PERIIOBASE (__arm_periiobase)
  23 extern uint32_t __arm_periiobase;
  24
  25 #define PL011_ICR_FLAGS (PL011_ICR_RXIC|PL011_ICR_TXIC|PL011_ICR_RTIC|PL011_ICR_FEIC|PL011_ICR_PEIC|PL011_ICR_BEIC|PL011_ICR_OEIC|PL011_ICR_RIMIC|PL011_ICR_CTSMIC|PL011_ICR_DSRMIC|PL011_ICR_DCDMIC)
  26
  27 #define DEF_BAUD 115200
  28
  29 #define PL011_DIVCLOCK(baud, clock)     ((clock * 4) / baud)
  30 #define PL011_BAUDINT(baud, clock)      ((PL011_DIVCLOCK(baud, clock) & 0xFFFFFFC0) >> 6)
  31 #define PL011_BAUDFRAC(baud, clock)     ((PL011_DIVCLOCK(baud, clock) & 0x0000003F) >> 0)
  32
  33 unsigned int uartclock;
  34 unsigned int uartdivint;
  35 unsigned int uartdivfrac;
  36 unsigned int uartbaud;
  37
  38 inline void waitSerOUT()
  39 {
  40     while(1)
  41     {
  42        if ((rd32le(PL011_0_BASE + PL011_FR) & PL011_FR_TXFF) == 0) break;
  43     }
  44 }
  45
  46 inline void putByte(uint8_t chr)
  47 {
  48     waitSerOUT();
  49
  50     if (chr == '\n')
  51     {
  52         wr32le(PL011_0_BASE + PL011_DR, '\r');
  53         waitSerOUT();
  54     }
  55     wr32le(PL011_0_BASE + PL011_DR, chr);
  56 }
  57
  58 void serInit(void)
  59 {
  60     unsigned int        uartvar;
  61
  62     volatile unsigned int *uart_msg = (unsigned int *) BOOTMEMADDR(bm_mboxmsg);
  63
  64     uartbaud = DEF_BAUD;
  65
  66     uart_msg[0] = AROS_LONG2LE(8 * 4);
  67     uart_msg[1] = AROS_LONG2LE(VCTAG_REQ);
  68     uart_msg[2] = AROS_LONG2LE(VCTAG_GETCLKRATE);
  69     uart_msg[3] = AROS_LONG2LE(8);
  70     uart_msg[4] = AROS_LONG2LE(4);
  71     uart_msg[5] = AROS_LONG2LE(0x000000002);                  // UART clock
  72     uart_msg[6] = 0;
  73     uart_msg[7] = 0;                            // terminate tag
  74
  75     vcmb_write(VCMB_BASE, VCMB_PROPCHAN, (void*)uart_msg);
  76     uart_msg = vcmb_read(VCMB_BASE, VCMB_PROPCHAN);
  77
  78     uartclock = AROS_LE2LONG(uart_msg[6]);
  79
  80     wr32le(PL011_0_BASE + PL011_CR, 0);
  81
  82     uartvar = rd32le(GPFSEL1);
  83     uartvar &= ~(7<<12);                        // TX on GPIO14
  84     uartvar |= 4<<12;                           // alt0
  85     uartvar &= ~(7<<15);                        // RX on GPIO15
  86     uartvar |= 4<<15;                           // alt0
  87     wr32le(GPFSEL1, uartvar);
  88
  89     /* Disable pull-ups and pull-downs on rs232 lines */
  90     wr32le(GPPUD, 0);
  91
  92     for (uartvar = 0; uartvar < 150; uartvar++) asm volatile ("mov r0, r0\n");
  93
  94     wr32le(GPPUDCLK0, (1 << 14)|(1 << 15));
  95
  96     for (uartvar = 0; uartvar < 150; uartvar++) asm volatile ("mov r0, r0\n");
  97
  98     wr32le(GPPUDCLK0, 0);
  99
 100     wr32le(PL011_0_BASE + PL011_ICR, PL011_ICR_FLAGS);
 101     uartdivint = PL011_BAUDINT(uartbaud, uartclock);
 102     wr32le(PL011_0_BASE + PL011_IBRD, uartdivint);
 103     uartdivfrac = PL011_BAUDFRAC(uartbaud, uartclock);
 104     wr32le(PL011_0_BASE + PL011_FBRD, uartdivfrac);
 105     wr32le(PL011_0_BASE + PL011_LCRH, PL011_LCRH_WLEN8|PL011_LCRH_FEN);           // 8N1, Fifo enabled
 106     wr32le(PL011_0_BASE + PL011_CR, PL011_CR_UARTEN|PL011_CR_TXE|PL011_CR_RXE);   // enable the uart, tx and rx
 107
 108     for (uartvar = 0; uartvar < 150; uartvar++) asm volatile ("mov r0, r0\n");
 109 }