arch/ppc-all/include/aros/fenv.h

   1 /*-
   2  * Copyright (c) 2004-2005 David Schultz <das@FreeBSD.ORG>
   3  * All rights reserved.
   4  *
   5  * Redistribution and use in source and binary forms, with or without
   6  * modification, are permitted provided that the following conditions
   7  * are met:
   8  * 1. Redistributions of source code must retain the above copyright
   9  *    notice, this list of conditions and the following disclaimer.
  10  * 2. Redistributions in binary form must reproduce the above copyright
  11  *    notice, this list of conditions and the following disclaimer in the
  12  *    documentation and/or other materials provided with the distribution.
  13  *
  14  * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND
  15  * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
  16  * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
  17  * ARE DISCLAIMED.  IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE
  18  * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
  19  * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
  20  * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
  21  * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
  22  * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
  23  * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
  24  * SUCH DAMAGE.
  25  *
  26  * $FreeBSD: src/lib/msun/powerpc/fenv.h,v 1.3 2005/03/16 19:03:45 das Exp $
  27  */
  28
  29 #ifndef _FENV_H_
  30 #define _FENV_H_
  31
  32 #ifdef __AROS__
  33 #include <aros/system.h>
  34 #endif
  35 #include <aros/types/int_t.h>
  36
  37 typedef uint32_t        fenv_t;
  38 typedef uint32_t        fexcept_t;
  39
  40 /* Exception flags */
  41 #define FE_INEXACT      0x02000000
  42 #define FE_DIVBYZERO    0x04000000
  43 #define FE_UNDERFLOW    0x08000000
  44 #define FE_OVERFLOW     0x10000000
  45 #define FE_INVALID      0x20000000      /* all types of invalid FP ops */
  46
  47 /*
  48  * The PowerPC architecture has extra invalid flags that indicate the
  49  * specific type of invalid operation occurred.  These flags may be
  50  * tested, set, and cleared---but not masked---separately.  All of
  51  * these bits are cleared when FE_INVALID is cleared, but only
  52  * FE_VXSOFT is set when FE_INVALID is explicitly set in software.
  53  */
  54 #define FE_VXCVI        0x00000100      /* invalid integer convert */
  55 #define FE_VXSQRT       0x00000200      /* square root of a negative */
  56 #define FE_VXSOFT       0x00000400      /* software-requested exception */
  57 #define FE_VXVC         0x00080000      /* ordered comparison involving NaN */
  58 #define FE_VXIMZ        0x00100000      /* inf * 0 */
  59 #define FE_VXZDZ        0x00200000      /* 0 / 0 */
  60 #define FE_VXIDI        0x00400000      /* inf / inf */
  61 #define FE_VXISI        0x00800000      /* inf - inf */
  62 #define FE_VXSNAN       0x01000000      /* operation on a signalling NaN */
  63 #define FE_ALL_INVALID  (FE_VXCVI | FE_VXSQRT | FE_VXSOFT | FE_VXVC | \
  64                          FE_VXIMZ | FE_VXZDZ | FE_VXIDI | FE_VXISI | \
  65                          FE_VXSNAN | FE_INVALID)
  66 #define FE_ALL_EXCEPT   (FE_DIVBYZERO | FE_INEXACT | \
  67                          FE_ALL_INVALID | FE_OVERFLOW | FE_UNDERFLOW)
  68
  69 /* Rounding modes */
  70 #define FE_TONEAREST    0x0000
  71 #define FE_TOWARDZERO   0x0001
  72 #define FE_UPWARD       0x0002
  73 #define FE_DOWNWARD     0x0003
  74 #define _ROUND_MASK     (FE_TONEAREST | FE_DOWNWARD | \
  75                          FE_UPWARD | FE_TOWARDZERO)
  76
  77 __BEGIN_DECLS
  78
  79 /* Default floating-point environment */
  80 extern const fenv_t     __fe_dfl_env;
  81 #define FE_DFL_ENV      (&__fe_dfl_env)
  82
  83 /* We need to be able to map status flag positions to mask flag positions */
  84 #define _FPUSW_SHIFT    22
  85 #define _ENABLE_MASK    ((FE_DIVBYZERO | FE_INEXACT | FE_INVALID | \
  86                          FE_OVERFLOW | FE_UNDERFLOW) >> _FPUSW_SHIFT)
  87
  88 #define __mffs(__env)   __asm __volatile("mffs %0" : "=f" (*(__env)))
  89 #define __mtfsf(__env)  __asm __volatile("mtfsf 255,%0" : : "f" (__env))
  90
  91 union __fpscr {
  92         double __d;
  93         struct {
  94                 uint32_t __junk;
  95                 fenv_t __reg;
  96         } __bits;
  97 };
  98
  99 #ifndef STDC_NOINLINE
 100 static __inline int
 101 feclearexcept(int __excepts)
 102 {
 103         union __fpscr __r;
 104
 105         if (__excepts & FE_INVALID)
 106                 __excepts |= FE_ALL_INVALID;
 107         __mffs(&__r.__d);
 108         __r.__bits.__reg &= ~__excepts;
 109         __mtfsf(__r.__d);
 110         return (0);
 111 }
 112
 113 static __inline int
 114 fegetexceptflag(fexcept_t *__flagp, int __excepts)
 115 {
 116         union __fpscr __r;
 117
 118         __mffs(&__r.__d);
 119         *__flagp = __r.__bits.__reg & __excepts;
 120         return (0);
 121 }
 122
 123 static __inline int
 124 fesetexceptflag(const fexcept_t *__flagp, int __excepts)
 125 {
 126         union __fpscr __r;
 127
 128         if (__excepts & FE_INVALID)
 129                 __excepts |= FE_ALL_EXCEPT;
 130         __mffs(&__r.__d);
 131         __r.__bits.__reg &= ~__excepts;
 132         __r.__bits.__reg |= *__flagp & __excepts;
 133         __mtfsf(__r.__d);
 134         return (0);
 135 }
 136
 137 static __inline int
 138 feraiseexcept(int __excepts)
 139 {
 140         union __fpscr __r;
 141
 142         if (__excepts & FE_INVALID)
 143                 __excepts |= FE_VXSOFT;
 144         __mffs(&__r.__d);
 145         __r.__bits.__reg |= __excepts;
 146         __mtfsf(__r.__d);
 147         return (0);
 148 }
 149
 150 static __inline int
 151 fetestexcept(int __excepts)
 152 {
 153         union __fpscr __r;
 154
 155         __mffs(&__r.__d);
 156         return (__r.__bits.__reg & __excepts);
 157 }
 158
 159 static __inline int
 160 fegetround(void)
 161 {
 162         union __fpscr __r;
 163
 164         __mffs(&__r.__d);
 165         return (__r.__bits.__reg & _ROUND_MASK);
 166 }
 167
 168 static __inline int
 169 fesetround(int __round)
 170 {
 171         union __fpscr __r;
 172
 173         if (__round & ~_ROUND_MASK)
 174                 return (-1);
 175         __mffs(&__r.__d);
 176         __r.__bits.__reg &= ~_ROUND_MASK;
 177         __r.__bits.__reg |= __round;
 178         __mtfsf(__r.__d);
 179         return (0);
 180 }
 181
 182 static __inline int
 183 fegetenv(fenv_t *__envp)
 184 {
 185         union __fpscr __r;
 186
 187         __mffs(&__r.__d);
 188         *__envp = __r.__bits.__reg;
 189         return (0);
 190 }
 191
 192 static __inline int
 193 feholdexcept(fenv_t *__envp)
 194 {
 195         union __fpscr __r;
 196
 197         __mffs(&__r.__d);
 198         *__envp = __r.__d;
 199         __r.__bits.__reg &= ~(FE_ALL_EXCEPT | _ENABLE_MASK);
 200         __mtfsf(__r.__d);
 201         return (0);
 202 }
 203
 204 static __inline int
 205 fesetenv(const fenv_t *__envp)
 206 {
 207         union __fpscr __r;
 208
 209         __r.__bits.__reg = *__envp;
 210         __mtfsf(__r.__d);
 211         return (0);
 212 }
 213
 214 static __inline int
 215 feupdateenv(const fenv_t *__envp)
 216 {
 217         union __fpscr __r;
 218
 219         __mffs(&__r.__d);
 220         __r.__bits.__reg &= FE_ALL_EXCEPT;
 221         __r.__bits.__reg |= *__envp;
 222         __mtfsf(__r.__d);
 223         return (0);
 224 }
 225 #endif /* !STDC_NOINLINE */
 226
 227 #if __BSD_VISIBLE
 228
 229 #ifndef STDC_NOINLINE
 230 static __inline int
 231 feenableexcept(int __mask)
 232 {
 233         union __fpscr __r;
 234         fenv_t __oldmask;
 235
 236         __mffs(&__r.__d);
 237         __oldmask = __r.__bits.__reg;
 238         __r.__bits.__reg |= (__mask & FE_ALL_EXCEPT) >> _FPUSW_SHIFT;
 239         __mtfsf(__r.__d);
 240         return ((__oldmask & _ENABLE_MASK) << _FPUSW_SHIFT);
 241 }
 242
 243 static __inline int
 244 fedisableexcept(int __mask)
 245 {
 246         union __fpscr __r;
 247         fenv_t __oldmask;
 248
 249         __mffs(&__r.__d);
 250         __oldmask = __r.__bits.__reg;
 251         __r.__bits.__reg &= ~((__mask & FE_ALL_EXCEPT) >> _FPUSW_SHIFT);
 252         __mtfsf(__r.__d);
 253         return ((__oldmask & _ENABLE_MASK) << _FPUSW_SHIFT);
 254 }
 255
 256 static __inline int
 257 fegetexcept(void)
 258 {
 259         union __fpscr __r;
 260
 261         __mffs(&__r.__d);
 262         return ((__r.__bits.__reg & _ENABLE_MASK) << _FPUSW_SHIFT);
 263 }
 264 #endif /* !STDC_NOINLINE */
 265
 266 #endif /* __BSD_VISIBLE */
 267
 268 __END_DECLS
 269
 270 #endif  /* !_FENV_H_ */