revert between 56095 -> 55830 in arch
[AROS.git] / arch / ppc-all / include / asm / io.h
blobb06eaa18834952f6e79eff32844a1a9e3670f723
1 /*
2 Copyright � 1995-2018, The AROS Development Team. All rights reserved.
3 $Id$
4 */
6 #ifndef ASM_PPC_IO_H
7 #define ASM_PPC_IO_H
9 #include <inttypes.h>
11 static inline uint8_t _inb(volatile uint8_t *port) {
12 uint8_t ret; asm volatile("lbz%U1%X1 %0,%1; eieio":"=r"(ret):"m"(*port)); return ret;
15 static inline void _outb(uint8_t val, volatile uint8_t *port) {
16 asm volatile("stb%U0%X0 %1,%0; eieio"::"m"(*port),"r"(val));
19 static inline uint16_t _inw(volatile uint16_t *port) {
20 uint16_t ret; asm volatile("lhz%U1%X1 %0,%1; eieio":"=r"(ret):"m"(*port)); return ret;
23 static inline void _outw(uint16_t val, volatile uint16_t *port) {
24 asm volatile("sth%U0%X0 %1,%0; eieio"::"m"(*port),"r"(val));
27 static inline uint16_t _inw_be(volatile uint16_t *port) {
28 return _inw(port);
31 static inline void _outw_be(uint16_t val, volatile uint16_t *port) {
32 _outw(val, port);
35 static inline uint16_t _inw_le(volatile uint16_t *port) {
36 uint16_t ret; asm volatile("lhbrx %0,0,%1; eieio":"=r"(ret):"r"(port),"m"(*port)); return ret;
39 static inline void _outw_le(uint16_t val, volatile uint16_t *port) {
40 asm volatile("sthbrx %1,0,%2; eieio":"=m"(*port):"r"(val),"r"(port));
44 static inline uint32_t _inl(volatile uint32_t *port) {
45 uint32_t ret; asm volatile("lwz%U1%X1 %0,%1; eieio":"=r"(ret):"m"(*port)); return ret;
48 static inline void _outl(uint32_t val, volatile uint32_t *port) {
49 asm volatile("stw%U0%X0 %1,%0; eieio"::"m"(*port),"r"(val));
52 static inline uint32_t _inl_be(volatile uint32_t *port) {
53 return _inl(port);
56 static inline void _outl_be(uint32_t val, volatile uint32_t *port) {
57 _outl(val, port);
60 static inline uint32_t _inl_le(volatile uint32_t *port) {
61 uint32_t ret; asm volatile("lwbrx %0,0,%1; eieio":"=r"(ret):"r"(port),"m"(*port)); return ret;
64 static inline void _outl_le(uint32_t val, volatile uint32_t *port) {
65 asm volatile("stwbrx %1,0,%2; eieio":"=m"(*port):"r"(val),"r"(port));
68 #define inb(a) _inb((volatile uint8_t *)(a))
69 #define inw(a) _inw((volatile uint16_t *)(a))
70 #define inl(a) _inl((volatile uint32_t *)(a))
71 #define inw_be(a) _inw_be((volatile uint16_t *)(a))
72 #define inl_be(a) _inl_be((volatile uint32_t *)(a))
73 #define inw_le(a) _inw_le((volatile uint16_t *)(a))
74 #define inl_le(a) _inl_le((volatile uint32_t *)(a))
76 #define outb(v,a) _outb(v,(volatile uint8_t *)(a))
77 #define outw(v,a) _outw(v,(volatile uint16_t *)(a))
78 #define outl(v,a) _outl(v,(volatile uint32_t *)(a))
79 #define outw_be(v,a) _outw_be(v,(volatile uint16_t *)(a))
80 #define outl_be(v,a) _outl_be(v,(volatile uint32_t *)(a))
81 #define outw_le(v,a) _outw_le(v,(volatile uint16_t *)(a))
82 #define outl_le(v,a) _outl_le(v,(volatile uint32_t *)(a))
84 /* This CPU has special little-endian I/O instructions */
85 #define HAVE_LE_IO
87 /* This CPU has special MMIO instructions */
88 #define HAVE_MMIO_IO
90 /* This CPU has special little-endian MMIO instructions */
91 #define HAVE_LE_MMIO_IO
93 /* All I/O on this CPU is memory-mapped */
94 #define mmio_inb(address) inb((uint8_t *)address)
95 #define mmio_inw(address) inw((uint16_t *)address)
96 #define mmio_inl(address) inl((uint32_t *)address)
98 #define mmio_outb(value, address) outb(value, (uint8_t *)address)
99 #define mmio_outw(value, address) outw(value, (uint16_t *)address)
100 #define mmio_outl(value, address) outl(value, (uint32_t *)address)
102 #define mmio_inw_le(address) inw_le((uint16_t *)address)
103 #define mmio_inl_le(address) inl_le((uint32_t *)address)
105 #define mmio_outw_le(value, address) outw_le(value, (uint16_t *)address)
106 #define mmio_outl_le(value, address) outl_le(value, (uint32_t *)address)
108 #endif