rom/devs/ahci/ahci_attach.c

   1 /*
   2  * (MPSAFE)
   3  *
   4  * Copyright (c) 2006 David Gwynne <dlg@openbsd.org>
   5  *
   6  * Permission to use, copy, modify, and distribute this software for any
   7  * purpose with or without fee is hereby granted, provided that the above
   8  * copyright notice and this permission notice appear in all copies.
   9  *
  10  * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
  11  * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
  12  * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
  13  * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
  14  * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
  15  * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF
  16  * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
  17  *
  18  *
  19  * Copyright (c) 2009 The DragonFly Project.  All rights reserved.
  20  *
  21  * This code is derived from software contributed to The DragonFly Project
  22  * by Matthew Dillon <dillon@backplane.com>
  23  *
  24  * Redistribution and use in source and binary forms, with or without
  25  * modification, are permitted provided that the following conditions
  26  * are met:
  27  *
  28  * 1. Redistributions of source code must retain the above copyright
  29  *    notice, this list of conditions and the following disclaimer.
  30  * 2. Redistributions in binary form must reproduce the above copyright
  31  *    notice, this list of conditions and the following disclaimer in
  32  *    the documentation and/or other materials provided with the
  33  *    distribution.
  34  * 3. Neither the name of The DragonFly Project nor the names of its
  35  *    contributors may be used to endorse or promote products derived
  36  *    from this software without specific, prior written permission.
  37  *
  38  * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
  39  * ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
  40  * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS
  41  * FOR A PARTICULAR PURPOSE ARE DISCLAIMED.  IN NO EVENT SHALL THE
  42  * COPYRIGHT HOLDERS OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,
  43  * INCIDENTAL, SPECIAL, EXEMPLARY OR CONSEQUENTIAL DAMAGES (INCLUDING,
  44  * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
  45  * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED
  46  * AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
  47  * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT
  48  * OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
  49  * SUCH DAMAGE.
  50  *
  51  * $OpenBSD: ahci.c,v 1.147 2009/02/16 21:19:07 miod Exp $
  52  */
  53
  54 #include "ahci.h"
  55 #include <exec/rawfmt.h>
  56
  57 extern CONST_STRPTR ahciDeviceName;
  58
  59 static int      ahci_vt8251_attach(device_t);
  60 static int      ahci_ati_sb600_attach(device_t);
  61 static int      ahci_ati_sb700_attach(device_t);
  62 static int      ahci_nvidia_mcp_attach(device_t);
  63 static int      ahci_pci_attach(device_t);
  64 static int      ahci_pci_detach(device_t);
  65
  66 static const struct ahci_device ahci_devices[] = {
  67     { PCI_VENDOR_VIATECH,       PCI_PRODUCT_VIATECH_VT8251_SATA,
  68         ahci_vt8251_attach, ahci_pci_detach, "ViaTech-VT8251-SATA" },
  69     { PCI_VENDOR_ATI,   PCI_PRODUCT_ATI_SB600_SATA,
  70         ahci_ati_sb600_attach, ahci_pci_detach, "ATI-SB600-SATA" },
  71     { PCI_VENDOR_ATI,   PCI_PRODUCT_ATI_SB700_SATA,
  72         ahci_ati_sb700_attach, ahci_pci_detach, "ATI-SB700-SATA" },
  73     { PCI_VENDOR_NVIDIA,        PCI_PRODUCT_NVIDIA_MCP65_AHCI_2,
  74         ahci_nvidia_mcp_attach, ahci_pci_detach, "NVidia-MCP65-SATA" },
  75     { PCI_VENDOR_NVIDIA,        PCI_PRODUCT_NVIDIA_MCP67_AHCI_1,
  76         ahci_nvidia_mcp_attach, ahci_pci_detach, "NVidia-MCP67-SATA" },
  77     { PCI_VENDOR_NVIDIA,        PCI_PRODUCT_NVIDIA_MCP77_AHCI_5,
  78         ahci_nvidia_mcp_attach, ahci_pci_detach, "NVidia-MCP77-SATA" },
  79     { PCI_VENDOR_NVIDIA,        PCI_PRODUCT_NVIDIA_MCP79_AHCI_1,
  80         ahci_nvidia_mcp_attach, ahci_pci_detach, "NVidia-MCP79-SATA" },
  81     { 0, 0,
  82         ahci_pci_attach, ahci_pci_detach, "AHCI-PCI-SATA" }
  83 };
  84
  85 /*
  86  * Match during probe and attach.  The device does not yet have a softc.
  87  */
  88 const struct ahci_device *
  89 ahci_lookup_device(device_t dev)
  90 {
  91     const struct ahci_device *ad;
  92     u_int16_t vendor = pci_get_vendor(dev);
  93     u_int16_t product = pci_get_device(dev);
  94     u_int8_t class = pci_get_class(dev);
  95     u_int8_t subclass = pci_get_subclass(dev);
  96     u_int8_t progif = pci_read_config(dev, PCIR_PROGIF, 1);
  97     int is_ahci;
  98     D(bug("[AHCI] %s()\n", __PRETTY_FUNCTION__));
  99
 100     /*
 101      * Generally speaking if the pci device does not identify as
 102      * AHCI we skip it.
 103      */
 104     if (class == PCIC_STORAGE && subclass == PCIS_STORAGE_SATA &&
 105         progif == PCIP_STORAGE_SATA_AHCI_1_0) {
 106             is_ahci = 1;
 107     } else {
 108             is_ahci = 0;
 109     }
 110
 111     for (ad = &ahci_devices[0]; ad->ad_vendor; ++ad) {
 112             if (ad->ad_vendor == vendor && ad->ad_product == product)
 113                     return (ad);
 114     }
 115
 116     /*
 117      * Last ad is the default match if the PCI device matches SATA.
 118      */
 119     if (is_ahci == 0)
 120             ad = NULL;
 121     return (ad);
 122 }
 123
 124 /*
 125  * Attach functions.  They all eventually fall through to ahci_pci_attach().
 126  */
 127 static int
 128 ahci_vt8251_attach(device_t dev)
 129 {
 130     struct ahci_softc *sc = device_get_softc(dev);
 131     D(bug("[AHCI] %s()\n", __PRETTY_FUNCTION__));
 132
 133     sc->sc_flags |= AHCI_F_NO_NCQ;
 134     return (ahci_pci_attach(dev));
 135 }
 136
 137 static int
 138 ahci_ati_sb600_attach(device_t dev)
 139 {
 140     struct ahci_softc *sc = device_get_softc(dev);
 141     pcireg_t magic;
 142     u_int8_t subclass = pci_get_subclass(dev);
 143     u_int8_t revid;
 144     D(bug("[AHCI] %s()\n", __PRETTY_FUNCTION__));
 145
 146     if (subclass == PCIS_STORAGE_IDE) {
 147         revid = pci_read_config(dev, PCIR_REVID, 1);
 148         magic = pci_read_config(dev, AHCI_PCI_ATI_SB600_MAGIC, 4);
 149         pci_write_config(dev, AHCI_PCI_ATI_SB600_MAGIC,
 150                          magic | AHCI_PCI_ATI_SB600_LOCKED, 4);
 151         pci_write_config(dev, PCIR_REVID,
 152                          (PCIC_STORAGE << 24) |
 153                          (PCIS_STORAGE_SATA << 16) |
 154                          (PCIP_STORAGE_SATA_AHCI_1_0 << 8) |
 155                          revid, 4);
 156         pci_write_config(dev, AHCI_PCI_ATI_SB600_MAGIC, magic, 4);
 157     }
 158
 159     sc->sc_flags |= AHCI_F_IGN_FR;
 160     return (ahci_pci_attach(dev));
 161 }
 162
 163 static int
 164 ahci_ati_sb700_attach(device_t dev)
 165 {
 166     struct ahci_softc *sc = device_get_softc(dev);
 167     D(bug("[AHCI] %s()\n", __PRETTY_FUNCTION__));
 168
 169     sc->sc_flags |= AHCI_F_IGN_FR;
 170     sc->sc_flags |= AHCI_F_NO_PM;
 171     return (ahci_pci_attach(dev));
 172 }
 173
 174 static int
 175 ahci_nvidia_mcp_attach(device_t dev)
 176 {
 177     struct ahci_softc *sc = device_get_softc(dev);
 178     D(bug("[AHCI] %s()\n", __PRETTY_FUNCTION__));
 179
 180     sc->sc_flags |= AHCI_F_IGN_FR;
 181     return (ahci_pci_attach(dev));
 182 }
 183
 184 static int
 185 ahci_pci_attach(device_t dev)
 186 {
 187         struct AHCIBase *AHCIBase = dev->dev_AHCIBase;
 188         struct ahci_softc *sc = device_get_softc(dev);
 189         struct ahci_port *ap;
 190         u_int32_t pi, reg;
 191         u_int32_t cap, cap2;
 192         bus_addr_t addr;
 193         int i;
 194         int error, fbs;
 195 #if !defined(__AROS__)
 196         const char *revision;
 197         const char *gen;
 198 #else
 199 # define revision       dev->dev_revision
 200 # define gen                    dev->dev_gen
 201 #endif
 202
 203         D(bug("[AHCI] %s()\n", __PRETTY_FUNCTION__));
 204
 205         if (pci_read_config(dev, PCIR_COMMAND, 2) & 0x0400) {
 206                 device_printf(dev, "BIOS disabled PCI interrupt, "
 207                                    "re-enabling\n");
 208                 pci_write_config(dev, PCIR_COMMAND,
 209                         pci_read_config(dev, PCIR_COMMAND, 2) & ~0x0400, 2);
 210         }
 211
 212
 213         /*
 214          * Map the AHCI controller's IRQ and BAR(5) (hardware registers)
 215          */
 216         sc->sc_dev = dev;
 217         sc->sc_rid_irq = AHCI_IRQ_RID;
 218         sc->sc_irq = bus_alloc_resource_any(dev, SYS_RES_IRQ, &sc->sc_rid_irq,
 219                                             RF_SHAREABLE | RF_ACTIVE);
 220         if (sc->sc_irq == NULL) {
 221                 device_printf(dev, "unable to map interrupt\n");
 222                 ahci_pci_detach(dev);
 223                 return (ENXIO);
 224         }
 225
 226         /*
 227          * When mapping the register window store the tag and handle
 228          * separately so we can use the tag with per-port bus handle
 229          * sub-spaces.
 230          */
 231         sc->sc_rid_regs = PCIR_BAR(5);
 232         sc->sc_regs = bus_alloc_resource_any(dev, SYS_RES_MEMORY,
 233                                              &sc->sc_rid_regs, RF_ACTIVE);
 234         if (sc->sc_regs == NULL) {
 235                 device_printf(dev, "unable to map registers\n");
 236                 ahci_pci_detach(dev);
 237                 return (ENXIO);
 238         }
 239         sc->sc_iot = rman_get_bustag(sc->sc_regs);
 240         sc->sc_ioh = rman_get_bushandle(sc->sc_regs);
 241
 242         /*
 243          * Initialize the chipset and then set the interrupt vector up
 244          */
 245         device_printf(dev, "device flags 0x%x\n", sc->sc_flags);
 246         error = ahci_init(sc);
 247         if (error) {
 248                 ahci_pci_detach(dev);
 249                 return (ENXIO);
 250         }
 251
 252         /*
 253          * Get the AHCI capabilities and max number of concurrent
 254          * command tags and set up the DMA tags.  Adjust the saved
 255          * sc_cap according to override flags.
 256          */
 257         cap = sc->sc_cap = ahci_read(sc, AHCI_REG_CAP);
 258         if (sc->sc_flags & AHCI_F_NO_NCQ)
 259                 sc->sc_cap &= ~AHCI_REG_CAP_SNCQ;
 260         if (sc->sc_flags & AHCI_F_NO_PM)
 261                 cap &= ~AHCI_REG_CAP_SPM;
 262         if (sc->sc_flags & AHCI_F_FORCE_FBSS)
 263                 sc->sc_cap |= AHCI_REG_CAP_FBSS;
 264
 265         /*
 266          * We assume at least 4 commands.
 267          */
 268         sc->sc_ncmds = AHCI_REG_CAP_NCS(cap);
 269         if (sc->sc_ncmds < 4) {
 270                 device_printf(dev, "NCS must probe a value >= 4\n");
 271                 ahci_pci_detach(dev);
 272                 return (ENXIO);
 273         }
 274
 275         addr = (cap & AHCI_REG_CAP_S64A) ?
 276                 BUS_SPACE_MAXADDR : BUS_SPACE_MAXADDR_32BIT;
 277
 278         /*
 279          * DMA tags for allocation of DMA memory buffers, lists, and so
 280          * forth.  These are typically per-port.
 281          *
 282          * When FIS-based switching is supported we need a rfis for
 283          * each target (4K total).  The spec also requires 4K alignment
 284          * for this case.
 285          */
 286         fbs = (cap & AHCI_REG_CAP_FBSS) ? 16 : 1;
 287         error = 0;
 288
 289         error += bus_dma_tag_create(
 290                         NULL,                           /* parent tag */
 291                         256 * fbs,                      /* alignment */
 292                         PAGE_SIZE,                      /* boundary */
 293                         addr,                           /* loaddr? */
 294                         BUS_SPACE_MAXADDR,              /* hiaddr */
 295                         NULL,                           /* filter */
 296                         NULL,                           /* filterarg */
 297                         sizeof(struct ahci_rfis) * fbs, /* [max]size */
 298                         1,                              /* maxsegs */
 299                         sizeof(struct ahci_rfis) * fbs, /* maxsegsz */
 300                         0,                              /* flags */
 301                         &sc->sc_tag_rfis);              /* return tag */
 302
 303         error += bus_dma_tag_create(
 304                         NULL,                           /* parent tag */
 305                         32,                             /* alignment */
 306                         1024,                           /* boundary */
 307                         addr,                           /* loaddr? */
 308                         BUS_SPACE_MAXADDR,              /* hiaddr */
 309                         NULL,                           /* filter */
 310                         NULL,                           /* filterarg */
 311                         sc->sc_ncmds * sizeof(struct ahci_cmd_hdr),
 312                         1,                              /* maxsegs */
 313                         sc->sc_ncmds * sizeof(struct ahci_cmd_hdr),
 314                         0,                              /* flags */
 315                         &sc->sc_tag_cmdh);              /* return tag */
 316
 317         /*
 318          * NOTE: ahci_cmd_table is sized to a power of 2
 319          */
 320         error += bus_dma_tag_create(
 321                         NULL,                           /* parent tag */
 322                         sizeof(struct ahci_cmd_table),  /* alignment */
 323                         1024,                           /* boundary */
 324                         addr,                           /* loaddr? */
 325                         BUS_SPACE_MAXADDR,              /* hiaddr */
 326                         NULL,                           /* filter */
 327                         NULL,                           /* filterarg */
 328                         sc->sc_ncmds * sizeof(struct ahci_cmd_table),
 329                         1,                              /* maxsegs */
 330                         sc->sc_ncmds * sizeof(struct ahci_cmd_table),
 331                         0,                              /* flags */
 332                         &sc->sc_tag_cmdt);              /* return tag */
 333
 334         /*
 335          * The data tag is used for later dmamaps and not immediately
 336          * allocated.
 337          */
 338         error += bus_dma_tag_create(
 339                         NULL,                           /* parent tag */
 340                         4,                              /* alignment */
 341                         0,                              /* boundary */
 342                         addr,                           /* loaddr? */
 343                         BUS_SPACE_MAXADDR,              /* hiaddr */
 344                         NULL,                           /* filter */
 345                         NULL,                           /* filterarg */
 346                         4096 * 1024,                    /* maxiosize */
 347                         AHCI_MAX_PRDT,                  /* maxsegs */
 348                         65536,                          /* maxsegsz */
 349                         0,                              /* flags */
 350                         &sc->sc_tag_data);              /* return tag */
 351
 352         if (error) {
 353                 device_printf(dev, "unable to create dma tags\n");
 354                 ahci_pci_detach(dev);
 355                 return (ENXIO);
 356         }
 357
 358         switch (cap & AHCI_REG_CAP_ISS) {
 359         case AHCI_REG_CAP_ISS_G1:
 360                 gen = "1 (1.5Gbps)";
 361                 break;
 362         case AHCI_REG_CAP_ISS_G2:
 363                 gen = "2 (3Gbps)";
 364                 break;
 365         case AHCI_REG_CAP_ISS_G3:
 366                 gen = "3 (6Gbps)";
 367                 break;
 368         default:
 369                 gen = "unknown";
 370                 break;
 371         }
 372
 373         /* check the revision */
 374         reg = ahci_read(sc, AHCI_REG_VS);
 375
 376         switch (reg) {
 377         case AHCI_REG_VS_0_95:
 378                 revision = "AHCI 0.95";
 379                 break;
 380         case AHCI_REG_VS_1_0:
 381                 revision = "AHCI 1.0";
 382                 break;
 383         case AHCI_REG_VS_1_1:
 384                 revision = "AHCI 1.1";
 385                 break;
 386         case AHCI_REG_VS_1_2:
 387                 revision = "AHCI 1.2";
 388                 break;
 389         case AHCI_REG_VS_1_3:
 390                 revision = "AHCI 1.3";
 391                 break;
 392         case AHCI_REG_VS_1_4:
 393                 revision = "AHCI 1.4";
 394                 break;
 395         case AHCI_REG_VS_1_5:
 396                 revision = "AHCI 1.5";  /* future will catch up to us */
 397                 break;
 398         default:
 399                 device_printf(sc->sc_dev,
 400                               "Warning: Unknown AHCI revision 0x%08x\n", reg);
 401                 revision = "AHCI <unknown>";
 402                 break;
 403         }
 404         sc->sc_vers = reg;
 405
 406         if (reg >= AHCI_REG_VS_1_3) {
 407                 cap2 = ahci_read(sc, AHCI_REG_CAP2);
 408                 device_printf(dev,
 409                               "%s cap 0x%b cap2 0x%b, %d ports, "
 410                               "%d tags/port, gen %s\n",
 411                               revision,
 412                               cap, AHCI_FMT_CAP,
 413                               cap2, AHCI_FMT_CAP2,
 414                               AHCI_REG_CAP_NP(cap), sc->sc_ncmds, gen);
 415         } else {
 416                 cap2 = 0;
 417                 device_printf(dev,
 418                               "%s cap 0x%b, %d ports, "
 419                               "%d tags/port, gen %s\n",
 420                               revision,
 421                               cap, AHCI_FMT_CAP,
 422                               AHCI_REG_CAP_NP(cap), sc->sc_ncmds, gen);
 423         }
 424         sc->sc_cap2 = cap2;
 425
 426         pi = ahci_read(sc, AHCI_REG_PI);
 427         DPRINTF(AHCI_D_VERBOSE, "%s: ports implemented: 0x%08x\n",
 428             DEVNAME(sc), pi);
 429
 430 #ifdef AHCI_COALESCE
 431         /* Naive coalescing support - enable for all ports. */
 432         if (cap & AHCI_REG_CAP_CCCS) {
 433                 u_int16_t               ccc_timeout = 20;
 434                 u_int8_t                ccc_numcomplete = 12;
 435                 u_int32_t               ccc_ctl;
 436
 437                 /* disable coalescing during reconfiguration. */
 438                 ccc_ctl = ahci_read(sc, AHCI_REG_CCC_CTL);
 439                 ccc_ctl &= ~0x00000001;
 440                 ahci_write(sc, AHCI_REG_CCC_CTL, ccc_ctl);
 441
 442                 sc->sc_ccc_mask = 1 << AHCI_REG_CCC_CTL_INT(ccc_ctl);
 443                 if (pi & sc->sc_ccc_mask) {
 444                         /* A conflict with the implemented port list? */
 445                         kprintf("%s: coalescing interrupt/implemented port list "
 446                             "conflict, PI: %08x, ccc_mask: %08x\n",
 447                             DEVNAME(sc), pi, sc->sc_ccc_mask);
 448                         sc->sc_ccc_mask = 0;
 449                         goto noccc;
 450                 }
 451
 452                 /* ahci_port_start will enable each port when it starts. */
 453                 sc->sc_ccc_ports = pi;
 454                 sc->sc_ccc_ports_cur = 0;
 455
 456                 /* program thresholds and enable overall coalescing. */
 457                 ccc_ctl &= ~0xffffff00;
 458                 ccc_ctl |= (ccc_timeout << 16) | (ccc_numcomplete << 8);
 459                 ahci_write(sc, AHCI_REG_CCC_CTL, ccc_ctl);
 460                 ahci_write(sc, AHCI_REG_CCC_PORTS, 0);
 461                 ahci_write(sc, AHCI_REG_CCC_CTL, ccc_ctl | 1);
 462         }
 463 noccc:
 464 #endif
 465         /*
 466          * Allocate per-port resources
 467          *
 468          * Ignore attach errors, leave the port intact for
 469          * rescan and continue the loop.
 470          *
 471          * All ports are attached in parallel but the CAM scan-bus
 472          * is held up until all ports are attached so we get a deterministic
 473          * order.
 474          */
 475         for (i = 0; error == 0 && i < AHCI_MAX_PORTS; i++) {
 476             D(bug("[AHCI] %s: checking port %d\n", __PRETTY_FUNCTION__, i));
 477             if ((pi & (1 << i)) == 0) {
 478                 /* dont allocate stuff if the port isnt implemented */
 479                 continue;
 480             }
 481             error = ahci_port_alloc(sc, i);
 482             if (error == 0)
 483             {
 484                 struct TagItem attrs[] =
 485                 {
 486                         {aHidd_Name             , (IPTR)ahciDeviceName          },
 487                         {aHidd_HardwareName     , 0                             },
 488 #define PORT_TAG_HARDWARENAME 1
 489                         {aHidd_Producer         , 0                             },
 490 #define PORT_TAG_PRODUCER 2
 491                         {aHidd_Product          , 0                             },
 492 #define PORT_TAG_PRODUCT 3
 493                         {aHidd_DriverData       , (IPTR)sc->sc_ports[i]         },
 494                         {TAG_DONE               , 0                             }
 495                 };
 496                 STRPTR name;
 497                 IPTR str[1];
 498                 OOP_Object *bus;
 499
 500                 D(bug("[AHCI] %s: port @ 0x%p\n", __PRETTY_FUNCTION__, sc->sc_ports[i]));
 501                 name = (char *)AllocVec(20, MEMF_CLEAR);
 502                 str[0] = i;
 503                 RawDoFmt("AHCI channel #%d", (RAWARG)str, RAWFMTFUNC_STRING, name);
 504                 attrs[PORT_TAG_HARDWARENAME].ti_Data = (IPTR)name;
 505
 506                 if ((attrs[PORT_TAG_PRODUCER].ti_Data = sc->sc_ad->ad_vendor) == 0)
 507                         attrs[PORT_TAG_PRODUCER].ti_Data = pci_get_vendor(dev);
 508                 if ((attrs[PORT_TAG_PRODUCT].ti_Data = sc->sc_ad->ad_product) == 0)
 509                         attrs[PORT_TAG_PRODUCT].ti_Data = pci_get_device(dev);
 510
 511                 D(bug("[AHCI] %s: Registering '%s' with controller @ 0x%p\n", __PRETTY_FUNCTION__, name, dev->dev_Controller));
 512                 bus = HW_AddDriver(dev->dev_Controller, AHCIBase->busClass, attrs);
 513                 if (!bus)
 514                 {
 515                     device_printf(dev,
 516                       "Failed to create Bus object for device %04X:%04X port %d\n",
 517                       attrs[PORT_TAG_PRODUCER].ti_Data, attrs[PORT_TAG_PRODUCT].ti_Data, i);
 518                 }
 519                 D(bug("[AHCI] %s: Bus Obj @ 0x%p\n", __PRETTY_FUNCTION__, bus));
 520             }
 521             else
 522             {
 523                 D(bug("[AHCI] %s: Failed to alloc port\n", __PRETTY_FUNCTION__));
 524             }
 525         }
 526
 527         /*
 528          * Setup the interrupt vector and enable interrupts.  Note that
 529          * since the irq may be shared we do not set it up until we are
 530          * ready to go.
 531          */
 532         if (error == 0) {
 533             error = bus_setup_intr(dev, sc->sc_irq, INTR_MPSAFE,
 534                                    ahci_intr, sc,
 535                                    &sc->sc_irq_handle, NULL);
 536         }
 537
 538         if (error) {
 539             device_printf(dev, "unable to install interrupt\n");
 540             ahci_pci_detach(dev);
 541             return (ENXIO);
 542         }
 543
 544         /*
 545          * Before marking the sc as good, which allows the interrupt
 546          * subsystem to operate on the ports, wait for all the port threads
 547          * to get past their initial pre-probe init.  Otherwise an interrupt
 548          * may try to process the port before it has been initialized.
 549          */
 550         for (i = 0; i < AHCI_MAX_PORTS; i++) {
 551             if ((ap = sc->sc_ports[i]) != NULL) {
 552                 while (ap->ap_signal & AP_SIGF_THREAD_SYNC)
 553                     ahci_os_sleep(100);
 554             }
 555         }
 556
 557         /*
 558          * Master interrupt enable, and call ahci_intr() in case we race
 559          * our AHCI_F_INT_GOOD flag.
 560          */
 561         crit_enter();
 562         ahci_write(sc, AHCI_REG_GHC, AHCI_REG_GHC_AE | AHCI_REG_GHC_IE);
 563         sc->sc_flags |= AHCI_F_INT_GOOD;
 564         crit_exit();
 565         ahci_intr(sc);
 566
 567         /*
 568          * All ports are probing in parallel.  Wait for them to finish
 569          * and then issue the cam attachment and bus scan serially so
 570          * the 'da' assignments are deterministic.
 571          */
 572         for (i = 0; i < AHCI_MAX_PORTS; i++) {
 573                 if ((ap = sc->sc_ports[i]) != NULL) {
 574                         while (ap->ap_signal & AP_SIGF_INIT)
 575                             ahci_os_sleep(100);
 576                         ahci_os_lock_port(ap);
 577                         if (ahci_cam_attach(ap) == 0) {
 578                                 ahci_cam_changed(ap, NULL, -1);
 579                                 ahci_os_unlock_port(ap);
 580                                 while ((ap->ap_flags & AP_F_SCAN_COMPLETED) == 0) {
 581                                         ahci_os_sleep(100);
 582                                 }
 583                         } else {
 584                                 ahci_os_unlock_port(ap);
 585                         }
 586                 }
 587         }
 588 #if defined(__AROS__)
 589 # undef revision
 590 # undef gen
 591 #endif
 592
 593         D(bug("[AHCI] %s: done\n", __PRETTY_FUNCTION__));
 594         return(0);
 595 }
 596
 597 /*
 598  * Device unload / detachment
 599  */
 600 static int
 601 ahci_pci_detach(device_t dev)
 602 {
 603         struct ahci_softc *sc = device_get_softc(dev);
 604         struct ahci_port *ap;
 605         int     i;
 606
 607         D(bug("[AHCI] %s()\n", __PRETTY_FUNCTION__));
 608
 609         /*
 610          * Disable the controller and de-register the interrupt, if any.
 611          *
 612          * XXX interlock last interrupt?
 613          */
 614         sc->sc_flags &= ~AHCI_F_INT_GOOD;
 615         if (sc->sc_regs)
 616                 ahci_write(sc, AHCI_REG_GHC, 0);
 617
 618         if (sc->sc_irq_handle) {
 619                 bus_teardown_intr(dev, sc->sc_irq, sc->sc_irq_handle);
 620                 sc->sc_irq_handle = NULL;
 621         }
 622
 623         /*
 624          * Free port structures and DMA memory
 625          */
 626         for (i = 0; i < AHCI_MAX_PORTS; i++) {
 627                 ap = sc->sc_ports[i];
 628                 if (ap) {
 629                         ahci_cam_detach(ap);
 630                         ahci_port_free(sc, i);
 631                 }
 632         }
 633
 634         /*
 635          * Clean up the bus space
 636          */
 637         if (sc->sc_irq) {
 638                 bus_release_resource(dev, SYS_RES_IRQ,
 639                                      sc->sc_rid_irq, sc->sc_irq);
 640                 sc->sc_irq = NULL;
 641         }
 642         if (sc->sc_regs) {
 643                 bus_release_resource(dev, SYS_RES_MEMORY,
 644                                      sc->sc_rid_regs, sc->sc_regs);
 645                 sc->sc_regs = NULL;
 646         }
 647
 648         if (sc->sc_tag_rfis) {
 649                 bus_dma_tag_destroy(sc->sc_tag_rfis);
 650                 sc->sc_tag_rfis = NULL;
 651         }
 652         if (sc->sc_tag_cmdh) {
 653                 bus_dma_tag_destroy(sc->sc_tag_cmdh);
 654                 sc->sc_tag_cmdh = NULL;
 655         }
 656         if (sc->sc_tag_cmdt) {
 657                 bus_dma_tag_destroy(sc->sc_tag_cmdt);
 658                 sc->sc_tag_cmdt = NULL;
 659         }
 660         if (sc->sc_tag_data) {
 661                 bus_dma_tag_destroy(sc->sc_tag_data);
 662                 sc->sc_tag_data = NULL;
 663         }
 664
 665         return (0);
 666 }