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revert between 56095 -> 55830 in arch
[AROS.git] / rom / devs / ata / lowlevel.c
blob35c5c849ebab76c95374c18d17f18b1caa0f2a13
1 /*
2 Copyright © 2004-2018, The AROS Development Team. All rights reserved.
3 $Id$
4
5 Desc:
6 Lang: English
7 */
8
9 /*
10 * TODO:
11 * - put a critical section around DMA transfers (shared dma channels)
12 */
13
14 #include <aros/debug.h>
15
16 #include <proto/exec.h>
17
18 #include <exec/types.h>
19 #include <exec/exec.h>
20 #include <exec/resident.h>
21 #include <utility/utility.h>
22 #include <oop/oop.h>
23
24 #include <devices/timer.h>
25
26 #include "ata.h"
27 #include "ata_bus.h"
28 #include "timer.h"
29
30 // use #define xxx(a) D(a) to enable particular sections.
31 #if DEBUG
32 #define DIRQ(a) D(a)
33 #define DIRQ_MORE(a)
34 #define DUMP(a) D(a)
35 #define DUMP_MORE(a)
36 #define DATA(a) D(a)
37 #define DATAPI(a) D(a)
38 #define DINIT(a) D(a)
39 #else
40 #define DIRQ(a) do { } while (0)
41 #define DIRQ_MORE(a) do { } while (0)
42 #define DUMP(a) do { } while (0)
43 #define DUMP_MORE(a) do { } while (0)
44 #define DATA(a) do { } while (0)
45 #define DATAPI(a) do { } while (0)
46 #define DINIT(a)
47 #endif
48 /* Errors that shouldn't happen */
49 #define DERROR(a) a
50
51 static BYTE ata_Identify(struct ata_Unit *unit);
52 static BYTE ata_ReadSector32(struct ata_Unit *, ULONG, ULONG, APTR, ULONG *);
53 static BYTE ata_ReadSector64(struct ata_Unit *, UQUAD, ULONG, APTR, ULONG *);
54 static BYTE ata_ReadMultiple32(struct ata_Unit *, ULONG, ULONG, APTR, ULONG *);
55 static BYTE ata_ReadMultiple64(struct ata_Unit *, UQUAD, ULONG, APTR, ULONG *);
56 static BYTE ata_ReadDMA32(struct ata_Unit *, ULONG, ULONG, APTR, ULONG *);
57 static BYTE ata_ReadDMA64(struct ata_Unit *, UQUAD, ULONG, APTR, ULONG *);
58 static BYTE ata_WriteSector32(struct ata_Unit *, ULONG, ULONG, APTR, ULONG *);
59 static BYTE ata_WriteSector64(struct ata_Unit *, UQUAD, ULONG, APTR, ULONG *);
60 static BYTE ata_WriteMultiple32(struct ata_Unit *, ULONG, ULONG, APTR, ULONG *);
61 static BYTE ata_WriteMultiple64(struct ata_Unit *, UQUAD, ULONG, APTR, ULONG *);
62 static BYTE ata_WriteDMA32(struct ata_Unit *, ULONG, ULONG, APTR, ULONG *);
63 static BYTE ata_WriteDMA64(struct ata_Unit *, UQUAD, ULONG, APTR, ULONG *);
64 static void ata_ResetBus(struct ata_Bus *bus);
65 static BYTE ata_Eject(struct ata_Unit *);
66 static BOOL ata_WaitBusyTO(struct ata_Unit *unit, UWORD tout, BOOL irq,
67 BOOL fake_irq, UBYTE *stout);
68
69 static BYTE atapi_SendPacket(struct ata_Unit *unit, APTR packet, APTR data,
70 LONG datalen, BOOL *dma, BOOL write);
71 static BYTE atapi_DirectSCSI(struct ata_Unit *unit, struct SCSICmd *cmd);
72 static BYTE atapi_Read(struct ata_Unit *, ULONG, ULONG, APTR, ULONG *);
73 static BYTE atapi_Write(struct ata_Unit *, ULONG, ULONG, APTR, ULONG *);
74 static BYTE atapi_Eject(struct ata_Unit *);
75 static ULONG atapi_RequestSense(struct ata_Unit* unit, UBYTE* sense,
76 ULONG senselen);
77 static BYTE atapi_EndCmd(struct ata_Unit *unit);
78
79 static void common_SetBestXferMode(struct ata_Unit* unit);
80
81 #define DEVHEAD_VAL 0xe0
82
83 #if DEBUG
84 static void dump(APTR mem, ULONG len)
85 {
86 register int i, j = 0;
87
88 DUMP_MORE(for (j=0; j<(len+15)>>4; ++j))
89 {
90 bug("[ATA ] %06lx: ", j<<4);
91
92 for (i=0; i<len-(j<<4); i++)
93 {
94 bug("%02lx ", ((unsigned char*)mem)[(j<<4)|i]);
95 if (i == 15)
96 break;
97 }
98
99 for (i=0; i<len-(j<<4); i++)
100 {
101 unsigned char c = ((unsigned char*)mem)[(j<<4)|i];
102
103 bug("%c", c >= 0x20 ? c<=0x7f ? c : '.' : '.');
104 if (i == 15)
105 break;
106 }
107 bug("\n");
108 }
109 }
110 #endif
111
112 static void ata_strcpy(const UBYTE *str1, UBYTE *str2, ULONG size)
113 {
114 register int i = size;
115
116 while (size--)
117 str2[size ^ 1] = str1[size];
118
119 while (i > 0 && str2[--i] <= ' ')
120 str2[i] = '\0';
121 }
122
123 static inline struct ata_Unit* ata_GetSelectedUnit(struct ata_Bus* bus)
124 {
125 return bus->ab_SelectedUnit;
126 }
127
128 static inline UBYTE ata_ReadStatus(struct ata_Bus *bus)
129 {
130 return PIO_In(bus, ata_Status);
131 }
132
133 static inline UBYTE ata_ReadAltStatus(struct ata_Bus *bus)
134 {
135 return PIO_InAlt(bus, ata_AltStatus);
136 }
137
138 static inline BOOL ata_SelectUnit(struct ata_Unit* unit)
139 {
140 struct ata_Bus *bus = unit->au_Bus;
141
142 if (unit == bus->ab_SelectedUnit)
143 return TRUE;
144
145 PIO_Out(bus, unit->au_DevMask, ata_DevHead);
146
147 do
148 {
149 ata_WaitNano(400, bus->ab_Base);
150 //ata_WaitTO(unit->au_Bus->ab_Timer, 0, 1, 0);
151 }
152 while (0 != (ATAF_BUSY & ata_ReadStatus(bus)));
153
154 bus->ab_SelectedUnit = unit;
155
156 return TRUE;
157 }
158
159 /*
160 * handle IRQ; still fast and efficient, supposed to verify if this irq is for us and take adequate steps
161 * part of code moved here from ata.c to reduce containment
162 */
163 static void ata_IRQSignalTask(struct ata_Bus *bus)
164 {
165 bus->ab_IntCnt++;
166 Signal(bus->ab_Task, 1UL << bus->ab_SleepySignal);
167 }
168
169 static void ata_IRQSetHandler(struct ata_Unit *unit,
170 void (*handler)(struct ata_Unit*, UBYTE), APTR piomem, ULONG blklen,
171 ULONG piolen)
172 {
173 if (NULL != handler)
174 unit->au_cmd_error = 0;
175
176 unit->au_cmd_data = piomem;
177 unit->au_cmd_length = (piolen < blklen) ? piolen : blklen;
178 unit->au_cmd_total = piolen;
179 unit->au_Bus->ab_HandleIRQ = handler;
180 }
181
182 static void ata_IRQNoData(struct ata_Unit *unit, UBYTE status)
183 {
184 if (status & ATAF_BUSY)
185 return;
186
187 if ((unit->au_cmd_error == 0) && (status & ATAF_ERROR))
188 unit->au_cmd_error = HFERR_BadStatus;
189
190 DIRQ(bug("[ATA%02ld] IRQ: NoData - done; status %02lx.\n", unit->au_UnitNum, status));
191 ata_IRQSetHandler(unit, NULL, NULL, 0, 0);
192 ata_IRQSignalTask(unit->au_Bus);
193 }
194
195 static void ata_IRQPIORead(struct ata_Unit *unit, UBYTE status)
196 {
197 if (status & ATAF_DATAREQ)
198 {
199 DIRQ(bug("[ATA%02ld] IRQ: PIOReadData - DRQ.\n", unit->au_UnitNum));
200
201 Unit_InS(unit, unit->au_cmd_data, unit->au_cmd_length);
202
203 /*
204 * Adjust data pointer and counter. If there's more data left for
205 * this transfer, keep same handler and wait for next interrupt
206 */
207 unit->au_cmd_data += unit->au_cmd_length;
208 unit->au_cmd_total -= unit->au_cmd_length;
209 if (unit->au_cmd_total != 0)
210 {
211 if (unit->au_cmd_length > unit->au_cmd_total)
212 unit->au_cmd_length = unit->au_cmd_total;
213 return;
214 }
215 DIRQ(bug("[ATA%02ld] IRQ: PIOReadData - transfer completed.\n",
216 unit->au_UnitNum));
217 }
218 else
219 unit->au_cmd_error = HFERR_BadStatus;
220 ata_IRQNoData(unit, status);
221 }
222
223 static void ata_PIOWriteBlk(struct ata_Unit *unit)
224 {
225 Unit_OutS(unit, unit->au_cmd_data, unit->au_cmd_length);
226
227 /*
228 * Adjust data pointer and counter
229 */
230 unit->au_cmd_data += unit->au_cmd_length;
231 unit->au_cmd_total -= unit->au_cmd_length;
232 if (unit->au_cmd_length > unit->au_cmd_total)
233 unit->au_cmd_length = unit->au_cmd_total;
234 }
235
236 static void ata_IRQPIOWrite(struct ata_Unit *unit, UBYTE status)
237 {
238 /*
239 * If there's more data left for this transfer, write it, keep same
240 * handler and wait for next interrupt
241 */
242 if (status & ATAF_DATAREQ) {
243 DIRQ(bug("[ATA%02ld] IRQ: PIOWriteData - DRQ.\n", unit->au_UnitNum));
244 ata_PIOWriteBlk(unit);
245 return;
246 }
247 else if (unit->au_cmd_total != 0)
248 unit->au_cmd_error = HFERR_BadStatus;
249 DIRQ(bug("[ATA%02ld] IRQ: PIOWriteData - done.\n", unit->au_UnitNum));
250 ata_IRQNoData(unit, status);
251 }
252
253 static void ata_IRQDMAReadWrite(struct ata_Unit *unit, UBYTE status)
254 {
255 struct ata_Bus *bus = unit->au_Bus;
256 ULONG stat = DMA_GetResult(bus);
257
258 DIRQ(bug("[ATA%02ld] IRQ: IO status %02lx, DMA status %02lx\n", unit->au_UnitNum, status, stat));
259
260 if ((status & ATAF_ERROR) || stat)
261 {
262 /* This is turned on in order to help Phantom - Pavel Fedin <sonic_amiga@rambler.ru> */
263 DERROR(bug("[ATA%02ld] IRQ: IO status %02lx, DMA status %d\n", unit->au_UnitNum, status, stat));
264 DERROR(bug("[ATA%02ld] IRQ: ERROR %02lx\n", unit->au_UnitNum, PIO_In(bus, atapi_Error)));
265 DERROR(bug("[ATA%02ld] IRQ: DMA Failed.\n", unit->au_UnitNum));
266
267 unit->au_cmd_error = stat;
268 ata_IRQNoData(unit, status);
269 }
270 else if (0 == (status & (ATAF_BUSY | ATAF_DATAREQ)))
271 {
272 DIRQ(bug("[ATA%02ld] IRQ: DMA Done.\n", unit->au_UnitNum));
273 ata_IRQNoData(unit, status);
274 }
275 }
276
277 static void ata_IRQPIOReadAtapi(struct ata_Unit *unit, UBYTE status)
278 {
279 struct ata_Bus *bus = unit->au_Bus;
280 ULONG size = 0;
281 LONG remainder = 0;
282 UBYTE reason = PIO_In(bus, atapi_Reason);
283 DIRQ(bug("[ATAPI] Current status: %ld during READ\n", reason));
284
285 /* have we failed yet? */
286 if (0 == (status & (ATAF_BUSY | ATAF_DATAREQ)))
287 ata_IRQNoData(unit, status);
288 if (status & ATAF_ERROR)
289 {
290 ata_IRQNoData(unit, status);
291 return;
292 }
293
294 /* anything for us please? */
295 if (ATAPIF_READ != (reason & ATAPIF_MASK))
296 return;
297
298 size = PIO_In(bus, atapi_ByteCntH) << 8 | PIO_In(bus, atapi_ByteCntL);
299 DIRQ(bug("[ATAPI] IRQ: data available for read (%ld bytes, max: %ld bytes)\n", size, unit->au_cmd_total));
300
301 if (size > unit->au_cmd_total)
302 {
303 DERROR(bug("[ATAPI] IRQ: CRITICAL! MORE DATA OFFERED THAN STORAGE CAN TAKE: %ld bytes vs %ld bytes left!\n", size, unit->au_cmd_total));
304 remainder = size - unit->au_cmd_total;
305 size = unit->au_cmd_total;
306 }
307
308 Unit_InS(unit, unit->au_cmd_data, size);
309
310 unit->au_cmd_data = &((UBYTE*)unit->au_cmd_data)[size];
311 unit->au_cmd_total -= size;
312
313 DIRQ(bug("[ATAPI] IRQ: %lu bytes read.\n", size));
314
315 /*
316 * Soak up excess bytes.
317 */
318 for (; remainder > 0; remainder -= 2)
319 Unit_InS(unit, &size, 2);
320
321 if (unit->au_cmd_total == 0)
322 ata_IRQSetHandler(unit, &ata_IRQNoData, NULL, 0, 0);
323 }
324
325 static void ata_IRQPIOWriteAtapi(struct ata_Unit *unit, UBYTE status)
326 {
327 struct ata_Bus *bus = unit->au_Bus;
328 ULONG size = 0;
329 UBYTE reason = PIO_In(bus, atapi_Reason);
330
331 DIRQ(bug("[ATAPI] IRQ: Current status: %ld during WRITE\n", reason));
332
333 /*
334 * have we failed yet?
335 * CHECKME: This sequence actually can trigger ata_IRQNoData() twice.
336 * Is this correct ?
337 */
338 if (0 == (status & (ATAF_BUSY | ATAF_DATAREQ)))
339 ata_IRQNoData(unit, status);
340 if (status & ATAF_ERROR)
341 {
342 ata_IRQNoData(unit, status);
343 return;
344 }
345
346 /* anything for us please? */
347 if (ATAPIF_WRITE != (reason & ATAPIF_MASK))
348 return;
349
350 size = PIO_In(bus, atapi_ByteCntH) << 8 | PIO_In(bus, atapi_ByteCntL);
351 DIRQ(bug("[ATAPI] IRQ: data requested for write (%ld bytes, max: %ld bytes)\n", size, unit->au_cmd_total));
352
353 if (size > unit->au_cmd_total)
354 {
355 DERROR(bug("[ATAPI] IRQ: CRITICAL! MORE DATA REQUESTED THAN STORAGE CAN GIVE: %ld bytes vs %ld bytes left!\n", size, unit->au_cmd_total));
356 size = unit->au_cmd_total;
357 }
358
359 Unit_OutS(unit, unit->au_cmd_data, size);
360 unit->au_cmd_data = &((UBYTE*)unit->au_cmd_data)[size];
361 unit->au_cmd_total -= size;
362
363 DIRQ(bug("[ATAPI] IRQ: %lu bytes written.\n", size));
364
365 if (unit->au_cmd_total == 0)
366 ata_IRQSetHandler(unit, &ata_IRQNoData, NULL, 0, 0);
367 }
368
369 /*
370 * wait for timeout or drive ready
371 */
372 static BOOL ata_WaitBusyTO(struct ata_Unit *unit, UWORD tout, BOOL irq,
373 BOOL fake_irq, UBYTE *stout)
374 {
375 struct ata_Bus *bus = unit->au_Bus;
376 UBYTE status = 0xff;
377 ULONG step = 0;
378 BOOL res = TRUE;
379
380 if (bus->ab_Base->ata_Poll)
381 irq = FALSE;
382
383 if (irq)
384 {
385 /* Do not read ata_Status in irq mode. It can cause random lost interrupts. */
386 if (bus->haveAltIO)
387 status = PIO_InAlt(bus, ata_AltStatus);
388 /*
389 * wait for either IRQ or timeout
390 */
391 DIRQ(bug("[ATA%02ld] Waiting (Current status: %02lx)...\n",
392 unit->au_UnitNum, status));
393 step = ata_WaitTO(unit->au_Bus->ab_Timer, tout, 0,
394 1 << bus->ab_SleepySignal);
395
396 if (step == 0)
397 {
398 DERROR(bug("[ATA%02ld] Timeout while waiting for device to complete"
399 " operation\n", unit->au_UnitNum));
400
401 Disable();
402 if (fake_irq)
403 {
404 /* fake the interrupt we expected */
405 status = PIO_In(bus, ata_Status);
406 while (unit->au_Bus->ab_HandleIRQ != NULL)
407 unit->au_Bus->ab_HandleIRQ(unit, status);
408 }
409 else
410 {
411 /* do nothing if the interrupt eventually arrives */
412 ata_IRQSetHandler(unit, NULL, NULL, 0, 0);
413 res = FALSE;
414 }
415 Enable();
416 }
417 }
418 else
419 {
420 status = PIO_InAlt(bus, ata_AltStatus);
421 while (status & ATAF_BUSY)
422 {
423 ++step;
424
425 /*
426 * every 16n rounds do some extra stuff
427 */
428 if ((step & 15) == 0)
429 {
430 /*
431 * huhm. so it's been 16n rounds already. any timeout yet?
432 */
433 if (step >> 4 > tout * 1000)
434 {
435 DERROR(bug("[ATA%02ld] Device still busy after timeout."
436 " Aborting\n", unit->au_UnitNum));
437 res = FALSE;
438 break;
439 }
440
441 /*
442 * no timeout just yet, but it's not a good idea to keep
443 * spinning like that. let's give the system some time.
444 */
445 ata_WaitTO(unit->au_Bus->ab_Timer, 0, 1000, 0);
446 }
447
448 status = PIO_InAlt(bus, ata_AltStatus);
449 }
450 }
451
452 /*
453 * get final status and clear any interrupt (may be neccessary if we
454 * were polling, for example)
455 */
456 status = PIO_In(bus, ata_Status);
457
458 /*
459 * be nice to frustrated developer
460 */
461 DIRQ(bug("[ATA%02ld] WaitBusy status: %lx / %ld\n", unit->au_UnitNum,
462 status, res));
463
464 /*
465 * release old junk
466 */
467 SetSignal(0, 1 << bus->ab_SleepySignal);
468
469 /*
470 * and say it went fine (i mean it)
471 */
472 if (stout)
473 *stout = status;
474 return res;
475 }
476
477 /*
478 * Procedure for sending ATA command blocks
479 * it appears LARGE but there's a lot of COMMENTS here :)
480 * handles *all* ata commands (no data, pio and dma)
481 * naturally could be split at some point in the future
482 * depends if anyone believes that the change for 50 lines
483 * would make slow ATA transfers any faster
484 */
485 static BYTE ata_exec_cmd(struct ata_Unit* unit, ata_CommandBlock *block)
486 {
487 struct ata_Bus *bus = unit->au_Bus;
488 BYTE err = 0;
489 APTR mem = block->buffer;
490 UBYTE status;
491
492 /*
493 * Use a short timeout for Identify commands. This is because some bad
494 * drives make us think that there are two devices on the bus when there
495 * is really only one, so when we send an Identify command to the phantom
496 * drive, we can't rely on getting an IRQ. Additionally, some real drives
497 * don't produce an IRQ when the Identify command is complete, so we call
498 * the interrupt handler "manually" if we time out while waiting for it.
499 */
500 BOOL fake_irq = block->command == ATA_IDENTIFY_DEVICE
501 || block->command == ATA_IDENTIFY_ATAPI;
502 UWORD timeout = fake_irq? 1 : TIMEOUT;
503
504 if (FALSE == ata_SelectUnit(unit))
505 return IOERR_UNITBUSY;
506
507 switch (block->type)
508 {
509 case CT_CHS:
510 case CT_LBA28:
511 if (block->sectors > 256)
512 {
513 DERROR(bug("[ATA%02ld] ata_exec_cmd: ERROR: Transfer length (%ld) exceeds 256 sectors. Aborting.\n", unit->au_UnitNum, block->sectors));
514 return IOERR_BADLENGTH;
515 }
516
517 /* note:
518 * we want the above to fall in here!
519 * we really do (checking for secmul)
520 */
521
522 case CT_LBA48:
523 if (block->sectors > 65536)
524 {
525 DERROR(bug("[ATA%02ld] ata_exec_cmd: ERROR: Transfer length (%ld) exceeds 65536 sectors. Aborting.\n", unit->au_UnitNum, block->sectors));
526 return IOERR_BADLENGTH;
527 }
528 if (block->secmul == 0)
529 {
530 DERROR(bug("[ATA%02ld] ata_exec_cmd: ERROR: Invalid transfer multiplier. Should be at least set to 1 (correcting)\n", unit->au_UnitNum));
531 block->secmul = 1;
532 }
533 break;
534
535 case CT_NoBlock:
536 break;
537
538 default:
539 DERROR(bug("[ATA%02ld] ata_exec_cmd: ERROR: Invalid command type %lx. Aborting.\n", unit->au_UnitNum, block->type));
540 return IOERR_NOCMD;
541 }
542
543 block->actual = 0;
544 D(bug("[ATA%02ld] ata_exec_cmd: Executing command %02lx\n", unit->au_UnitNum, block->command));
545
546 if (block->feature != 0)
547 PIO_Out(bus, block->feature, ata_Feature);
548
549 /*
550 * - set LBA and sector count
551 */
552 switch (block->type)
553 {
554 case CT_CHS:
555 DATA(bug("[ATA%02ld] ata_exec_cmd: Command uses CHS addressing (OLD)\n", unit->au_UnitNum));
556 {
557 ULONG cyl, head, sector;
558 ULONG tmp = unit->au_Heads * unit->au_Sectors;
559 cyl = block->blk / tmp;
560 head = (block->blk % tmp) / unit->au_Sectors;
561 sector = (block->blk % unit->au_Sectors) + 1;
562
563 PIO_Out(bus, ((head) & 0x0f) | unit->au_DevMask, ata_DevHead);
564 PIO_Out(bus, sector, ata_Sector);
565 PIO_Out(bus, cyl & 0xff, ata_CylinderLow);
566 PIO_Out(bus, (cyl >> 8) & 0xff, ata_CylinderHigh);
567 PIO_Out(bus, block->sectors, ata_Count);
568 }
569 break;
570 case CT_LBA28:
571 DATA(bug("[ATA%02ld] ata_exec_cmd: Command uses 28bit LBA addressing (OLD)\n", unit->au_UnitNum));
572
573 PIO_Out(bus, ((block->blk >> 24) & 0x0f) | DEVHEAD_VAL | unit->au_DevMask, ata_DevHead);
574 PIO_Out(bus, block->blk >> 16, ata_LBAHigh);
575 PIO_Out(bus, block->blk >> 8, ata_LBAMid);
576 PIO_Out(bus, block->blk, ata_LBALow);
577 PIO_Out(bus, block->sectors, ata_Count);
578 break;
579
580 case CT_LBA48:
581 DATA(bug("[ATA%02ld] ata_exec_cmd: Command uses 48bit LBA addressing (NEW)\n", unit->au_UnitNum));
582
583 PIO_Out(bus, DEVHEAD_VAL | unit->au_DevMask, ata_DevHead);
584 PIO_Out(bus, block->blk >> 40, ata_LBAHigh);
585 PIO_Out(bus, block->blk >> 32, ata_LBAMid);
586 PIO_Out(bus, block->blk >> 24, ata_LBALow);
587
588 PIO_Out(bus, block->blk >> 16, ata_LBAHigh);
589 PIO_Out(bus, block->blk >> 8, ata_LBAMid);
590 PIO_Out(bus, block->blk, ata_LBALow);
591
592 PIO_Out(bus, block->sectors >> 8, ata_Count);
593 PIO_Out(bus, block->sectors, ata_Count);
594 break;
595
596 case CT_NoBlock:
597 DATA(bug("[ATA%02ld] ata_exec_cmd: Command does not address any block\n", unit->au_UnitNum));
598 break;
599 }
600
601 switch (block->method)
602 {
603 case CM_PIOWrite:
604 ata_IRQSetHandler(unit, &ata_IRQPIOWrite, mem, block->secmul << unit->au_SectorShift, block->length);
605 break;
606
607 case CM_PIORead:
608 ata_IRQSetHandler(unit, &ata_IRQPIORead, mem, block->secmul << unit->au_SectorShift, block->length);
609 break;
610
611 case CM_DMARead:
612 if (FALSE == DMA_Setup(bus, mem, block->length, TRUE))
613 return IOERR_ABORTED;
614
615 ata_IRQSetHandler(unit, &ata_IRQDMAReadWrite, NULL, 0, 0);
616 DMA_Start(bus);
617 break;
618
619 case CM_DMAWrite:
620 if (FALSE == DMA_Setup(bus, mem, block->length, FALSE))
621 return IOERR_ABORTED;
622
623 ata_IRQSetHandler(unit, &ata_IRQDMAReadWrite, NULL, 0, 0);
624 DMA_Start(bus);
625 break;
626
627 case CM_NoData:
628 ata_IRQSetHandler(unit, &ata_IRQNoData, NULL, 0, 0);
629 break;
630
631 default:
632 return IOERR_NOCMD;
633 break;
634 };
635
636 /*
637 * send command now
638 * let drive propagate its signals
639 */
640 DATA(bug("[ATA%02ld] ata_exec_cmd: Sending command\n", unit->au_UnitNum));
641
642 PIO_Out(bus, block->command, ata_Command);
643 ata_WaitNano(400, bus->ab_Base);
644 //ata_WaitTO(unit->au_Bus->ab_Timer, 0, 1, 0);
645
646 /*
647 * In case of PIO write the drive won't issue an IRQ before first
648 * data transfer, so we should poll the status and send the first
649 * block upon request.
650 */
651 if (block->method == CM_PIOWrite)
652 {
653 if (FALSE == ata_WaitBusyTO(unit, TIMEOUT, FALSE, FALSE, &status)) {
654 DERROR(bug("[ATA%02ld] ata_exec_cmd: PIOWrite - no response from device. Status %02X\n", unit->au_UnitNum, status));
655 return IOERR_UNITBUSY;
656 }
657 if (status & ATAF_DATAREQ) {
658 DATA(bug("[ATA%02ld] ata_exec_cmd: PIOWrite - DRQ.\n", unit->au_UnitNum));
659 ata_PIOWriteBlk(unit);
660 }
661 else
662 {
663 DERROR(bug("[ATA%02ld] ata_exec_cmd: PIOWrite - bad status: %02X\n", status));
664 return HFERR_BadStatus;
665 }
666 }
667
668 /*
669 * wait for drive to complete what it has to do
670 */
671 if (FALSE == ata_WaitBusyTO(unit, timeout, TRUE, fake_irq, &status))
672 {
673 DERROR(bug("[ATA%02ld] ata_exec_cmd: Device is late - no response\n", unit->au_UnitNum));
674 err = IOERR_UNITBUSY;
675 }
676 else
677 err = unit->au_cmd_error;
678
679 DATA(bug("[ATA%02ld] ata_exec_cmd: Command done\n", unit->au_UnitNum));
680
681 /*
682 * clean up DMA
683 * don't use 'mem' pointer here as it's already invalid.
684 */
685 switch (block->method)
686 {
687 case CM_DMARead:
688 DMA_End(bus, block->buffer, block->length, TRUE);
689 break;
690
691 case CM_DMAWrite:
692 DMA_End(bus, block->buffer, block->length, FALSE);
693 break;
694
695 default:
696 break; /* Shut up the compiler */
697 }
698
699 D(bug("[ATA%02ld] ata_exec_cmd: return code %ld\n", unit->au_UnitNum, err));
700 return err;
701 }
702
703 /*
704 * atapi packet iface
705 */
706 static BYTE atapi_SendPacket(struct ata_Unit *unit, APTR packet, APTR data,
707 LONG datalen, BOOL *dma, BOOL write)
708 {
709 struct ata_Bus *bus = unit->au_Bus;
710 *dma = *dma && (unit->au_Flags & AF_DMA) ? TRUE : FALSE;
711 LONG err = 0;
712
713 UBYTE cmd[12] = {
714 0
715 };
716 register int t=5,l=0;
717
718 if (((UBYTE*)packet)[0] > 0x1f)
719 t+= 4;
720 if (((UBYTE*)packet)[0] > 0x5f)
721 t+= 2;
722
723 switch (((UBYTE*)packet)[0])
724 {
725 case 0x28: // read10
726 case 0xa8: // read12
727 case 0xbe: // readcd
728 case 0xb9: // readcdmsf
729 case 0x2f: // verify
730 case 0x2a: // write
731 case 0xaa: // write12
732 case 0x2e: // writeverify
733 case 0xad: // readdvdstructure
734 case 0xa4: // reportkey
735 case 0xa3: // sendkey
736 break;
737 default:
738 *dma = FALSE;
739 }
740
741 while (l<=t)
742 {
743 cmd[l] = ((UBYTE*)packet)[l];
744 ++l;
745 }
746
747 DATAPI({
748 bug("[ATA%02lx] Sending %s ATA packet: ", unit->au_UnitNum, (*dma) ? "DMA" : "PIO");
749 l=0;
750 while (l<=t)
751 {
752 bug("%02lx ", ((UBYTE*)cmd)[l]);
753 ++l;
754 }
755 bug("\n");
756
757 if (datalen & 1)
758 bug("[ATAPI] ERROR: DATA LENGTH NOT EVEN! Rounding Up! (%ld bytes requested)\n", datalen);
759 });
760
761 datalen = (datalen+1)&~1;
762
763 if (FALSE == ata_SelectUnit(unit))
764 {
765 DATAPI(bug("[ATAPI] WaitBusy failed at first check\n"));
766 return IOERR_UNITBUSY;
767 }
768
769 /*
770 * tell device whether we want to read or write and if we want a dma transfer
771 */
772 PIO_Out(bus,
773 ((*dma) ? 1 : 0) | (((unit->au_Drive->id_DMADir & 0x8000) && !write) ? 4 : 0),
774 atapi_Features);
775 PIO_Out(bus, (datalen & 0xff), atapi_ByteCntL);
776 PIO_Out(bus, (datalen >> 8) & 0xff, atapi_ByteCntH);
777
778 /*
779 * once we're done with that, we can go ahead and inform device that we're about to send atapi packet
780 * after command is dispatched, we are obliged to give 400ns for the unit to parse command and set status
781 */
782 DATAPI(bug("[ATAPI] Issuing ATA_PACKET command.\n"));
783 ata_IRQSetHandler(unit, &ata_IRQNoData, 0, 0, 0);
784 PIO_Out(bus, ATA_PACKET, atapi_Command);
785 ata_WaitNano(400, bus->ab_Base);
786 //ata_WaitTO(unit->au_Bus->ab_Timer, 0, 1, 0);
787
788 ata_WaitBusyTO(unit, TIMEOUT, (unit->au_Drive->id_General & 0x60) == 0x20,
789 FALSE, NULL);
790 if (0 == (ata_ReadStatus(bus) & ATAF_DATAREQ))
791 return HFERR_BadStatus;
792
793 /*
794 * setup appropriate hooks
795 */
796 if (datalen == 0)
797 ata_IRQSetHandler(unit, &ata_IRQNoData, 0, 0, 0);
798 else if (*dma)
799 ata_IRQSetHandler(unit, &ata_IRQDMAReadWrite, NULL, 0, 0);
800 else if (write)
801 ata_IRQSetHandler(unit, &ata_IRQPIOWriteAtapi, data, 0, datalen);
802 else
803 ata_IRQSetHandler(unit, &ata_IRQPIOReadAtapi, data, 0, datalen);
804
805 if (*dma)
806 {
807 DATAPI(bug("[ATAPI] Starting DMA\n"));
808 DMA_Start(bus);
809 }
810
811 DATAPI(bug("[ATAPI] Sending packet\n"));
812 Unit_OutS(unit, cmd, 12);
813 ata_WaitNano(400, bus->ab_Base);
814
815 DATAPI(bug("[ATAPI] Status after packet: %lx\n", ata_ReadAltStatus(bus)));
816
817 /*
818 * Wait for command to complete. Note that two interrupts will occur
819 * before we wake up if this is a PIO data transfer
820 */
821 if (ata_WaitTO(unit->au_Bus->ab_Timer, TIMEOUT, 0,
822 1 << unit->au_Bus->ab_SleepySignal) == 0)
823 {
824 DATAPI(bug("[DSCSI] Command timed out.\n"));
825 err = IOERR_UNITBUSY;
826 }
827 else
828 err = atapi_EndCmd(unit);
829
830 if (*dma)
831 {
832 DMA_End(bus, data, datalen, !write);
833 }
834
835 DATAPI(bug("[ATAPI] IO error code %ld\n", err));
836 return err;
837 }
838
839 static BYTE atapi_DirectSCSI(struct ata_Unit *unit, struct SCSICmd *cmd)
840 {
841 APTR buffer = cmd->scsi_Data;
842 ULONG length = cmd->scsi_Length;
843 BYTE err = 0;
844 BOOL dma = FALSE;
845
846 cmd->scsi_Actual = 0;
847
848 DATAPI(bug("[DSCSI] Sending packet!\n"));
849
850 /*
851 * setup DMA & push command
852 * it does not really mean we will use dma here btw
853 */
854 if ((unit->au_Flags & AF_DMA) && (length !=0) && (buffer != 0))
855 {
856 dma = DMA_Setup(unit->au_Bus, buffer, length,
857 cmd->scsi_Flags & SCSIF_READ);
858 }
859
860 err = atapi_SendPacket(unit, cmd->scsi_Command, cmd->scsi_Data, cmd->scsi_Length, &dma, (cmd->scsi_Flags & SCSIF_READ) == 0);
861
862 DUMP({ if (cmd->scsi_Data != 0) dump(cmd->scsi_Data, cmd->scsi_Length); });
863
864 /*
865 * on check condition - grab sense data
866 */
867 DATAPI(bug("[ATA%02lx] atapi_DirectSCSI: SCSI Flags: %02lx / Error: %ld\n", unit->au_UnitNum, cmd->scsi_Flags, err));
868 if ((err != 0) && (cmd->scsi_Flags & SCSIF_AUTOSENSE))
869 {
870 DATAPI(bug("[DSCSI] atapi_DirectSCSI: Packet Failed. Calling atapi_RequestSense\n"));
871 atapi_RequestSense(unit, cmd->scsi_SenseData, cmd->scsi_SenseLength);
872 DUMP(dump(cmd->scsi_SenseData, cmd->scsi_SenseLength));
873 }
874
875 return err;
876 }
877
878 /*
879 * chops the large transfers into set of smaller transfers
880 * specifically useful when requested transfer size is >256 sectors for 28bit commands
881 */
882 static BYTE ata_exec_blk(struct ata_Unit *unit, ata_CommandBlock *blk)
883 {
884 BYTE err = 0;
885 ULONG part;
886 ULONG max=256;
887 ULONG count=blk->sectors;
888 APTR buffer = blk->buffer;
889 APTR bounce_buffer = NULL;
890 IPTR bounce_buffer_length = 0;
891
892 if (blk->type == CT_LBA48)
893 max <<= 8;
894
895 if (((IPTR)blk->buffer > 0xffffffffULL || ((IPTR)blk->buffer + (count << unit->au_SectorShift)) > 0xffffffffULL) &&
896 (blk->method == CM_DMARead || blk->method == CM_DMAWrite))
897 {
898 DATA(bug("[ATA%02ld] ata_exec_blk: attempt to do DMA transfer outside 32bit address space\n", unit->au_UnitNum));
899 DATA(bug("[ATA%02ld] ata_exec_blk: ptr %p, length %d, %s\n", unit->au_UnitNum, blk->buffer, count << unit->au_SectorShift, blk->method == CM_DMARead ? "DMARead" : "DMAWrite"));
900
901 bounce_buffer_length = count << unit->au_SectorShift;
902 bounce_buffer = AllocPooled(unit->au_Bus->ab_BounceBufferPool, bounce_buffer_length);
903 blk->buffer = bounce_buffer;
904 }
905
906 DATA(bug("[ATA%02ld] ata_exec_blk: Accessing %ld sectors starting from %x%08x\n", unit->au_UnitNum, count, (ULONG)(blk->blk >> 32), (ULONG)blk->blk));
907 while ((count > 0) && (err == 0))
908 {
909 part = (count > max) ? max : count;
910 blk->sectors = part;
911 blk->length = part << unit->au_SectorShift;
912
913 DATA(bug("[ATA%02ld] Transfer of %ld sectors from %x%08x\n", unit->au_UnitNum, part, (ULONG)(blk->blk >> 32), (ULONG)blk->blk));
914 // If bounce buffer is active,
915 if (bounce_buffer && blk->method == CM_DMAWrite)
916 {
917 DATA(bug("[ATA%02ld] Copy %d bytes from source %p to bounce buffer %p\n", unit->au_UnitNum, blk->length, buffer, bounce_buffer));
918 CopyMemQuick(buffer, bounce_buffer, blk->length);
919 buffer = (APTR)((IPTR)buffer + blk->length);
920 }
921 err = ata_exec_cmd(unit, blk);
922 DATA(bug("[ATA%02ld] ata_exec_blk: ata_exec_cmd returned %lx\n", unit->au_UnitNum, err));
923 if (bounce_buffer)
924 {
925 if (blk->method == CM_DMARead)
926 {
927 DATA(bug("[ATA%02ld] Copy %d bytes from bounce buffer %p to destination %p\n", unit->au_UnitNum, blk->length, bounce_buffer, buffer));
928 CopyMemQuick(bounce_buffer, buffer, part << unit->au_SectorShift);
929 buffer = (APTR)((IPTR)buffer + (part << unit->au_SectorShift));
930 }
931 }
932 else
933 {
934 blk->buffer = (APTR)((IPTR)blk->buffer + (part << unit->au_SectorShift));
935 }
936 blk->blk += part;
937 count -= part;
938 }
939
940 if (bounce_buffer)
941 FreePooled(unit->au_Bus->ab_BounceBufferPool, bounce_buffer, bounce_buffer_length);
942
943 return err;
944 }
945
946 /*
947 * Initial device configuration that suits *all* cases
948 */
949 void ata_init_unit(struct ata_Bus *bus, struct ata_Unit *unit, UBYTE u)
950 {
951 struct ataBase *ATABase = bus->ab_Base;
952 OOP_Object *obj = OOP_OBJECT(ATABase->busClass, bus);
953
954 unit->au_Bus = bus;
955 unit->pioInterface = bus->pioInterface;
956 unit->au_UnitNum = bus->ab_BusNum << 1 | u; // b << 8 | u
957 unit->au_DevMask = 0xa0 | (u << 4);
958
959 DINIT(bug("[ATA%02u] ata_init_unit: bus %u unit %d\n", unit->au_UnitNum, bus->ab_BusNum, u));
960
961 /* Set PIO transfer functions, either 16 or 32 bits */
962 if (ATABase->ata_32bit && OOP_GET(obj, aHidd_ATABus_Use32Bit))
963 Unit_Enable32Bit(unit);
964 else
965 Unit_Disable32Bit(unit);
966 }
967
968 BOOL ata_setup_unit(struct ata_Bus *bus, struct ata_Unit *unit)
969 {
970 /*
971 * this stuff always goes along the same way
972 * WARNING: NO INTERRUPTS AT THIS POINT!
973 */
974 UBYTE u;
975
976 DINIT(bug("[ATA ] ata_setup_unit(%d)\n", unit->au_UnitNum));
977 ata_SelectUnit(unit);
978
979 if (FALSE == ata_WaitBusyTO(unit, 1, FALSE, FALSE, NULL))
980 {
981 DINIT(bug("[ATA%02ld] ata_setup_unit: ERROR: Drive not ready for use. Keeping functions stubbed\n", unit->au_UnitNum));
982 return FALSE;
983 }
984
985 u = unit->au_UnitNum & 1;
986 switch (bus->ab_Dev[u])
987 {
988 /*
989 * safe fallback settings
990 */
991 case DEV_SATAPI:
992 case DEV_ATAPI:
993 case DEV_SATA:
994 case DEV_ATA:
995 unit->au_Identify = ata_Identify;
996 break;
997
998 default:
999 DINIT(bug("[ATA%02ld] ata_setup_unit: Unsupported device %lx. All functions will remain stubbed.\n", unit->au_UnitNum, bus->ab_Dev[u]));
1000 return FALSE;
1001 }
1002
1003 DINIT(bug("[ATA ] ata_setup_unit: Enabling IRQs\n"));
1004 PIO_OutAlt(bus, 0x0, ata_AltControl);
1005
1006 /*
1007 * now make unit self diagnose
1008 */
1009 if (unit->au_Identify(unit) != 0)
1010 {
1011 return FALSE;
1012 }
1013
1014 return TRUE;
1015 }
1016
1017 /*
1018 * ata[pi] identify
1019 */
1020 static void common_SetXferMode(struct ata_Unit* unit, ata_XferMode mode)
1021 {
1022 struct ata_Bus *bus = unit->au_Bus;
1023 BOOL dma = FALSE;
1024 /*
1025 * We can't set drive modes unless we also set the controller's timing registers
1026 * FIXME: Implement aoHodd_ATABus_CanSetXferMode and moHidd_ATABus_SetXferMode
1027 support.
1028 * CHECKME: Current code lives with what machine's firmware has set for us. Looks
1029 * like all firmwares set up the best DMA mode. But what if the firmware
1030 * didn't set it up for some reason (the add-on controller which has been
1031 * ignored by it
1032 * for example) ? Shouldn't we check unit->au_UseModes here ?
1033 */
1034 #if 0
1035 struct ataBase *ATABase = bus->ab_Base;
1036 OOP_Object *obj = OOP_OBJECT(ATABase->busClass, bus);
1037 UBYTE type=0;
1038 ata_CommandBlock acb =
1039 {
1040 ATA_SET_FEATURES,
1041 0x03,
1042 0x01,
1043 0x00,
1044 0x00,
1045 0x00,
1046 0x00,
1047 0x00,
1048 0x00,
1049 CM_NoData,
1050 CT_LBA28
1051 };
1052 #endif
1053 DINIT(bug("[ATA%02ld] common_SetXferMode: Trying to set mode %d\n", unit->au_UnitNum, mode));
1054
1055 /* CHECKME: This condition should be not needed. */
1056 if ((!bus->dmaVectors) && (mode >= AB_XFER_MDMA0))
1057 {
1058 DINIT(bug("[ATA%02ld] common_SetXferMode: This controller does not own DMA port! Will set best PIO\n", unit->au_UnitNum));
1059 common_SetBestXferMode(unit);
1060 return;
1061 }
1062
1063 /*
1064 * first, ONLY for ATA devices, set new commands
1065 */
1066 if (0 == (unit->au_XferModes & AF_XFER_PACKET))
1067 {
1068 if ((mode >= AB_XFER_MDMA0) && (mode <= AB_XFER_UDMA6))
1069 {
1070 /* DMA, both multiword and Ultra */
1071 unit->au_Read32 = ata_ReadDMA32;
1072 unit->au_Write32 = ata_WriteDMA32;
1073 if (unit->au_XferModes & AF_XFER_48BIT)
1074 {
1075 unit->au_UseModes |= AF_XFER_48BIT;
1076 unit->au_Read64 = ata_ReadDMA64;
1077 unit->au_Write64 = ata_WriteDMA64;
1078 }
1079 }
1080 else if ((!unit->au_Bus->ab_Base->ata_NoMulti) && (unit->au_XferModes & AF_XFER_RWMULTI))
1081 {
1082 /* Multisector PIO */
1083 ata_IRQSetHandler(unit, ata_IRQNoData, NULL, 0, 0);
1084 PIO_Out(bus, unit->au_Drive->id_RWMultipleSize & 0xFF, ata_Count);
1085 PIO_Out(bus, ATA_SET_MULTIPLE, ata_Command);
1086 ata_WaitBusyTO(unit, -1, TRUE, FALSE, NULL);
1087
1088 unit->au_UseModes |= AF_XFER_RWMULTI;
1089 unit->au_Read32 = ata_ReadMultiple32;
1090 unit->au_Write32 = ata_WriteMultiple32;
1091 if (unit->au_XferModes & AF_XFER_48BIT)
1092 {
1093 unit->au_UseModes |= AF_XFER_48BIT;
1094 unit->au_Read64 = ata_ReadMultiple64;
1095 unit->au_Write64 = ata_WriteMultiple64;
1096 }
1097 }
1098 else
1099 {
1100 /* 1-sector PIO */
1101 unit->au_Read32 = ata_ReadSector32;
1102 unit->au_Write32 = ata_WriteSector32;
1103 if (unit->au_XferModes & AF_XFER_48BIT)
1104 {
1105 unit->au_UseModes |= AF_XFER_48BIT;
1106 unit->au_Read64 = ata_ReadSector64;
1107 unit->au_Write64 = ata_WriteSector64;
1108 }
1109 }
1110 }
1111
1112 #if 0 // We can't set drive modes unless we also set the controller's timing registers
1113 if ((mode >= AB_XFER_PIO0) && (mode <= AB_XFER_PIO4))
1114 {
1115 type = 8 + (mode - AB_XFER_PIO0);
1116 }
1117 else if ((mode >= AB_XFER_MDMA0) && (mode <= AB_XFER_MDMA2))
1118 {
1119 type = 32 + (mode - AB_XFER_MDMA0);
1120 dma=TRUE;
1121 }
1122 else if ((mode >= AB_XFER_UDMA0) && (mode <= AB_XFER_UDMA6))
1123 {
1124 type = 64 + (mode - AB_XFER_UDMA0);
1125 dma=TRUE;
1126 }
1127 else
1128 {
1129 type = 0;
1130 }
1131
1132 acb.sectors = type;
1133 if (0 != ata_exec_cmd(unit, &acb))
1134 {
1135 DINIT(bug("[ATA%02ld] common_SetXferMode: ERROR: Failed to apply new xfer mode.\n", unit->au_UnitNum));
1136 }
1137
1138 if (!HIDD_ATABus_SetXferMode(obj, mode))
1139 {
1140 /*
1141 * DMA mode setup failed.
1142 * FIXME: Should completely revert back to PIO protocol, or try lower mode.
1143 */
1144 dma = FALSE;
1145 }
1146 #else
1147 if (mode >= AB_XFER_MDMA0)
1148 dma = TRUE;
1149 #endif
1150
1151 if (dma)
1152 {
1153 unit->au_Flags |= AF_DMA; /* This flag is used by ATAPI protocol */
1154 }
1155 else
1156 {
1157 unit->au_UseModes &= ~AF_XFER_DMA_MASK;
1158 unit->au_Flags &= ~AF_DMA;
1159 }
1160 }
1161
1162 static void common_SetBestXferMode(struct ata_Unit* unit)
1163 {
1164 struct ata_Bus *bus = unit->au_Bus;
1165 struct ataBase *ATABase = bus->ab_Base;
1166 OOP_Object *obj = OOP_OBJECT(ATABase->busClass, bus);
1167 int iter;
1168 int max = AB_XFER_UDMA6;
1169
1170 if ((!bus->dmaInterface)
1171 || ( !(unit->au_Drive->id_MWDMASupport & 0x0700)
1172 && !(unit->au_Drive->id_UDMASupport & 0x7f00)))
1173 {
1174 /*
1175 * make sure you reduce scan search to pio here!
1176 * otherwise this and above function will fall into infinite loop
1177 */
1178 DINIT(bug("[ATA%02ld] common_SetBestXferMode: DMA is disabled for"
1179 " this drive.\n", unit->au_UnitNum));
1180 max = AB_XFER_PIO4;
1181 }
1182 else if (!OOP_GET(obj, aHidd_ATABus_Use80Wire))
1183 {
1184 DINIT(bug("[ATA%02ld] common_SetBestXferMode: "
1185 "An 80-wire cable has not been detected for this drive. "
1186 "Disabling modes above UDMA2.\n", unit->au_UnitNum));
1187 max = AB_XFER_UDMA2;
1188 }
1189
1190 for (iter=max; iter>=AB_XFER_PIO0; --iter)
1191 {
1192 if (unit->au_XferModes & (1<<iter))
1193 {
1194 common_SetXferMode(unit, iter);
1195 return;
1196 }
1197 }
1198 bug("[ATA%02ld] common_SetBestXferMode: ERROR: device never reported any valid xfer modes. will continue at default\n", unit->au_UnitNum);
1199 common_SetXferMode(unit, AB_XFER_PIO0);
1200 }
1201
1202 static void common_DetectXferModes(struct ata_Unit* unit)
1203 {
1204 int iter;
1205
1206 DINIT(bug("[ATA%02ld] common_DetectXferModes: Supports\n", unit->au_UnitNum));
1207
1208 if (unit->au_Drive->id_Commands4 & (1 << 4))
1209 {
1210 DINIT(bug("[ATA%02ld] common_DetectXferModes: - Packet interface\n", unit->au_UnitNum));
1211 unit->au_XferModes |= AF_XFER_PACKET;
1212 unit->au_DirectSCSI = atapi_DirectSCSI;
1213 }
1214 else if (unit->au_Drive->id_Commands5 & (1 << 10))
1215 {
1216 /* ATAPI devices do not use this bit. */
1217 DINIT(bug("[ATA%02ld] common_DetectXferModes: - 48bit I/O\n", unit->au_UnitNum));
1218 unit->au_XferModes |= AF_XFER_48BIT;
1219 }
1220
1221 if ((unit->au_XferModes & AF_XFER_PACKET) || (unit->au_Drive->id_Capabilities & (1<< 9)))
1222 {
1223 DINIT(bug("[ATA%02ld] common_DetectXferModes: - LBA Addressing\n", unit->au_UnitNum));
1224 unit->au_XferModes |= AF_XFER_LBA;
1225 unit->au_UseModes |= AF_XFER_LBA;
1226 }
1227 else
1228 {
1229 DINIT(bug("[ATA%02ld] common_DetectXferModes: - DEVICE DOES NOT SUPPORT LBA ADDRESSING >> THIS IS A POTENTIAL PROBLEM <<\n", unit->au_UnitNum));
1230 unit->au_Flags |= AF_CHSOnly;
1231 }
1232
1233 if (unit->au_Drive->id_RWMultipleSize & 0xff)
1234 {
1235 DINIT(bug("[ATA%02ld] common_DetectXferModes: - R/W Multiple (%ld sectors per xfer)\n", unit->au_UnitNum, unit->au_Drive->id_RWMultipleSize & 0xff));
1236 unit->au_XferModes |= AF_XFER_RWMULTI;
1237 }
1238
1239 DINIT(bug("[ATA%02ld] common_DetectXferModes: - PIO0 PIO1 PIO2 ",
1240 unit->au_UnitNum));
1241 unit->au_XferModes |= AF_XFER_PIO(0) | AF_XFER_PIO(1) | AF_XFER_PIO(2);
1242 if (unit->au_Drive->id_ConfigAvailable & (1 << 1))
1243 {
1244 for (iter = 0; iter < 2; iter++)
1245 {
1246 if (unit->au_Drive->id_PIOSupport & (1 << iter))
1247 {
1248 DINIT(bug("PIO%ld ", 3 + iter));
1249 unit->au_XferModes |= AF_XFER_PIO(3 + iter);
1250 }
1251 }
1252 DINIT(bug("\n"));
1253 }
1254
1255 if ((unit->au_Drive->id_ConfigAvailable & (1 << 1)) &&
1256 (unit->au_Drive->id_Capabilities & (1<<8)))
1257 {
1258 DINIT(bug("[ATA%02ld] common_DetectXferModes: DMA:\n", unit->au_UnitNum));
1259 if (unit->au_Drive->id_MWDMASupport & 0xff)
1260 {
1261 DINIT(bug("[ATA%02ld] common_DetectXferModes: - ", unit->au_UnitNum));
1262 for (iter = 0; iter < 3; iter++)
1263 {
1264 if (unit->au_Drive->id_MWDMASupport & (1 << iter))
1265 {
1266 unit->au_XferModes |= AF_XFER_MDMA(iter);
1267 if (unit->au_Drive->id_MWDMASupport & (256 << iter))
1268 {
1269 unit->au_UseModes |= AF_XFER_MDMA(iter);
1270 DINIT(bug("[MDMA%ld] ", iter));
1271 }
1272 DINIT(else bug("MDMA%ld ", iter);)
1273 }
1274 }
1275 DINIT(bug("\n"));
1276 }
1277
1278 if (unit->au_Drive->id_UDMASupport & 0xff)
1279 {
1280 DINIT(bug("[ATA%02ld] common_DetectXferModes: - ", unit->au_UnitNum));
1281 for (iter = 0; iter < 7; iter++)
1282 {
1283 if (unit->au_Drive->id_UDMASupport & (1 << iter))
1284 {
1285 unit->au_XferModes |= AF_XFER_UDMA(iter);
1286 if (unit->au_Drive->id_UDMASupport & (256 << iter))
1287 {
1288 unit->au_UseModes |= AF_XFER_UDMA(iter);
1289 DINIT(bug("[UDMA%ld] ", iter));
1290 }
1291 DINIT(else bug("UDMA%ld ", iter);)
1292 }
1293 }
1294 DINIT(bug("\n"));
1295 }
1296 }
1297 }
1298
1299 #define SWAP_LE_WORD(x) (x) = AROS_LE2WORD((x))
1300 #define SWAP_LE_LONG(x) (x) = AROS_LE2LONG((x))
1301 #define SWAP_LE_QUAD(x) (x) = AROS_LE2LONG((x) >> 32) | (((QUAD)(AROS_LE2LONG((x) & 0xffffffff))) << 32)
1302
1303 static BYTE ata_Identify(struct ata_Unit *unit)
1304 {
1305 BOOL atapi = unit->au_Bus->ab_Dev[unit->au_UnitNum & 1] & 0x80;
1306 BOOL supportLBA, supportLBA48;
1307 ata_CommandBlock acb =
1308 {
1309 atapi ? ATA_IDENTIFY_ATAPI : ATA_IDENTIFY_DEVICE,
1310 0,
1311 1,
1312 0,
1313 0,
1314 0,
1315 unit->au_Drive,
1316 sizeof(struct DriveIdent),
1317 0,
1318 CM_PIORead,
1319 CT_NoBlock
1320 };
1321 UWORD n = 0, *p, *limit;
1322
1323 /* If the right command fails, try the wrong one. If both fail, abort */
1324 DINIT(bug("[ATA%02ld] ata_Identify: Executing ATA_IDENTIFY_%s command\n",
1325 unit->au_UnitNum, atapi ? "ATAPI" : "DEVICE"));
1326 if (ata_exec_cmd(unit, &acb))
1327 {
1328 acb.command = atapi ? ATA_IDENTIFY_DEVICE : ATA_IDENTIFY_ATAPI;
1329 DINIT(bug("[ATA%02ld] ata_Identify: Executing ATA_IDENTIFY_%s command"
1330 " instead\n", unit->au_UnitNum, atapi ? "DEVICE" : "ATAPI"));
1331 if (ata_exec_cmd(unit, &acb))
1332 {
1333 DINIT(bug("[ATA%02ld] ata_Identify: Both command variants failed."
1334 " Discarding drive.\n",
1335 unit->au_UnitNum));
1336 return IOERR_OPENFAIL;
1337 }
1338 unit->au_Bus->ab_Dev[unit->au_UnitNum & 1] ^= 0x82;
1339 atapi = unit->au_Bus->ab_Dev[unit->au_UnitNum & 1] & 0x80;
1340 DINIT(bug("[ATA%02ld] ata_Identify:"
1341 " Incorrect device signature detected."
1342 " Switching device type to %lx.\n", unit->au_UnitNum,
1343 unit->au_Bus->ab_Dev[unit->au_UnitNum & 1]));
1344 }
1345
1346 /*
1347 * If every second word is zero with 32-bit reads, switch to 16-bit
1348 * accesses for this drive and try again
1349 */
1350 if (unit->au_Bus->ab_Base->ata_32bit)
1351 {
1352 for (p = (UWORD *)unit->au_Drive, limit = p + 256; p < limit; p++)
1353 n |= *++p;
1354
1355 if (n == 0)
1356 {
1357 DINIT(bug("[ATA%02ld] Identify data was invalid with 32-bit reads."
1358 " Switching to 16-bit mode.\n", unit->au_UnitNum));
1359
1360 Unit_Disable32Bit(unit);
1361
1362 if (ata_exec_cmd(unit, &acb))
1363 return IOERR_OPENFAIL;
1364 }
1365 }
1366
1367 #if (AROS_BIG_ENDIAN != 0)
1368 SWAP_LE_WORD(unit->au_Drive->id_General);
1369 SWAP_LE_WORD(unit->au_Drive->id_OldCylinders);
1370 SWAP_LE_WORD(unit->au_Drive->id_SpecificConfig);
1371 SWAP_LE_WORD(unit->au_Drive->id_OldHeads);
1372 SWAP_LE_WORD(unit->au_Drive->id_OldSectors);
1373 SWAP_LE_WORD(unit->au_Drive->id_RWMultipleSize);
1374 SWAP_LE_WORD(unit->au_Drive->id_Capabilities);
1375 SWAP_LE_WORD(unit->au_Drive->id_OldCaps);
1376 SWAP_LE_WORD(unit->au_Drive->id_OldPIO);
1377 SWAP_LE_WORD(unit->au_Drive->id_ConfigAvailable);
1378 SWAP_LE_WORD(unit->au_Drive->id_OldLCylinders);
1379 SWAP_LE_WORD(unit->au_Drive->id_OldLHeads);
1380 SWAP_LE_WORD(unit->au_Drive->id_OldLSectors);
1381 SWAP_LE_WORD(unit->au_Drive->id_RWMultipleTrans);
1382 SWAP_LE_WORD(unit->au_Drive->id_DMADir);
1383 SWAP_LE_WORD(unit->au_Drive->id_MWDMASupport);
1384 SWAP_LE_WORD(unit->au_Drive->id_PIOSupport);
1385 SWAP_LE_WORD(unit->au_Drive->id_MWDMA_MinCycleTime);
1386 SWAP_LE_WORD(unit->au_Drive->id_MWDMA_DefCycleTime);
1387 SWAP_LE_WORD(unit->au_Drive->id_PIO_MinCycleTime);
1388 SWAP_LE_WORD(unit->au_Drive->id_PIO_MinCycleTimeIORDY);
1389 SWAP_LE_WORD(unit->au_Drive->id_QueueDepth);
1390 SWAP_LE_WORD(unit->au_Drive->id_ATAVersion);
1391 SWAP_LE_WORD(unit->au_Drive->id_ATARevision);
1392 SWAP_LE_WORD(unit->au_Drive->id_Commands1);
1393 SWAP_LE_WORD(unit->au_Drive->id_Commands2);
1394 SWAP_LE_WORD(unit->au_Drive->id_Commands3);
1395 SWAP_LE_WORD(unit->au_Drive->id_Commands4);
1396 SWAP_LE_WORD(unit->au_Drive->id_Commands5);
1397 SWAP_LE_WORD(unit->au_Drive->id_Commands6);
1398 SWAP_LE_WORD(unit->au_Drive->id_UDMASupport);
1399 SWAP_LE_WORD(unit->au_Drive->id_SecurityEraseTime);
1400 SWAP_LE_WORD(unit->au_Drive->id_ESecurityEraseTime);
1401 SWAP_LE_WORD(unit->au_Drive->id_CurrentAdvPowerMode);
1402 SWAP_LE_WORD(unit->au_Drive->id_MasterPwdRevision);
1403 SWAP_LE_WORD(unit->au_Drive->id_HWResetResult);
1404 SWAP_LE_WORD(unit->au_Drive->id_AcousticManagement);
1405 SWAP_LE_WORD(unit->au_Drive->id_StreamMinimunReqSize);
1406 SWAP_LE_WORD(unit->au_Drive->id_StreamingTimeDMA);
1407 SWAP_LE_WORD(unit->au_Drive->id_StreamingLatency);
1408 SWAP_LE_WORD(unit->au_Drive->id_StreamingTimePIO);
1409 SWAP_LE_WORD(unit->au_Drive->id_PhysSectorSize);
1410 SWAP_LE_WORD(unit->au_Drive->id_RemMediaStatusNotificationFeatures);
1411 SWAP_LE_WORD(unit->au_Drive->id_SecurityStatus);
1412
1413 SWAP_LE_LONG(unit->au_Drive->id_WordsPerLogicalSector);
1414 SWAP_LE_LONG(unit->au_Drive->id_LBASectors);
1415 SWAP_LE_LONG(unit->au_Drive->id_StreamingGranularity);
1416
1417 SWAP_LE_QUAD(unit->au_Drive->id_LBA48Sectors);
1418 #endif
1419
1420 DUMP(dump(unit->au_Drive, sizeof(struct DriveIdent)));
1421
1422 if (atapi)
1423 {
1424 unit->au_SectorShift = 11;
1425 unit->au_Read32 = atapi_Read;
1426 unit->au_Write32 = atapi_Write;
1427 unit->au_DirectSCSI = atapi_DirectSCSI;
1428 unit->au_Eject = atapi_Eject;
1429 unit->au_Flags |= AF_DiscChanged;
1430 unit->au_DevType = (unit->au_Drive->id_General >>8) & 0x1f;
1431 unit->au_XferModes = AF_XFER_PACKET;
1432 unit->au_UseModes |= AF_XFER_PACKET; /* OR because this field may already contain AF_XFER_PIO32 */
1433 }
1434 else
1435 {
1436 unit->au_SectorShift = 9;
1437 unit->au_DevType = DG_DIRECT_ACCESS;
1438 unit->au_Read32 = ata_ReadSector32;
1439 unit->au_Write32 = ata_WriteSector32;
1440 unit->au_Eject = ata_Eject;
1441 unit->au_XferModes = 0;
1442 unit->au_Flags |= AF_DiscPresent | AF_DiscChanged;
1443 }
1444
1445 ata_strcpy(unit->au_Drive->id_Model, unit->au_Model, 40);
1446 ata_strcpy(unit->au_Drive->id_SerialNumber, unit->au_SerialNumber, 20);
1447 ata_strcpy(unit->au_Drive->id_FirmwareRev, unit->au_FirmwareRev, 8);
1448
1449 bug("[ATA%02ld] ata_Identify: Unit info: %s / %s / %s\n", unit->au_UnitNum, unit->au_Model, unit->au_SerialNumber, unit->au_FirmwareRev);
1450 common_DetectXferModes(unit);
1451 common_SetBestXferMode(unit);
1452
1453 if (unit->au_Drive->id_General & 0x80)
1454 {
1455 DINIT(bug("[ATA%02ld] ata_Identify: Device is removable.\n", unit->au_UnitNum));
1456 unit->au_Flags |= AF_Removable;
1457 }
1458
1459 supportLBA = (unit->au_Drive->id_Capabilities & (1 << 9)) != 0;
1460 supportLBA48 = supportLBA && (unit->au_Drive->id_Commands5 & (1 << 10)) != 0;
1461
1462 unit->au_Capacity = unit->au_Drive->id_LBASectors;
1463 if (supportLBA48)
1464 unit->au_Capacity48 = unit->au_Drive->id_LBA48Sectors;
1465 else
1466 unit->au_Capacity48 = unit->au_Capacity;
1467
1468 DINIT(bug("[ATA%02ld] ata_Identify: Unit LBA%d: %07lx 28bit / %04lx:%08lx 48bit addressable blocks\n",
1469 unit->au_UnitNum, supportLBA48 ? 48 : (supportLBA ? 28 : 0),
1470 unit->au_Capacity, (ULONG)(unit->au_Capacity48 >> 32), (ULONG)(unit->au_Capacity48 & 0xfffffffful)));
1471
1472 if (atapi)
1473 {
1474 /*
1475 * ok, this is not very original, but quite compatible :P
1476 */
1477 switch (unit->au_DevType)
1478 {
1479 case DG_CDROM:
1480 case DG_WORM:
1481 case DG_OPTICAL_DISK:
1482 unit->au_SectorShift = 11;
1483 unit->au_Heads = 1;
1484 unit->au_Sectors = 75;
1485 unit->au_Cylinders = 4440;
1486 break;
1487
1488 case DG_DIRECT_ACCESS:
1489 unit->au_SectorShift = 9;
1490 if (!strcmp("LS-120", &unit->au_Model[0]))
1491 {
1492 unit->au_Heads = 2;
1493 unit->au_Sectors = 18;
1494 unit->au_Cylinders = 6848;
1495 }
1496 else if (!strcmp("ZIP 100 ", &unit->au_Model[8]))
1497 {
1498 unit->au_Heads = 1;
1499 unit->au_Sectors = 64;
1500 unit->au_Cylinders = 3072;
1501 }
1502 break;
1503 }
1504
1505 atapi_TestUnitOK(unit);
1506 }
1507 else
1508 {
1509 /*
1510 For drive capacities > 8.3GB assume maximal possible layout.
1511 It really doesn't matter here, as BIOS will not handle them in
1512 CHS way anyway :)
1513 i guess this just solves that weirdo div-by-zero crash, if nothing
1514 else...
1515 */
1516 if (supportLBA && ((unit->au_Drive->id_LBA48Sectors > (63 * 255 * 1024)) ||
1517 (unit->au_Drive->id_LBASectors > (63 * 255 * 1024))))
1518 {
1519 ULONG div = 1;
1520 /*
1521 * TODO: this shouldn't be casted down here.
1522 */
1523 ULONG sec = unit->au_Capacity48;
1524
1525 if (sec < unit->au_Capacity48)
1526 sec = ~((ULONG)0);
1527
1528 if (sec < unit->au_Capacity)
1529 sec = unit->au_Capacity;
1530
1531 unit->au_Sectors = 63;
1532 sec /= 63;
1533 /*
1534 * keep dividing by 2
1535 */
1536 do
1537 {
1538 if (((sec >> 1) << 1) != sec)
1539 break;
1540 if ((div << 1) > 255)
1541 break;
1542 div <<= 1;
1543 sec >>= 1;
1544 } while (1);
1545
1546 do
1547 {
1548 if (((sec / 3) * 3) != sec)
1549 break;
1550 if ((div * 3) > 255)
1551 break;
1552 div *= 3;
1553 sec /= 3;
1554 } while (1);
1555
1556 unit->au_Cylinders = sec;
1557 unit->au_Heads = div;
1558 }
1559 else
1560 {
1561 unit->au_Cylinders = unit->au_Drive->id_OldLCylinders;
1562 unit->au_Heads = unit->au_Drive->id_OldLHeads;
1563 unit->au_Sectors = unit->au_Drive->id_OldLSectors;
1564 if (!supportLBA) {
1565 unit->au_Capacity = unit->au_Cylinders * unit->au_Heads * unit->au_Sectors;
1566 unit->au_Capacity48 = unit->au_Capacity;
1567 }
1568 }
1569 }
1570
1571 DINIT(bug("[ATA%02ld] ata_Identify: Unit CHS: %d/%d/%d\n", unit->au_UnitNum, unit->au_Cylinders, unit->au_Heads, unit->au_Sectors));
1572
1573 return 0;
1574 }
1575
1576 /*
1577 * ata read32 commands
1578 */
1579 static BYTE ata_ReadSector32(struct ata_Unit *unit, ULONG block,
1580 ULONG count, APTR buffer, ULONG *act)
1581 {
1582 ata_CommandBlock acb =
1583 {
1584 ATA_READ,
1585 0,
1586 1,
1587 0,
1588 block,
1589 count,
1590 buffer,
1591 count << unit->au_SectorShift,
1592 0,
1593 CM_PIORead,
1594 (unit->au_Flags & AF_CHSOnly) ? CT_CHS : CT_LBA28,
1595 };
1596 BYTE err;
1597
1598 D(bug("[ATA%02ld] ata_ReadSector32()\n", unit->au_UnitNum));
1599
1600 *act = 0;
1601 if (0 != (err = ata_exec_blk(unit, &acb)))
1602 return err;
1603
1604 *act = count << unit->au_SectorShift;
1605 return 0;
1606 }
1607
1608 static BYTE ata_ReadMultiple32(struct ata_Unit *unit, ULONG block,
1609 ULONG count, APTR buffer, ULONG *act)
1610 {
1611 ata_CommandBlock acb =
1612 {
1613 ATA_READ_MULTIPLE,
1614 0,
1615 unit->au_Drive->id_RWMultipleSize & 0xff,
1616 0,
1617 block,
1618 count,
1619 buffer,
1620 count << unit->au_SectorShift,
1621 0,
1622 CM_PIORead,
1623 (unit->au_Flags & AF_CHSOnly) ? CT_CHS : CT_LBA28,
1624 };
1625 BYTE err;
1626
1627 D(bug("[ATA%02ld] ata_ReadMultiple32()\n", unit->au_UnitNum));
1628
1629 *act = 0;
1630 if (0 != (err = ata_exec_blk(unit, &acb)))
1631 return err;
1632
1633 *act = count << unit->au_SectorShift;
1634 return 0;
1635 }
1636
1637 static BYTE ata_ReadDMA32(struct ata_Unit *unit, ULONG block,
1638 ULONG count, APTR buffer, ULONG *act)
1639 {
1640 BYTE err;
1641 ata_CommandBlock acb =
1642 {
1643 ATA_READ_DMA,
1644 0,
1645 1,
1646 0,
1647 block,
1648 count,
1649 buffer,
1650 count << unit->au_SectorShift,
1651 0,
1652 CM_DMARead,
1653 (unit->au_Flags & AF_CHSOnly) ? CT_CHS : CT_LBA28,
1654 };
1655
1656 D(bug("[ATA%02ld] ata_ReadDMA32()\n", unit->au_UnitNum));
1657
1658 *act = 0;
1659 if (0 != (err = ata_exec_blk(unit, &acb)))
1660 return err;
1661
1662 *act = count << unit->au_SectorShift;
1663 return 0;
1664 }
1665
1666 /*
1667 * ata read64 commands
1668 */
1669 static BYTE ata_ReadSector64(struct ata_Unit *unit, UQUAD block,
1670 ULONG count, APTR buffer, ULONG *act)
1671 {
1672 ata_CommandBlock acb =
1673 {
1674 ATA_READ64,
1675 0,
1676 1,
1677 0,
1678 block,
1679 count,
1680 buffer,
1681 count << unit->au_SectorShift,
1682 0,
1683 CM_PIORead,
1684 CT_LBA48
1685 };
1686 BYTE err = 0;
1687
1688 D(bug("[ATA%02ld] ata_ReadSector64()\n", unit->au_UnitNum));
1689
1690 *act = 0;
1691 if (0 != (err = ata_exec_blk(unit, &acb)))
1692 return err;
1693
1694 *act = count << unit->au_SectorShift;
1695 return 0;
1696 }
1697
1698 static BYTE ata_ReadMultiple64(struct ata_Unit *unit, UQUAD block,
1699 ULONG count, APTR buffer, ULONG *act)
1700 {
1701 ata_CommandBlock acb =
1702 {
1703 ATA_READ_MULTIPLE64,
1704 0,
1705 unit->au_Drive->id_RWMultipleSize & 0xff,
1706 0,
1707 block,
1708 count,
1709 buffer,
1710 count << unit->au_SectorShift,
1711 0,
1712 CM_PIORead,
1713 CT_LBA48
1714 };
1715 BYTE err;
1716
1717 D(bug("[ATA%02ld] ata_ReadMultiple64()\n", unit->au_UnitNum));
1718
1719 *act = 0;
1720 if (0 != (err = ata_exec_blk(unit, &acb)))
1721 return err;
1722
1723 *act = count << unit->au_SectorShift;
1724 return 0;
1725 }
1726
1727 static BYTE ata_ReadDMA64(struct ata_Unit *unit, UQUAD block,
1728 ULONG count, APTR buffer, ULONG *act)
1729 {
1730 ata_CommandBlock acb =
1731 {
1732 ATA_READ_DMA64,
1733 0,
1734 1,
1735 0,
1736 block,
1737 count,
1738 buffer,
1739 count << unit->au_SectorShift,
1740 0,
1741 CM_DMARead,
1742 CT_LBA48
1743 };
1744 BYTE err;
1745
1746 D(bug("[ATA%02ld] ata_ReadDMA64()\n", unit->au_UnitNum));
1747
1748 *act = 0;
1749 if (0 != (err = ata_exec_blk(unit, &acb)))
1750 return err;
1751
1752 *act = count << unit->au_SectorShift;
1753 return 0;
1754 }
1755
1756 /*
1757 * ata write32 commands
1758 */
1759 static BYTE ata_WriteSector32(struct ata_Unit *unit, ULONG block,
1760 ULONG count, APTR buffer, ULONG *act)
1761 {
1762 ata_CommandBlock acb =
1763 {
1764 ATA_WRITE,
1765 0,
1766 1,
1767 0,
1768 block,
1769 count,
1770 buffer,
1771 count << unit->au_SectorShift,
1772 0,
1773 CM_PIOWrite,
1774 (unit->au_Flags & AF_CHSOnly) ? CT_CHS : CT_LBA28,
1775 };
1776 BYTE err;
1777
1778 D(bug("[ATA%02ld] ata_WriteSector32()\n", unit->au_UnitNum));
1779
1780 *act = 0;
1781 if (0 != (err = ata_exec_blk(unit, &acb)))
1782 return err;
1783
1784 *act = count << unit->au_SectorShift;
1785 return 0;
1786 }
1787
1788 static BYTE ata_WriteMultiple32(struct ata_Unit *unit, ULONG block,
1789 ULONG count, APTR buffer, ULONG *act)
1790 {
1791 ata_CommandBlock acb =
1792 {
1793 ATA_WRITE_MULTIPLE,
1794 0,
1795 unit->au_Drive->id_RWMultipleSize & 0xff,
1796 0,
1797 block,
1798 count,
1799 buffer,
1800 count << unit->au_SectorShift,
1801 0,
1802 CM_PIOWrite,
1803 (unit->au_Flags & AF_CHSOnly) ? CT_CHS : CT_LBA28,
1804 };
1805 BYTE err;
1806
1807 D(bug("[ATA%02ld] ata_WriteMultiple32()\n", unit->au_UnitNum));
1808
1809 *act = 0;
1810 if (0 != (err = ata_exec_blk(unit, &acb)))
1811 return err;
1812
1813 *act = count << unit->au_SectorShift;
1814 return 0;
1815 }
1816
1817 static BYTE ata_WriteDMA32(struct ata_Unit *unit, ULONG block,
1818 ULONG count, APTR buffer, ULONG *act)
1819 {
1820 ata_CommandBlock acb =
1821 {
1822 ATA_WRITE_DMA,
1823 0,
1824 1,
1825 0,
1826 block,
1827 count,
1828 buffer,
1829 count << unit->au_SectorShift,
1830 0,
1831 CM_DMAWrite,
1832 (unit->au_Flags & AF_CHSOnly) ? CT_CHS : CT_LBA28,
1833 };
1834 BYTE err;
1835
1836 D(bug("[ATA%02ld] ata_WriteDMA32()\n", unit->au_UnitNum));
1837
1838 *act = 0;
1839 if (0 != (err = ata_exec_blk(unit, &acb)))
1840 return err;
1841
1842 *act = count << unit->au_SectorShift;
1843 return 0;
1844 }
1845
1846 /*
1847 * ata write64 commands
1848 */
1849 static BYTE ata_WriteSector64(struct ata_Unit *unit, UQUAD block,
1850 ULONG count, APTR buffer, ULONG *act)
1851 {
1852 ata_CommandBlock acb =
1853 {
1854 ATA_WRITE64,
1855 0,
1856 1,
1857 0,
1858 block,
1859 count,
1860 buffer,
1861 count << unit->au_SectorShift,
1862 0,
1863 CM_PIOWrite,
1864 CT_LBA48
1865 };
1866 BYTE err;
1867
1868 D(bug("[ATA%02ld] ata_WriteSector64()\n", unit->au_UnitNum));
1869
1870 *act = 0;
1871 if (0 != (err = ata_exec_blk(unit, &acb)))
1872 return err;
1873
1874 *act = count << unit->au_SectorShift;
1875 return 0;
1876 }
1877
1878 static BYTE ata_WriteMultiple64(struct ata_Unit *unit, UQUAD block,
1879 ULONG count, APTR buffer, ULONG *act)
1880 {
1881 ata_CommandBlock acb =
1882 {
1883 ATA_WRITE_MULTIPLE64,
1884 0,
1885 unit->au_Drive->id_RWMultipleSize & 0xff,
1886 0,
1887 block,
1888 count,
1889 buffer,
1890 count << unit->au_SectorShift,
1891 0,
1892 CM_PIOWrite,
1893 CT_LBA48
1894 };
1895 BYTE err;
1896
1897 D(bug("[ATA%02ld] ata_WriteMultiple64()\n", unit->au_UnitNum));
1898
1899 *act = 0;
1900 if (0 != (err = ata_exec_blk(unit, &acb)))
1901 return err;
1902
1903 *act = count << unit->au_SectorShift;
1904 return 0;
1905 }
1906
1907 static BYTE ata_WriteDMA64(struct ata_Unit *unit, UQUAD block,
1908 ULONG count, APTR buffer, ULONG *act)
1909 {
1910 ata_CommandBlock acb =
1911 {
1912 ATA_WRITE_DMA64,
1913 0,
1914 1,
1915 0,
1916 block,
1917 count,
1918 buffer,
1919 count << unit->au_SectorShift,
1920 0,
1921 CM_DMAWrite,
1922 CT_LBA48
1923 };
1924 BYTE err;
1925
1926 D(bug("[ATA%02ld] ata_WriteDMA64()\n", unit->au_UnitNum));
1927
1928 *act = 0;
1929 if (0 != (err = ata_exec_blk(unit, &acb)))
1930 return err;
1931
1932 *act = count << unit->au_SectorShift;
1933 return 0;
1934 }
1935
1936 /*
1937 * ata miscellaneous commands
1938 */
1939 static BYTE ata_Eject(struct ata_Unit *unit)
1940 {
1941 ata_CommandBlock acb =
1942 {
1943 ATA_MEDIA_EJECT,
1944 0,
1945 0,
1946 0,
1947 0,
1948 0,
1949 0,
1950 0,
1951 0,
1952 CM_NoData,
1953 CT_NoBlock
1954 };
1955
1956 D(bug("[ATA%02ld] ata_Eject()\n", unit->au_UnitNum));
1957
1958 return ata_exec_cmd(unit, &acb);
1959 }
1960
1961 /*
1962 * atapi commands
1963 */
1964 int atapi_TestUnitOK(struct ata_Unit *unit)
1965 {
1966 UBYTE cmd[6] = {
1967 0
1968 };
1969 UBYTE sense[16] = {
1970 0
1971 };
1972 struct SCSICmd sc = {
1973 0
1974 };
1975 UWORD i;
1976
1977 D(bug("[ATA%02ld] atapi_TestUnitOK()\n", unit->au_UnitNum));
1978
1979 sc.scsi_Command = (void*) &cmd;
1980 sc.scsi_CmdLength = sizeof(cmd);
1981 sc.scsi_SenseData = (void*)&sense;
1982 sc.scsi_SenseLength = sizeof(sense);
1983 sc.scsi_Flags = SCSIF_AUTOSENSE;
1984
1985 DATAPI(bug("[ATA%02ld] atapi_TestUnitOK: Testing Unit Ready sense...\n", unit->au_UnitNum));
1986
1987 /* Send command twice, and take the second result, as some drives give
1988 * invalid (or at least not so useful) sense data straight after reset */
1989 for (i = 0; i < 2; i++)
1990 unit->au_DirectSCSI(unit, &sc);
1991 unit->au_SenseKey = sense[2];
1992
1993 /*
1994 * we may have just lost the disc...?
1995 */
1996 /*
1997 * per MMC, drives are expected to return 02-3a-0# status, when disc is not present
1998 * that would translate into following code:
1999 * int p1 = ((sense[2] == 2) && (sense[12] == 0x3a)) ? 1 : 0;
2000 * unfortunately, it's what MMC says, not what vendors code.
2001 */
2002 int p1 = (sense[2] == 2) ? 1 : 0;
2003 int p2 = (0 != (AF_DiscPresent & unit->au_Flags)) ? 1 : 0;
2004
2005 if (p1 == p2)
2006 {
2007 //unit->au_Flags ^= AF_DiscPresent;
2008 if (p1 == 0)
2009 unit->au_Flags |= AF_DiscPresent;
2010 else
2011 unit->au_Flags &= ~AF_DiscPresent;
2012
2013 unit->au_Flags |= AF_DiscChanged;
2014 }
2015
2016 DATAPI(bug("[ATA%02ld] atapi_TestUnitOK: Test Unit Ready sense: %02lx, Media %s\n", unit->au_UnitNum, sense[2], unit->au_Flags & AF_DiscPresent ? "PRESENT" : "ABSENT"));
2017 return sense[2];
2018 }
2019
2020 static BYTE atapi_Read(struct ata_Unit *unit, ULONG block, ULONG count,
2021 APTR buffer, ULONG *act)
2022 {
2023 UBYTE cmd[] = {
2024 SCSI_READ10, 0, block>>24, block>>16, block>>8, block, 0, count>>8, count, 0
2025 };
2026 struct SCSICmd sc = {
2027 0
2028 };
2029
2030 D(bug("[ATA%02ld] atapi_Read()\n", unit->au_UnitNum));
2031
2032 sc.scsi_Command = (void*) &cmd;
2033 sc.scsi_CmdLength = sizeof(cmd);
2034 sc.scsi_Data = buffer;
2035 sc.scsi_Length = count << unit->au_SectorShift;
2036 sc.scsi_Flags = SCSIF_READ;
2037
2038 return unit->au_DirectSCSI(unit, &sc);
2039 }
2040
2041 static BYTE atapi_Write(struct ata_Unit *unit, ULONG block, ULONG count,
2042 APTR buffer, ULONG *act)
2043 {
2044 UBYTE cmd[] = {
2045 SCSI_WRITE10, 0, block>>24, block>>16, block>>8, block, 0, count>>8, count, 0
2046 };
2047 struct SCSICmd sc = {
2048 0
2049 };
2050
2051 D(bug("[ATA%02ld] atapi_Write()\n", unit->au_UnitNum));
2052
2053 sc.scsi_Command = (void*) &cmd;
2054 sc.scsi_CmdLength = sizeof(cmd);
2055 sc.scsi_Data = buffer;
2056 sc.scsi_Length = count << unit->au_SectorShift;
2057 sc.scsi_Flags = SCSIF_WRITE;
2058
2059 return unit->au_DirectSCSI(unit, &sc);
2060 }
2061
2062 static BYTE atapi_Eject(struct ata_Unit *unit)
2063 {
2064 struct atapi_StartStop cmd = {
2065 command: SCSI_STARTSTOP,
2066 immediate: 1,
2067 flags: ATAPI_SS_EJECT,
2068 };
2069
2070 struct SCSICmd sc = {
2071 0
2072 };
2073
2074 D(bug("[ATA%02ld] atapi_Eject()\n", unit->au_UnitNum));
2075
2076 sc.scsi_Command = (void*) &cmd;
2077 sc.scsi_CmdLength = sizeof(cmd);
2078 sc.scsi_Flags = SCSIF_READ;
2079
2080 return unit->au_DirectSCSI(unit, &sc);
2081 }
2082
2083 static ULONG atapi_RequestSense(struct ata_Unit* unit, UBYTE* sense,
2084 ULONG senselen)
2085 {
2086 UBYTE cmd[] = {
2087 3, 0, 0, 0, senselen & 0xfe, 0
2088 };
2089 struct SCSICmd sc = {
2090 0
2091 };
2092
2093 D(bug("[ATA%02ld] atapi_RequestSense()\n", unit->au_UnitNum));
2094
2095 if ((senselen == 0) || (sense == 0))
2096 {
2097 return 0;
2098 }
2099 sc.scsi_Data = (void*)sense;
2100 sc.scsi_Length = senselen & 0xfe;
2101 sc.scsi_Command = (void*)&cmd;
2102 sc.scsi_CmdLength = 6;
2103 sc.scsi_Flags = SCSIF_READ;
2104
2105 unit->au_DirectSCSI(unit, &sc);
2106
2107 DATAPI(dump(sense, senselen));
2108 DATAPI(bug("[SENSE] atapi_RequestSense: sensed data: %lx %lx %lx\n", sense[2]&0xf, sense[12], sense[13]));
2109 return ((sense[2]&0xf)<<16) | (sense[12]<<8) | (sense[13]);
2110 }
2111
2112 static ULONG ata_ReadSignature(struct ata_Bus *bus, int unit,
2113 BOOL *DiagExecuted)
2114 {
2115 UBYTE tmp1, tmp2;
2116
2117 D(bug("[ATA ] ata_ReadSignature(%02ld)\n", unit));
2118
2119 PIO_Out(bus, DEVHEAD_VAL | (unit << 4), ata_DevHead);
2120 ata_WaitNano(400, bus->ab_Base);
2121 //ata_WaitTO(bus->ab_Timer, 0, 1, 0);
2122
2123 DINIT(bug("[ATA ] ata_ReadSignature: Status %02lx Device %02lx\n",
2124 ata_ReadStatus(bus), PIO_In(bus, ata_DevHead)));
2125
2126 /* Ok, ATA/ATAPI device. Get detailed signature */
2127 DINIT(bug("[ATA ] ata_ReadSignature: ATA[PI] device present. Attempting to detect specific subtype\n"));
2128
2129 tmp1 = PIO_In(bus, ata_LBAMid);
2130 tmp2 = PIO_In(bus, ata_LBAHigh);
2131
2132 DINIT(bug("[ATA ] ata_ReadSignature: Subtype check returned %02lx:%02lx (%04lx)\n", tmp1, tmp2, (tmp1 << 8) | tmp2));
2133
2134 switch ((tmp1 << 8) | tmp2)
2135 {
2136 case 0x14eb:
2137 DINIT(bug("[ATA ] ata_ReadSignature: Found signature for ATAPI device\n"));
2138 return DEV_ATAPI;
2139
2140 case 0x3cc3:
2141 DINIT(bug("[ATA ] ata_ReadSignature: Found signature for SATA device\n"));
2142 return DEV_SATA;
2143
2144 case 0x6996:
2145 DINIT(bug("[ATA ] ata_ReadSignature: Found signature for SATAPI device\n"));
2146 return DEV_SATAPI;
2147
2148 default:
2149 if (0 == (ata_ReadStatus(bus) & 0xfe)) {
2150 DINIT(bug("[ATA ] ata_ReadSignature: Found NONE\n"));
2151 return DEV_NONE;
2152 }
2153
2154 /* ATA_EXECUTE_DIAG is executed by both devices, do it only once */
2155 if (!*DiagExecuted)
2156 {
2157 DINIT(bug("[ATA ] ata_ReadSignature: ATA_EXECUTE_DIAG\n"));
2158 PIO_Out(bus, ATA_EXECUTE_DIAG, ata_Command);
2159 *DiagExecuted = TRUE;
2160 }
2161
2162 ata_WaitTO(bus->ab_Timer, 0, 2000, 0);
2163 while (ata_ReadStatus(bus) & ATAF_BUSY)
2164 ata_WaitNano(400, bus->ab_Base);
2165 //ata_WaitTO(bus->ab_Timer, 0, 1, 0);
2166
2167 DINIT(bug("[ATA ] ata_ReadSignature: ATAF_BUSY wait finished\n"));
2168
2169 PIO_Out(bus, DEVHEAD_VAL | (unit << 4), ata_DevHead);
2170 do
2171 {
2172 ata_WaitNano(400, bus->ab_Base);
2173 //ata_WaitTO(unit->au_Bus->ab_Timer, 0, 1, 0);
2174 }
2175 while (0 != (ATAF_BUSY & ata_ReadStatus(bus)));
2176 DINIT(bug("[ATA ] ata_ReadSignature: Further validating ATA signature: %lx & 0x7f = 1, %lx & 0x10 = unit\n",
2177 PIO_In(bus, ata_Error), PIO_In(bus, ata_DevHead)));
2178
2179 if ((PIO_In(bus, ata_Error) & 0x7f) == 1)
2180 {
2181 DINIT(bug("[ATA ] ata_ReadSignature: Found *valid* signature for ATA device\n"));
2182 /* this might still be an (S)ATAPI device, but we correct that in ata_Identify */
2183 return DEV_ATA;
2184 }
2185 DERROR(bug("[ATA ] ata_ReadSignature: Found signature for ATA "
2186 "device, but further validation failed\n"));
2187 return DEV_NONE;
2188 }
2189 }
2190
2191 static void ata_ResetBus(struct ata_Bus *bus)
2192 {
2193 struct ataBase *ATABase = bus->ab_Base;
2194 ULONG TimeOut;
2195 BOOL DiagExecuted = FALSE;
2196
2197 /*
2198 * Set and then reset the soft reset bit in the Device Control
2199 * register. This causes device 0 to be selected.
2200 */
2201 DINIT(bug("[ATA ] ata_ResetBus()\n"));
2202
2203 PIO_Out(bus, DEVHEAD_VAL, ata_DevHead); /* Select it never the less */
2204 ata_WaitNano(400, ATABase);
2205 //ata_WaitTO(bus->ab_Timer, 0, 1, 0);
2206
2207 if (bus->haveAltIO)
2208 {
2209 PIO_OutAlt(bus, ATACTLF_RESET | ATACTLF_INT_DISABLE, ata_AltControl);
2210 ata_WaitTO(bus->ab_Timer, 0, 10, 0); /* sleep 10us; min: 5us */
2211
2212 PIO_OutAlt(bus, ATACTLF_INT_DISABLE, ata_AltControl);
2213 }
2214 else
2215 {
2216 PIO_Out(bus, ATA_EXECUTE_DIAG, ata_Command);
2217 }
2218 ata_WaitTO(bus->ab_Timer, 0, 20000, 0); /* sleep 20ms; min: 2ms */
2219
2220 /* If there is a device 0, wait for device 0 to clear BSY */
2221 if (DEV_NONE != bus->ab_Dev[0])
2222 {
2223 DINIT(bug("[ATA ] ata_ResetBus: Wait for master to clear BSY\n"));
2224 TimeOut = 1000; /* Timeout 1s (1ms x 1000) */
2225
2226 while ( 1 )
2227 {
2228 if ((ata_ReadStatus(bus) & ATAF_BUSY) == 0)
2229 break;
2230 ata_WaitTO(bus->ab_Timer, 0, 1000, 0);
2231 if (!(--TimeOut)) {
2232 DINIT(bug("[ATA%02ld] ata_ResetBus: Master device Timed Out!\n"));
2233 bus->ab_Dev[0] = DEV_NONE;
2234 break;
2235 }
2236 }
2237 DINIT(bug("[ATA ] ata_ResetBus: Wait left after %d ms\n", 1000 - TimeOut));
2238 }
2239
2240 /* If there is a device 1, wait some time until device 1 allows
2241 * register access, but fail only if BSY isn't cleared */
2242 if (DEV_NONE != bus->ab_Dev[1])
2243 {
2244 DINIT(bug("[ATA ] ata_ResetBus: Wait DEV1 to allow access\n"));
2245 PIO_Out(bus, DEVHEAD_VAL | (1 << 4), ata_DevHead);
2246 ata_WaitNano(400, bus->ab_Base);
2247 //ata_WaitTO(bus->ab_Timer, 0, 1, 0);
2248
2249 TimeOut = 50; /* Timeout 50ms (1ms x 50) */
2250 while ( 1 )
2251 {
2252 if ((PIO_In(bus, ata_Count) == 0x01) && (PIO_In(bus, ata_LBALow) == 0x01))
2253 break;
2254 ata_WaitTO(bus->ab_Timer, 0, 1000, 0);
2255 if (!(--TimeOut))
2256 {
2257 DINIT(bug("[ATA ] ata_ResetBus: DEV1 1/2 TimeOut!\n"));
2258 break;
2259 }
2260 }
2261 DINIT(bug("[ATA ] ata_ResetBus: DEV1 1/2 Wait left after %d ms\n", 1000 - TimeOut));
2262
2263 DINIT(bug("[ATA ] ata_ResetBus: Wait for slave to clear BSY\n"));
2264 TimeOut = 1000; /* Timeout 1s (1ms x 1000) */
2265 while ( 1 )
2266 {
2267 if ((ata_ReadStatus(bus) & ATAF_BUSY) == 0)
2268 break;
2269 ata_WaitTO(bus->ab_Timer, 0, 1000, 0);
2270 if (!(--TimeOut)) {
2271 DINIT(bug("[ATA ] ata_ResetBus: Slave device Timed Out!\n"));
2272 bus->ab_Dev[1] = DEV_NONE;
2273 break;
2274 }
2275 }
2276 DINIT(bug("[ATA ] ata_ResetBus: Wait left after %d ms\n", 1000 - TimeOut));
2277 }
2278
2279 if (DEV_NONE != bus->ab_Dev[0])
2280 bus->ab_Dev[0] = ata_ReadSignature(bus, 0, &DiagExecuted);
2281 if (DEV_NONE != bus->ab_Dev[1])
2282 bus->ab_Dev[1] = ata_ReadSignature(bus, 1, &DiagExecuted);
2283 }
2284
2285 void ata_InitBus(struct ata_Bus *bus)
2286 {
2287 struct ataBase *ATABase = bus->ab_Base;
2288 OOP_Object *obj = OOP_OBJECT(ATABase->busClass, bus);
2289 IPTR haveAltIO;
2290 UBYTE tmp1, tmp2;
2291 UWORD i;
2292
2293 /*
2294 * initialize timer for the sake of scanning
2295 */
2296 bus->ab_Timer = ata_OpenTimer(bus->ab_Base);
2297
2298 OOP_GetAttr(obj, aHidd_ATABus_UseIOAlt, &haveAltIO);
2299 bus->haveAltIO = haveAltIO != 0;
2300
2301 DINIT(bug("[ATA ] ata_InitBus(%p)\n", bus));
2302
2303 bus->ab_Dev[0] = DEV_NONE;
2304 bus->ab_Dev[1] = DEV_NONE;
2305
2306 /* Check if device 0 and/or 1 is present on this bus. It may happen that
2307 a single drive answers for both device addresses, but the phantom
2308 drive will be filtered out later */
2309 for (i = 0; i < MAX_BUSUNITS; i++)
2310 {
2311 /* Select device and disable IRQs */
2312 PIO_Out(bus, DEVHEAD_VAL | (i << 4), ata_DevHead);
2313 ata_WaitTO(bus->ab_Timer, 0, 400, 0);
2314 PIO_OutAlt(bus, ATACTLF_INT_DISABLE, ata_AltControl);
2315
2316 /* Write some pattern to registers. This is a variant of a more
2317 common technique, with the difference that we don't use the
2318 sector count register because some bad ATAPI drives disallow
2319 writing to it */
2320 PIO_Out(bus, 0x55, ata_LBALow);
2321 PIO_Out(bus, 0xaa, ata_LBAMid);
2322 PIO_Out(bus, 0xaa, ata_LBALow);
2323 PIO_Out(bus, 0x55, ata_LBAMid);
2324 PIO_Out(bus, 0x55, ata_LBALow);
2325 PIO_Out(bus, 0xaa, ata_LBAMid);
2326
2327 tmp1 = PIO_In(bus, ata_LBALow);
2328 tmp2 = PIO_In(bus, ata_LBAMid);
2329 DB2(bug("[ATA ] ata_InitBus: Reply 0x%02X 0x%02X\n", tmp1, tmp2));
2330
2331 if ((tmp1 == 0x55) && (tmp2 == 0xaa))
2332 bus->ab_Dev[i] = DEV_UNKNOWN;
2333 DINIT(bug("[ATA ] ata_InitBus: Device type = 0x%02X\n", bus->ab_Dev[i]));
2334 }
2335
2336 ata_ResetBus(bus);
2337 ata_CloseTimer(bus->ab_Timer);
2338 DINIT(bug("[ATA ] ata_InitBus: Finished\n"));
2339 }
2340
2341 /*
2342 * not really sure what this is meant to be - TO BE REPLACED
2343 */
2344 static const ULONG ErrorMap[] = {
2345 CDERR_NotSpecified,
2346 CDERR_NoSecHdr,
2347 CDERR_NoDisk,
2348 CDERR_NoSecHdr,
2349 CDERR_NoSecHdr,
2350 CDERR_NOCMD,
2351 CDERR_NoDisk,
2352 CDERR_WriteProt,
2353 CDERR_NotSpecified,
2354 CDERR_NotSpecified,
2355 CDERR_NotSpecified,
2356 CDERR_ABORTED,
2357 CDERR_NotSpecified,
2358 CDERR_NotSpecified,
2359 CDERR_NoSecHdr,
2360 CDERR_NotSpecified,
2361 };
2362
2363 static BYTE atapi_EndCmd(struct ata_Unit *unit)
2364 {
2365 struct ata_Bus *bus = unit->au_Bus;
2366 UBYTE status;
2367
2368 DATAPI(bug("[ATA%02ld] atapi_EndCmd()\n", unit->au_UnitNum));
2369
2370 /*
2371 * read alternate status register (per specs)
2372 */
2373 status = PIO_InAlt(bus, ata_AltStatus);
2374 DATAPI(bug("[ATA%02ld] atapi_EndCmd: Alternate status: %lx\n", unit->au_UnitNum, status));
2375
2376 status = PIO_In(bus, atapi_Status);
2377
2378 DATAPI(bug("[ATA%02ld] atapi_EndCmd: Command complete. Status: %lx\n",
2379 unit->au_UnitNum, status));
2380
2381 if (!(status & ATAPIF_CHECK))
2382 {
2383 return 0;
2384 }
2385 else
2386 {
2387 status = PIO_In(bus, atapi_Error);
2388 DATAPI(bug("[ATA%02ld] atapi_EndCmd: Error code 0x%lx\n", unit->au_UnitNum, status >> 4));
2389 return ErrorMap[status >> 4];
2390 }
2391 }
Mirror of AROS' svn.