rom/usb/pciusb/ehcichip.h

   1 #ifndef EHCICHIP_H
   2 #define EHCICHIP_H
   3
   4 /*
   5  *----------------------------------------------------------------------------
   6  *             Includes for EHCI USB Controller
   7  *----------------------------------------------------------------------------
   8  *                   By Chris Hodges <chrisly@platon42.de>
   9  */
  10
  11 #include <exec/types.h>
  12 #include "hccommon.h"
  13
  14 /*
  15  * --------------------- EHCI registers ------------------------
  16  * Warning: These are BYTE offsets!
  17  */
  18
  19 #define EHCI_CAPLENGTH      0x000 /* Offset for operational registers */
  20 #define EHCI_HCIVERSION     0x002 /* HC Version Number */
  21 #define EHCI_HCSPARAMS      0x004 /* HC Structural Parameters */
  22 #define EHCI_HCCPARAMS      0x008 /* HC Capability Parameters */
  23 #define EHCI_HCSPPORTROUTE  0x00c /* HC Companion Port Route Description */
  24
  25 /* EHCI_HCSPARAMS defines */
  26 #define EHSB_PORTPOWERCTRL   4    /* Support for Port Power Control */
  27 #define EHSB_EXTPORTROUTING  7    /* Routing to companion ports via HCSSPORTROUTE array */
  28 #define EHSB_PORTINDICATORS 16    /* Support for Port Indicators */
  29
  30 #define EHSS_NUM_PORTS       0    /* Number of ports */
  31 #define EHSS_PORTS_PER_COMP  8    /* Ports per companion controller */
  32 #define EHSS_NUM_COMPANIONS 12    /* Number of companion controllers */
  33
  34 #define EHSF_PORTPOWERCTRL  (1UL<<EHSB_PORTPOWERCTRL)
  35 #define EHSF_EXTPORTROUTING (1UL<<EHSB_EXTPORTROUTING)
  36 #define EHSF_PORTINDICATORS (1UL<<EHSB_PORTINDICATORS)
  37
  38 #define EHSM_NUM_PORTS      (((1UL<<4)-1)<<EHSS_NUM_PORTS)
  39 #define EHSM_PORTS_PER_COMP (((1UL<<4)-1)<<EHSS_PORTS_PER_COMP)
  40 #define EHSM_NUM_COMPANIONS (((1UL<<4)-1)<<EHSS_NUM_COMPANIONS)
  41
  42 /* EHCI_HCCPARAMS defines */
  43 #define EHCB_64BITS          0    /* Use 64 Bit pointers and structures */
  44 #define EHCB_PROGFRAMELIST   1    /* Programmable Frame list size */
  45 #define EHCB_ASYNCSCHEDPARK  2    /* Park feature for highspeed QH supported */
  46 #define EHCS_EXTCAPOFFSET    8    /* Offset to extended capabilities registers */
  47
  48 #define EHCF_64BITS         (1UL<<EHCB_64BITS)
  49 #define EHCF_PROGFRAMELIST  (1UL<<EHCB_PROGFRAMELIST)
  50 #define EHCF_ASYNCSCHEDPARK (1UL<<EHCB_ASYNCSCHEDPARK)
  51 #define EHCM_EXTCAPOFFSET   (((1UL<<8)-1)<<EHCS_EXTCAPOFFSET)
  52
  53 /* Operational Registers */
  54 #define EHCI_USBCMD         0x000 /* USB Command (r/w) */
  55 #define EHCI_USBSTATUS      0x004 /* USB Status (r/wc) */
  56 #define EHCI_USBINTEN       0x008 /* USB Interrupt enable (r/w) */
  57 #define EHCI_FRAMECOUNT     0x00c /* Frame Number (r/w) */
  58 #define EHCI_CTRLDSSEGMENT  0x010 /* Upper 32 bits in 64 Bit mode */
  59 #define EHCI_PERIODICLIST   0x014 /* Periodic Frame List Base Address Register (4K aligned) */
  60 #define EHCI_ASYNCADDR      0x018 /* Asynchronous List Address Register (32 byte aligned) */
  61 #define EHCI_CONFIGFLAG     0x040 /* Configure flag (r/w) */
  62 #define EHCI_PORTSC1        0x044 /* Port Status & Control 1 (r/w) */
  63
  64 /* EHCI_USBCMD defines */
  65 #define EHUB_RUNSTOP         0    /* 1=Run, 0=Stop */
  66 #define EHUB_HCRESET         1    /* Host Controller Reset */
  67 #define EHUB_PERIODICENABLE  4    /* Enable Periodic Schedule */
  68 #define EHUB_ASYNCENABLE     5    /* Enable Async Schedule */
  69 #define EHUB_ASYNCDOORBELL   6    /* Cause interrupt on next Async schedule advance */
  70 #define EHUB_LIGHTHCRESET    7    /* Light Host Controller Reset */
  71 #define EHUB_ASYNCSCHEDPARK 11    /* Park Asynchroneous schedule */
  72
  73 #define EHUS_FRAMELISTSIZE   2    /* Size of framelist (divisor) */
  74 #define EHUS_ASYNCPARKCOUNT  8    /* Number of successive transactions before continuing async */
  75 #define EHUS_INTTHRESHOLD   16    /* Interrupt threshold control */
  76
  77 #define EHUF_RUNSTOP        (1UL<<EHUB_RUNSTOP)
  78 #define EHUF_HCRESET        (1UL<<EHUB_HCRESET)
  79 #define EHUF_PERIODICENABLE (1UL<<EHUB_PERIODICENABLE)
  80 #define EHUF_ASYNCENABLE    (1UL<<EHUB_ASYNCENABLE)
  81 #define EHUF_ASYNCDOORBELL  (1UL<<EHUB_ASYNCDOORBELL)
  82 #define EHUF_LIGHTHCRESET   (1UL<<EHUB_LIGHTHCRESET)
  83 #define EHUF_ASYNCSCHEDPARK (1UL<<EHUB_ASYNCSCHEDPARK)
  84
  85 #define EHUM_FRAMELISTSIZE  (((1UL<<2)-1)<<EHUS_FRAMELISTSIZE)
  86 #define EHUM_ASYNCPARKCOUNT (((1UL<<2)-1)<<EHUS_ASYNCPARKCOUNT)
  87 #define EHUM_INTTHRESHOLD   (((1UL<<8)-1)<<EHUS_INTTHRESHOLD)
  88
  89 /* EHCI_USBSTS and EHCI_USBINTEN (0-5) defines */
  90 #define EHSB_TDDONE          0    /* Transfer descriptor done */
  91 #define EHSB_TDERROR         1    /* Some TD has errored */
  92 #define EHSB_PORTCHANGED     2    /* Port Change detected */
  93 #define EHSB_FRAMECOUNTOVER  3    /* Frame List Rollover */
  94 #define EHSB_HOSTERROR       4    /* Host System Error */
  95 #define EHSB_ASYNCADVANCE    5    /* Async Schedule has advanced */
  96 #define EHSB_HCHALTED       12    /* Host controller halted */
  97 #define EHSB_RECLAMATION    13    /* Empty asynchrous schedule */
  98 #define EHSB_PERIODICACTIVE 14    /* Periodic schedule is running */
  99 #define EHSB_ASYNCACTIVE    15    /* Async schedule is running */
 100
 101 #define EHSF_TDDONE         (1UL<<EHSB_TDDONE)
 102 #define EHSF_TDERROR        (1UL<<EHSB_TDERROR)
 103 #define EHSF_PORTCHANGED    (1UL<<EHSB_PORTCHANGED)
 104 #define EHSF_FRAMECOUNTOVER (1UL<<EHSB_FRAMECOUNTOVER)
 105 #define EHSF_HOSTERROR      (1UL<<EHSB_HOSTERROR)
 106 #define EHSF_ASYNCADVANCE   (1UL<<EHSB_ASYNCADVANCE)
 107 #define EHSF_HCHALTED       (1UL<<EHSB_HCHALTED)
 108 #define EHSF_RECLAMATION    (1UL<<EHSB_RECLAMATION)
 109 #define EHSF_PERIODICACTIVE (1UL<<EHSB_PERIODICACTIVE)
 110 #define EHSF_ASYNCACTIVE    (1UL<<EHSB_ASYNCACTIVE)
 111
 112 #define EHSF_ALL_INTS       (EHSF_TDDONE|EHSF_TDERROR|EHSF_PORTCHANGED|EHSF_FRAMECOUNTOVER|EHSF_HOSTERROR|EHSF_ASYNCADVANCE)
 113
 114 /* EHCI_CONFIGFLAG defines */
 115 #define EHCB_CONFIGURED      0
 116 #define EHCF_CONFIGURED     (1UL<<EHCB_CONFIGURED)
 117
 118 /* EHCI_PORTSC defines */
 119 #define EHPB_PORTCONNECTED   0    /* Port Connection status */
 120 #define EHPB_CONNECTCHANGE   1    /* Port Connection change */
 121 #define EHPB_PORTENABLE      2    /* Enable Port */
 122 #define EHPB_ENABLECHANGE    3    /* Port eanbled status changed */
 123 #define EHPB_OVERCURRENT     4    /* OVer current condition detected */
 124 #define EHPB_OVERCURRENTCHG  5    /* Over current condition changed */
 125 #define EHPB_RESUMEDTX       6    /* Resume detected */
 126 #define EHPB_PORTSUSPEND     7    /* Port is suspended */
 127 #define EHPB_PORTRESET       8    /* Port is in reset state */
 128 #define EHPB_LINESTATUS_DM  10    /* Line Status D- */
 129 #define EHPB_LINESTATUS_DP  11    /* Line Stauts D+ */
 130 #define EHPB_PORTPOWER      12    /* Depends on PortPowerControl */
 131 #define EHPB_NOTPORTOWNER   13    /* Inverse of CONFIGURED (0=Owner) */
 132 #define EHPB_WAKECONNECT    20    /* Wake on Connect */
 133 #define EHPB_WAKEDISCONNECT 21    /* Wake on Disconnect */
 134 #define EHPB_WAKEOCENABLE   22    /* Wake on Over Current Condition */
 135
 136 #define EHPS_PORTINDICATOR  14    /* Port indicator leds (0=off, 1=amber, 2=green) */
 137
 138 #define EHPF_PORTCONNECTED  (1UL<<EHPB_PORTCONNECTED)
 139 #define EHPF_CONNECTCHANGE  (1UL<<EHPB_CONNECTCHANGE)
 140 #define EHPF_PORTENABLE     (1UL<<EHPB_PORTENABLE)
 141 #define EHPF_ENABLECHANGE   (1UL<<EHPB_ENABLECHANGE)
 142 #define EHPF_OVERCURRENT    (1UL<<EHPB_OVERCURRENT)
 143 #define EHPF_OVERCURRENTCHG (1UL<<EHPB_OVERCURRENTCHG)
 144 #define EHPF_RESUMEDTX      (1UL<<EHPB_RESUMEDTX)
 145 #define EHPF_PORTSUSPEND    (1UL<<EHPB_PORTSUSPEND)
 146 #define EHPF_PORTRESET      (1UL<<EHPB_PORTRESET)
 147 #define EHPF_LINESTATUS_DM  (1UL<<EHPB_LINESTATUS_DM)
 148 #define EHPF_LINESTATUS_DP  (1UL<<EHPB_LINESTATUS_DP)
 149 #define EHPF_PORTPOWER      (1UL<<EHPB_PORTPOWER)
 150 #define EHPF_NOTPORTOWNER   (1UL<<EHPB_NOTPORTOWNER)
 151 #define EHPF_WAKECONNECT    (1UL<<EHPB_WAKECONNECT)
 152 #define EHPF_WAKEDISCONNECT (1UL<<EHPB_WAKEDISCONNECT)
 153 #define EHPF_WAKEOCENABLE   (1UL<<EHPB_WAKEOCENABLE)
 154
 155 #define EHPM_PORTINDICATOR  (((1UL<<2)-1)<<EHPS_PORTINDICATOR)
 156 #define EHPF_PORTIND_OFF    (0UL<<EHPS_PORTINDICATOR)
 157 #define EHPF_PORTIND_AMBER  (1UL<<EHPS_PORTINDICATOR)
 158 #define EHPF_PORTIND_GREEN  (2UL<<EHPS_PORTINDICATOR)
 159
 160 /* Legacy support register */
 161 #define EHLS_CAP_ID          0
 162 #define EHLB_BIOS_OWNER     16
 163 #define EHLB_OS_OWNER       24
 164
 165 #define EHLM_CAP_ID         (((1UL<<8)-1)<<EHLS_CAP_ID)
 166 #define EHLF_BIOS_OWNER     (1UL<<EHLB_BIOS_OWNER)
 167 #define EHLF_OS_OWNER       (1UL<<EHLB_OS_OWNER)
 168
 169 /* Legacy support control / status */
 170
 171 /* data structures */
 172
 173 #define EHCI_FRAMELIST_SIZE      1024
 174 #define EHCI_FRAMELIST_ALIGNMENT 0x0fff
 175
 176 #define EHCI_PAGE_SIZE           4096
 177 #define EHCI_PAGE_MASK           0xfffff000
 178 #define EHCI_OFFSET_MASK         0x00000fff
 179
 180 #define EHCI_TDQH_ALIGNMENT      0x001f
 181
 182 #define EHCI_QH_POOLSIZE         128
 183 #define EHCI_TD_POOLSIZE         512
 184
 185 #define EHCI_TD_BULK_LIMIT       (128<<10) // limit for one batch of BULK data TDs
 186
 187 struct EhciTD
 188 {
 189     struct EhciTD  *etd_Succ;
 190     IPTR            etd_Unused0;
 191     ULONG           etd_Self;       /* LE PHYSICAL pointer to self */
 192     ULONG           etd_Length;     /* Number of bytes to transfer within this */
 193 #if __WORDSIZE == 64
 194     IPTR            etd_Unused1;
 195 #endif
 196     IPTR            etd_Unused[4];
 197
 198     /* aligned to 32 bytes */
 199     ULONG           etd_NextTD;     /* LE PHYSICAL pointer to next qTD */
 200     ULONG           etd_AltNextTD;  /* LE PHYSICAL alternate pointer to next qTD on short packet */
 201     ULONG           etd_CtrlStatus; /* LE Control and Status word */
 202     ULONG           etd_BufferPtr[5]; /* LE Buffer Pointers */
 203
 204     ULONG           etd_ExtBufferPtr[5]; /* LE Buffer Pointers (upper 32 bit) */
 205     ULONG           etd_Unused2[3];
 206 };
 207
 208 struct EhciQH
 209 {
 210     struct EhciQH  *eqh_Succ;
 211     struct EhciQH  *eqh_Pred;
 212     ULONG           eqh_Self;       /* LE PHYSICAL pointer to self + UHCI_QHSELECT */
 213 #if __WORDSIZE == 64
 214     ULONG           eqh_Unused1;    // Fill te gap
 215 #endif
 216     struct IOUsbHWReq *eqh_IOReq;   /* IO Request this belongs to */
 217
 218     struct EhciTD  *eqh_FirstTD;    /* First TD */
 219     IPTR            eqh_Actual;     /* Number of bytes for successful completion in this QH */
 220     APTR            eqh_Buffer;     /* Mirror buffer for data outside of DMA-accessible area */
 221     APTR            eqh_SetupBuf;   /* Mirror buffer for setup packet */
 222
 223     /* aligned to 32 bytes */
 224     ULONG           eqh_NextQH;     /* LE PHYSICAL horizontal pointer to next QH */
 225     ULONG           eqh_EPCaps;     /* LE Endpoint Capabilities/Characteristics word */
 226     ULONG           eqh_SplitCtrl;  /* LE Split and Int control stuff */
 227     ULONG           eqh_CurrTD;     /* LE PHYSICAL current TD pointer */
 228
 229     /* Transaction working space for host controller */
 230     ULONG           eqh_NextTD;     /* LE PHYSICAL pointer to next qTD */
 231     ULONG           eqh_AltNextTD;  /* LE PHYSICAL alternate pointer to next qTD on short packet */
 232     ULONG           eqh_CtrlStatus; /* LE Control and Status word */
 233     ULONG           eqh_BufferPtr[5]; /* LE Buffer Pointers */
 234
 235     ULONG           eqh_ExtBufferPtr[5]; /* LE Buffer Pointers (upper 32 bit) */
 236     ULONG           eqh_Unused[7];
 237 };
 238
 239 /* pointer defines */
 240
 241 #define EHCI_PTRMASK        0xffffffe0 /* frame list pointer mask */
 242 #define EHCI_TERMINATE      0x00000001 /* terminate list here */
 243 #define EHCI_ISOTD          0x00000000 /* isochronous TD */
 244 #define EHCI_QUEUEHEAD      0x00000002 /* pointer is a queue head */
 245 #define EHCI_SPLITISOTD     0x00000004 /* split transaction isochronous TD */
 246 #define EHCI_FRAMESPAN      0x00000006 /* frame span traversal node */
 247
 248 /* TD control and status word defines */
 249
 250 #define ETSB_PING            0    /* PING state instead of OUT */
 251 #define ETSB_SPLITERR        0    /* periodic split transaction error handshake */
 252 #define ETSB_COMPLETESPLIT   1    /* In complete-split state */
 253 #define ETSB_MISSEDCSPLIT    2    /* Missed Micro-frame for complete-split */
 254 #define ETSB_TRANSERR        3    /* Transaction error (Timeout, CRC, PID) */
 255 #define ETSB_BABBLE          4    /* Babble detected on the bus */
 256 #define ETSB_DATABUFFERERR   5    /* Data Buffer Error (Overrun / Underrun) */
 257 #define ETSB_HALTED          6    /* TD has been halted */
 258 #define ETCB_ACTIVE          7    /* TD is active / enable TD */
 259 #define ETCB_READYINTEN     15    /* Interrupt on Complete enable */
 260 #define ETCB_DATA1          31    /* Data toggle bit */
 261
 262 #define ETCS_PIDCODE         8    /* PID code */
 263 #define ETCS_ERRORLIMIT     10    /* how many errors permitted */
 264 #define ETSS_CURRENTPAGE    12    /* current page offset */
 265 #define ETSS_TRANSLENGTH    16    /* bytes to transfer */
 266
 267 #define ETSF_PING           (1UL<<ETSB_PING)
 268 #define ETSF_SPLITERR       (1UL<<ETSB_SPLITERR)
 269 #define ETSF_COMPLETESPLIT  (1UL<<ETSB_COMPLETESPLIT)
 270 #define ETSF_MISSEDCSPLIT   (1UL<<ETSB_MISSEDCSPLIT)
 271 #define ETSF_TRANSERR       (1UL<<ETSB_TRANSERR)
 272 #define ETSF_BABBLE         (1UL<<ETSB_BABBLE)
 273 #define ETSF_DATABUFFERERR  (1UL<<ETSB_DATABUFFERERR)
 274 #define ETSF_HALTED         (1UL<<ETSB_HALTED)
 275 #define ETCF_ACTIVE         (1UL<<ETCB_ACTIVE)
 276 #define ETCF_READYINTEN     (1UL<<ETCB_READYINTEN)
 277 #define ETCF_DATA1          (1UL<<ETCB_DATA1)
 278
 279 #define ETCM_PIDCODE        (((1UL<<2)-1)<<ETCS_PIDCODE)
 280 #define ETCF_PIDCODE_OUT    (0UL<<ETCS_PIDCODE)
 281 #define ETCF_PIDCODE_IN     (1UL<<ETCS_PIDCODE)
 282 #define ETCF_PIDCODE_SETUP  (2UL<<ETCS_PIDCODE)
 283
 284 #define ETCM_ERRORLIMIT     (((1UL<<2)-1)<<ETCS_ERRORLIMIT)
 285 #define ETCF_NOERRORLIMIT   (0UL<<ETCS_ERRORLIMIT)
 286 #define ETCF_1ERRORLIMIT    (1UL<<ETCS_ERRORLIMIT)
 287 #define ETCF_2ERRORSLIMIT   (2UL<<ETCS_ERRORLIMIT)
 288 #define ETCF_3ERRORSLIMIT   (3UL<<ETCS_ERRORLIMIT)
 289
 290 #define ETSM_CURRENTPAGE    (((1UL<<3)-1)<<ETSS_CURRENTPAGE)
 291 #define ETSM_TRANSLENGTH    (((1UL<<15)-1)<<ETSS_TRANSLENGTH)
 292
 293 /* QH EP Capabilitities */
 294
 295 #define EQEB_INACTIVATENEXT  7    /* Inactivate on next transaction for periodic schedule (FS/LS) */
 296 #define EQEB_LOWSPEED       12    /* Lowspeed transaction */
 297 #define EQEB_HIGHSPEED      13    /* Highspeed transaction */
 298 #define EQEB_TOGGLEFROMTD   14    /* Data toggle comes from TD */
 299 #define EQEB_RECLAMHEAD     15    /* Head Of Reclamation List Flag */
 300 #define EQEB_SPLITCTRLEP    27    /* For Fullspeed/Lowspeed, signal Control Endpoint */
 301
 302 #define EQES_DEVADDR         0    /* Device Address */
 303 #define EQES_ENDPOINT        8    /* Endpoint number */
 304 #define EQES_MAXPKTLEN      16    /* Maximum Packet Length */
 305 #define EQES_RELOAD         28    /* 0=Ignore NAKCOUNT, NAKCOUNT is loaded with this */
 306
 307 #define EQEF_INACTIVATENEXT (1UL<<EQEB_INACTIVATENEXT)
 308 #define EQEF_LOWSPEED       (1UL<<EQEB_LOWSPEED)
 309 #define EQEF_HIGHSPEED      (1UL<<EQEB_HIGHSPEED)
 310 #define EQEF_TOGGLEFROMTD   (1UL<<EQEB_TOGGLEFROMTD)
 311 #define EQEF_RECLAMHEAD     (1UL<<EQEB_RECLAMHEAD)
 312 #define EQEF_SPLITCTRLEP    (1UL<<EQEB_SPLITCTRLEP)
 313
 314 #define EQEM_DEVADDR        (((1UL<<7)-1)<<EQES_DEVADDR)
 315 #define EQEM_ENDPOINT       (((1UL<<4)-1)<<EQES_ENDPOINT)
 316 #define EQEM_MAXPKTLEN      (((1UL<<11)-1)<<EQES_MAXPKTLEN)
 317 #define EQEM_RELOAD         (((1UL<<4)-1)<<EQES_RELOAD)
 318
 319 /* QH Split Ctrl */
 320 #define EQSS_MUSOFACTIVE     0    /* µSOF Active */
 321 #define EQSS_MUSOFCSPLIT     8    /* When to send the complete split */
 322
 323 #define EQSS_HUBADDRESS     16    /* Hub Device Address for Split Transaction */
 324 #define EQSS_PORTNUMBER     23    /* Port Number of hub for Split Transaction */
 325 #define EQSS_MULTIPLIER     30    /* Multiplier, how many successive packets are sent */
 326
 327 #define EQSM_MUSOFACTIVE    (((1UL<<8)-1)<<EQSS_MUSOFACTIVE)
 328 #define EQSM_MUSOFCSPLIT    (((1UL<<8)-1)<<EQSS_MUSOFCSPLIT)
 329 #define EQSM_HUBADDRESS     (((1UL<<7)-1)<<EQSS_HUBADDRESS)
 330 #define EQSM_PORTNUMBER     (((1UL<<7)-1)<<EQSS_PORTNUMBER)
 331
 332 #define EQSM_MULTIPLIER     (((1UL<<2)-1)<<EQSS_MULTIPLIER)
 333 #define EQSF_MULTI_1        (1UL<<EQSS_MULTIPLIER)
 334 #define EQSF_MULTI_2        (2UL<<EQSS_MULTIPLIER)
 335 #define EQSF_MULTI_3        (3UL<<EQSS_MULTIPLIER)
 336
 337 #endif /* EHCICHIP_H */