rom/usb/pciusbhc/xhci/pcixhci_controller.h

   1 /*
   2     Copyright © 2014, The AROS Development Team. All rights reserved.
   3     $Id$
   4
   5     Desc:
   6     Lang: English
   7 */
   8 #ifndef PCIXHCICONTROLLER_H
   9 #define PCIXHCICONTROLLER_H
  10
  11
  12 /*
  13  *----------------------------------------------------------------------------
  14  *             Includes for XHCI USB Controller
  15  *----------------------------------------------------------------------------
  16  */
  17
  18 /*
  19     XHCI_xxx's are register indexes
  20     XHCB_xxx's are bitnumbers
  21     XHCF_xxx's are flags
  22     XHCM_xxx's are bitmasks
  23     XHCV_xxx(p)'s return shifted values from p
  24 */
  25
  26 #define READMEM32(rb) AROS_LE2LONG(*((volatile ULONG *) (rb)))
  27 #define WRITEMEM32(adr, value)     *((volatile ULONG *) (adr)) = AROS_LONG2LE(value)
  28
  29 #define WRITEREG16(rb, offset, value) *((volatile UWORD *) (((UBYTE *) (rb)) + ((ULONG) (offset)))) = AROS_WORD2LE(value)
  30 #define WRITEREG32(rb, offset, value) *((volatile ULONG *) (((UBYTE *) (rb)) + ((ULONG) (offset)))) = AROS_LONG2LE(value)
  31 #define WRITEREG64(rb, offset, value) *((volatile UQUAD *) (((UBYTE *) (rb)) + ((ULONG) (offset)))) = AROS_QUAD2LE(value)
  32
  33 #define  READREG8(rb, offset)             (*((volatile UBYTE *) (((UBYTE *) (rb)) + ((ULONG) (offset)))))
  34 #define READREG16(rb, offset) AROS_LE2WORD(*((volatile UWORD *) (((UBYTE *) (rb)) + ((ULONG) (offset)))))
  35 #define READREG32(rb, offset) AROS_LE2LONG(*((volatile ULONG *) (((UBYTE *) (rb)) + ((ULONG) (offset)))))
  36 #define READREG64(rb, offset) AROS_LE2QUAD(*((volatile UQUAD *) (((UBYTE *) (rb)) + ((ULONG) (offset)))))
  37
  38 #define operational_readl(reg)          READREG32(unit->hc.operational_base, reg)
  39 #define operational_readq(reg)          READREG64(unit->hc.operational_base, reg)
  40 #define operational_writel(reg, value) WRITEREG32(unit->hc.operational_base, reg, value)
  41 #define operational_writeq(reg, value) WRITEREG64(unit->hc.operational_base, reg, value)
  42
  43 #define capability_readl(reg) READREG32(unit->hc.capability_base, reg)
  44 #define capability_readw(reg) READREG16(unit->hc.capability_base, reg)
  45 #define capability_readb(reg)  READREG8(unit->hc.capability_base, reg)
  46
  47 #define doorbell_readl(reg) READREG32(unit->hc.doorbell_base, reg)
  48
  49 #define runtime_readl(reg)          READREG32(unit->hc.runtime_base, reg)
  50 #define runtime_writel(reg, value) WRITEREG32(unit->hc.runtime_base, reg, value)
  51 #define runtime_writeq(reg, value) WRITEREG64(unit->hc.runtime_base, reg, value)
  52
  53 /*
  54     XHCI capability register defines
  55
  56     All Capability Registers are Read-Only (RO).
  57     The offsets for these registers are all relative to the beginning of the host controller’s MMIO address space.
  58 */
  59 #define XHCI_CAPLENGTH  0x00
  60 #define XHCI_HCIVERSION 0x02
  61 #define XHCI_HCSPARAMS1 0x04
  62 #define XHCI_HCSPARAMS2 0x08
  63 #define XHCI_HCSPARAMS3 0x0C
  64 #define XHCI_HCCPARAMS1 0x10
  65 #define XHCI_DBOFF      0x14
  66 #define XHCV_DBOFF(p)   (p&~0x3)
  67 #define XHCI_RTSOFF     0x18
  68 #define XHCV_RTSOFF(p)  (p&~0xf)
  69
  70
  71 /* XHCI_HCSPARAMS1 defines */
  72 #define XHCB_MaxSlots   0
  73 #define XHCB_MaxIntrs   8
  74 #define XHCB_MaxPorts   24
  75
  76 #define XHCM_MaxSlots (((1UL<<8)-1)<<XHCB_MaxSlots)
  77 #define XHCM_MaxIntrs (((1UL<<11)-1)<<XHCB_MaxIntrs)
  78 #define XHCM_MaxPorts (((1UL<<8)-1)<<XHCB_MaxPorts)
  79
  80 #define XHCV_MaxPorts(p)    (((p)&XHCM_MaxPorts)>>XHCB_MaxPorts)
  81 #define XHCV_MaxIntrs(p)    (((p)&XHCM_MaxIntrs)>>XHCB_MaxIntrs)
  82 #define XHCV_MaxSlots(p)    (((p)&XHCM_MaxSlots)>>XHCB_MaxSlots)
  83
  84
  85 /* XHCI_HCSPARAMS2 defines */
  86 #define XHCB_IST        0
  87 #define XHCB_ERST_Max   4
  88 #define XHCB_SPR        26
  89 #define XHCB_SPB_Max    27
  90
  91 #define XHCM_IST         (((1UL<<4)-1)<<XHCB_IST)
  92 #define XHCM_ERST_Max    (((1UL<<4)-1)<<XHCB_ERST_Max)
  93 #define XHCV_ERST_Max(p) (((p)&XHCM_ERST_Max)>>XHCB_ERST_Max)
  94 #define XHCF_SPR         (1UL<<XHCB_SPR)
  95 #define XHCM_SPB_Max     (((1UL<<5)-1)<<XHCB_SPB_Max)
  96 #define XHCV_SPB_Max(p)  (((p)&XHCM_SPB_Max)>>XHCB_SPB_Max)
  97
  98 #define XHCI_MAX_SCRATCHPADS    31
  99
 100 /* XHCI_HCSPARAMS3 defines */
 101 #define XHCB_U1DEV_LAT  0
 102 #define XHCB_U2DEV_LAT  16
 103
 104 #define XHCM_U1DEV_LAT  (((1UL<<8)-1)<<XHCB_U1DEV_LAT)
 105 #define XHCM_U2DEV_LAT  (((1UL<<16)-1)<<XHCB_U2DEV_LAT)
 106
 107
 108 /* XHCI_HCCPARAMS1 defines */
 109 #define XHCB_AC64       0
 110 #define XHCB_BNC        1
 111 #define XHCB_CSZ        2
 112 #define XHCB_PPC        3
 113 #define XHCB_PIND       4
 114 #define XHCB_LHRC       5
 115 #define XHCB_LTC        6
 116 #define XHCB_NSS        7
 117 #define XHCB_MaxPSASize 12
 118 #define XHCB_xECP       16
 119
 120 #define XHCF_AC64       (1UL<<XHCB_AC64)
 121 #define XHCF_BNC        (1UL<<XHCB_BNC)
 122 #define XHCF_CSZ        (1UL<<XHCB_CSZ)
 123 #define XHCF_PPC        (1UL<<XHCB_PPC)
 124 #define XHCF_PIND       (1UL<<XHCB_PIND)
 125 #define XHCF_LHRC       (1UL<<XHCB_LHRC)
 126 #define XHCF_LTC        (1UL<<XHCB_LTC)
 127 #define XHCF_NSS        (1UL<<XHCB_NSS)
 128 #define XHCM_MaxPSASize (((1UL<<4)-1)<<XHCB_MaxPSASize)
 129 #define XHCM_xECP       (((1UL<<16)-1)<<XHCB_xECP)
 130 #define XHCV_xECP(p)    ((((p)&XHCM_xECP)>>XHCB_xECP)<<2)
 131
 132
 133 /*
 134     XHCI runtime register defines
 135 */
 136 #define XHCI_MFINDEX    0
 137 #define XHCI_IMAN(n)    0x20+(32*n)
 138 #define XHCI_IMOD(n)    0x24+(32*n)
 139 #define XHCI_ERSTSZ(n)  0x28+(32*n)
 140 #define XHCI_ERSTBA(n)  0x30+(32*n)
 141 #define XHCI_ERDP(n)    0x38+(32*n)
 142
 143 #define XHCB_IMANIE     1
 144 #define XHCF_IMANIE     (1UL<<XHCB_IMANIE)
 145
 146
 147 /* Extended capability IDs */
 148 #define XHCB_EXT_CAPS_ID        0
 149 #define XHCB_EXT_CAPS_NEXT      8
 150 #define XHCB_EXT_CAPS_VALUE     16
 151
 152 #define XHCM_EXT_CAPS_ID        (((1UL<<8)-1)<<XHCB_EXT_CAPS_ID)
 153 #define XHCM_EXT_CAPS_NEXT      (((1UL<<8)-1)<<XHCB_EXT_CAPS_NEXT)
 154 #define XHCM_EXT_CAPS_VALUE     (((1UL<<16)-1)<<XHCB_EXT_CAPS_VALUE)
 155
 156 #define XHCV_EXT_CAPS_ID(p)     (((p)&XHCM_EXT_CAPS_ID)>>XHCB_EXT_CAPS_ID)
 157 #define XHCV_EXT_CAPS_NEXT(p)   ((((p)&XHCM_EXT_CAPS_NEXT)>>XHCB_EXT_CAPS_NEXT)<<2)
 158 #define XHCV_EXT_CAPS_VALUE(p)  (((p)&XHCM_EXT_CAPS_VALUE)>>XHCB_EXT_CAPS_VALUE)
 159
 160
 161 /* Reserved ID 0 */
 162 #define XHCI_EXT_CAPS_LEGACY    1
 163 #define XHCI_EXT_CAPS_PROTOCOL  2
 164 #define XHCI_EXT_CAPS_XPOWERMNG 3
 165 #define XHCI_EXT_CAPS_IOVIRT    4
 166 #define XHCI_EXT_CAPS_MSGINTR   5
 167 #define XHCI_EXT_CAPS_LOCALMEM  6
 168 /* Reserved IDs 7-9 */
 169 #define XHCI_EXT_CAPS_USBDEBUG  10
 170 /* Reserved IDs 11-16 */
 171 #define XHCI_EXT_CAPS_XMSGINTR  17
 172 /* Reserved IDs 18-191 */
 173 /* Vendor defined IDs 192-255 */
 174 #define XHCI_EXT_CAPS_MAX       255
 175
 176
 177 /* These are for XHCI_EXT_CAPS_LEGACY */
 178 /* USB Legacy Support Capability (USBLEGSUP) */
 179 #define XHCI_USBLEGSUP   0x00
 180 #define XHCB_BIOSOWNED   16
 181 #define XHCB_OSOWNED     24
 182 #define XHCF_BIOSOWNED  (1UL<<XHCB_BIOSOWNED)
 183 #define XHCF_OSOWNED    (1UL<<XHCB_OSOWNED)
 184
 185 /* USB Legacy Support Control/Status (USBLEGCTLSTS) */
 186 #define XHCI_USBLEGCTLSTS       0x04
 187 #define XHCB_SMI_USBE           0
 188 #define XHCB_SMI_HSEE           4
 189 #define XHCB_SMI_OSOE           13
 190 #define XHCB_SMI_PCICE          14
 191 #define XHCB_SMI_BARE           15
 192 #define XHCB_SMI_EI             16
 193 #define XHCB_SMI_HSE            20
 194 #define XHCB_SMI_OSOC           29
 195 #define XHCB_SMI_PCIC           30
 196 #define XHCB_SMI_BAR            31
 197
 198 #define XHCF_SMI_USBE           (1UL<<XHCB_SMI_USBE)
 199 #define XHCF_SMI_HSEE           (1UL<<XHCB_SMI_HSEE)
 200 #define XHCF_SMI_OSOE           (1UL<<XHCB_SMI_OSOE)
 201 #define XHCF_SMI_PCICE          (1UL<<XHCB_SMI_PCICE)
 202 #define XHCF_SMI_BARE           (1UL<<XHCB_SMI_BARE)
 203 #define XHCF_SMI_EI             (1UL<<XHCB_SMI_EI)
 204 #define XHCF_SMI_HSE            (1UL<<XHCB_SMI_HSE)
 205 #define XHCF_SMI_OSOC           (1UL<<XHCB_SMI_OSOC)
 206 #define XHCF_SMI_PCIC           (1UL<<XHCB_SMI_PCIC)
 207 #define XHCF_SMI_BAR            (1UL<<XHCB_SMI_BAR)
 208
 209
 210 /* These are for XHCI_EXT_CAPS_PROTOCOL */
 211 /* xHCI Supported Protocol Capability Field Definitions */
 212 #define XHCI_SPFD               0x00
 213 #define XHCB_SPFD_RMINOR        16
 214 #define XHCB_SPFD_RMAJOR        24
 215
 216 #define XHCM_SPFD_RMINOR        (((1UL<<8)-1)<<XHCB_SPFD_RMINOR)
 217 #define XHCM_SPFD_RMAJOR        (((1UL<<8)-1)<<XHCB_SPFD_RMAJOR)
 218
 219 #define XHCV_SPFD_RMINOR(p)    (((p)&XHCM_SPFD_RMINOR)>>XHCB_SPFD_RMINOR)
 220 #define XHCV_SPFD_RMAJOR(p)    (((p)&XHCM_SPFD_RMAJOR)>>XHCB_SPFD_RMAJOR)
 221
 222 #define XHCI_SPNAMESTRING       0x04
 223
 224 #define XHCI_SPPORT             0x08
 225 #define XHCB_SPPORT_CPO         0       /* Compatible Port Offset */
 226 #define XHCB_SPPORT_CPCNT       8       /* Compatible Port Count */
 227 #define XHCB_SPPORT_PD          16      /* Protocol Defined */
 228 #define XHCB_SPPORT_PSIC        28      /* Protocol Speed ID Count */
 229
 230 #define XHCM_SPPORT_CPO         (((1UL<<8)-1)<<XHCB_SPPORT_CPO)
 231 #define XHCM_SPPORT_CPCNT       (((1UL<<8)-1)<<XHCB_SPPORT_CPCNT)
 232 #define XHCM_SPPORT_PD          (((1UL<<12)-1)<<XHCB_SPPORT_PD)
 233 #define XHCM_SPPORT_PSIC        (((1UL<<4)-1)<<XHCB_SPPORT_PSIC)
 234
 235 #define XHCV_SPPORT_CPO(p)      (((p)&XHCM_SPPORT_CPO)>>XHCB_SPPORT_CPO)
 236 #define XHCV_SPPORT_CPCNT(p)    (((p)&XHCM_SPPORT_CPCNT)>>XHCB_SPPORT_CPCNT)
 237 #define XHCV_SPPORT_PD(p)       (((p)&XHCM_SPPORT_PD)>>XHCB_SPPORT_PD)
 238 #define XHCV_SPPORT_PSIC(p)     (((p)&XHCM_SPPORT_PSIC)>>XHCB_SPPORT_PSIC)
 239
 240 #define XHCI_SPPSI(psic) ((psic *4) + 0x10 )
 241 /* XHCI operational register defines */
 242 /* USB Command Register (USBCMD) */
 243 #define XHCI_USBCMD     0x00
 244
 245 #define XHCB_CMD_RS     0
 246 #define XHCB_CMD_HCRST  1
 247 #define XHCB_CMD_INTE   2
 248 #define XHCB_CMD_HSEE   3
 249 #define XHCB_CMD_LHCRST 7
 250 #define XHCB_CMD_CSS    8
 251 #define XHCB_CMD_CRS    9
 252 #define XHCB_CMD_EWE    10
 253 #define XHCB_CMD_EU3S   11
 254
 255 #define XHCF_CMD_RS     (1UL<<XHCB_CMD_RS)
 256 #define XHCF_CMD_HCRST  (1UL<<XHCB_CMD_HCRST)
 257 #define XHCF_CMD_INTE   (1UL<<XHCB_CMD_INTE)
 258 #define XHCF_CMD_HSEE   (1UL<<XHCB_CMD_HSEE)
 259 #define XHCF_CMD_LHCRST (1UL<<XHCB_CMD_LHCRST)
 260 #define XHCF_CMD_CSS    (1UL<<XHCB_CMD_CSS)
 261 #define XHCF_CMD_CRS    (1UL<<XHCB_CMD_CRS)
 262 #define XHCF_CMD_EWE    (1UL<<XHCB_CMD_EWE)
 263 #define XHCF_CMD_EU3S   (1UL<<XHCB_CMD_EU3S)
 264
 265 /* USB Status Register (USBSTS) */
 266 #define XHCI_USBSTS     0x04
 267 #define XHCB_STS_HCH    0
 268 #define XHCB_STS_HSE    2
 269 #define XHCB_STS_EINT   3
 270 #define XHCB_STS_PCD    4
 271 #define XHCB_STS_SSS    8
 272 #define XHCB_STS_RSS    9
 273 #define XHCB_STS_SRE    10
 274 #define XHCB_STS_CNR    11
 275 #define XHCB_STS_HCE    12
 276
 277 #define XHCF_STS_HCH    (1UL<<XHCB_STS_HCH)
 278 #define XHCF_STS_HSE    (1UL<<XHCB_STS_HSE)
 279 #define XHCF_STS_EINT   (1UL<<XHCB_STS_EINT)
 280 #define XHCF_STS_PCD    (1UL<<XHCB_STS_PCD)
 281 #define XHCF_STS_SSS    (1UL<<XHCB_STS_SSS)
 282 #define XHCF_STS_RSS    (1UL<<XHCB_STS_RSS)
 283 #define XHCF_STS_SRE    (1UL<<XHCB_STS_SRE)
 284 #define XHCF_STS_CNR    (1UL<<XHCB_STS_CNR)
 285 #define XHCF_STS_HCE    (1UL<<XHCB_STS_HCE)
 286
 287 /* Page Size Register (PAGESIZE) */
 288 #define XHCI_PAGESIZE   0x08
 289
 290 /* Device Notification Control Register (DNCTRL) */
 291 #define XHCI_DNCTRL     0x14
 292
 293 /* Command Ring Control Register (CRCR) */
 294 #define XHCI_CRCR       0x18
 295
 296 /* Device Context Base Address Array Pointer Register (DCBAAP) */
 297 #define XHCI_DCBAAP     0x30
 298
 299 /* Configure Register (CONFIG) */
 300 #define XHCI_CONFIG     0x38
 301 #define XHCB_CONFIG_MaxSlotsEn  0
 302 #define XHCM_CONFIG_MaxSlotsEn  (((1UL<<8)-1)<<XHCB_CONFIG_MaxSlotsEn)
 303
 304 /* Port Status and Control Register (PORTSC) */
 305 #define XHCI_PORTSC(port) (0x400 + (0x10 * (port-1)))
 306
 307 #define XHCB_PS_CCS     0
 308 #define XHCB_PS_PED     1
 309 #define XHCB_PS_OCA     3
 310 #define XHCB_PS_PR      4
 311 #define XHCB_PS_PLS     5
 312 #define XHCB_PS_PP      9
 313 #define XHCB_PS_SPEED   10
 314 #define XHCB_PS_PIC     14
 315 #define XHCB_PS_LWS     16
 316 #define XHCB_PS_CSC     17
 317 #define XHCB_PS_PEC     18
 318 #define XHCB_PS_WRC     19
 319 #define XHCB_PS_OCC     20
 320 #define XHCB_PS_PRC     21
 321 #define XHCB_PS_PLC     22
 322 #define XHCB_PS_CEC     23
 323 #define XHCB_PS_CAS     24
 324 #define XHCB_PS_WCE     25
 325 #define XHCB_PS_WDE     26
 326 #define XHCB_PS_WOE     27
 327 #define XHCB_PS_DR      30
 328 #define XHCB_PS_WPR     31
 329
 330 #define XHCF_PS_CCS     (1UL<<XHCB_PS_CCS)
 331 #define XHCF_PS_PED     (1UL<<XHCB_PS_PED)
 332 #define XHCF_PS_OCA     (1UL<<XHCB_PS_OCA)
 333 #define XHCF_PS_PR      (1UL<<XHCB_PS_PR)
 334 #define XHCM_PS_PLS     (((1UL<<4)-1)<<XHCB_PS_PLS)
 335 #define XHCF_PS_PP      (1UL<<XHCB_PS_PP)
 336 #define XHCM_PS_SPEED   (((1UL<<4)-1)<<XHCB_PS_SPEED)
 337 #define XHCM_PS_PIC     (((1UL<<2)-1)<<XHCB_PS_PIC)
 338 #define XHCF_PS_LWS     (1UL<<XHCB_PS_LWS)
 339 #define XHCF_PS_CSC     (1UL<<XHCB_PS_CSC)
 340 #define XHCF_PS_PEC     (1UL<<XHCB_PS_PEC)
 341 #define XHCF_PS_WRC     (1UL<<XHCB_PS_WRC)
 342 #define XHCF_PS_OCC     (1UL<<XHCB_PS_OCC)
 343 #define XHCF_PS_PRC     (1UL<<XHCB_PS_PRC)
 344 #define XHCF_PS_PLC     (1UL<<XHCB_PS_PLC)
 345 #define XHCF_PS_CEC     (1UL<<XHCB_PS_CEC)
 346 #define XHCF_PS_CAS     (1UL<<XHCB_PS_CAS)
 347 #define XHCF_PS_WCE     (1UL<<XHCB_PS_WCE)
 348 #define XHCF_PS_WDE     (1UL<<XHCB_PS_WDE)
 349 #define XHCF_PS_WOE     (1UL<<XHCB_PS_WOE)
 350 #define XHCF_PS_DR      (1UL<<XHCB_PS_DR)
 351 #define XHCF_PS_WPR     (1UL<<XHCB_PS_WPR)
 352 #define XHCV_PS_SPEED(p)    (((p)&XHCM_PS_SPEED)>>XHCB_PS_SPEED)
 353
 354 /* Event Ring Segment Table Entry */
 355 struct xhci_erste {
 356     UQUAD address;
 357     UWORD size;
 358     UWORD rsvd1;
 359         ULONG rsvd2;
 360 } __packed;
 361
 362 struct xhci_trb_template {
 363     UQUAD parameter;
 364     ULONG status;
 365     ULONG control;
 366 } __packed;
 367
 368
 369 /* TODO: define these */
 370 struct PCIXHCITransferRequestBlock {
 371         UQUAD   a;
 372         ULONG   b;
 373         ULONG   c;
 374 } __packed;
 375
 376 enum xhci_ring_type {
 377     TYPE_CTRL = 0,
 378     TYPE_ISOC,
 379     TYPE_BULK,
 380     TYPE_INTR,
 381     TYPE_STREAM,
 382     TYPE_COMMAND,
 383     TYPE_EVENT,
 384 };
 385
 386 #endif /* PCIXHCICONTROLLER_H */