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revert between 56095 -> 55830 in arch
[AROS.git] / tools / fd2inline / cross / share / m68k-amigaos / macros.h
blob6e75a23755c1e8e6f389eaaf9cfa2056f9d81609
1 #ifndef __INLINE_MACROS_H
2 #define __INLINE_MACROS_H
3
4 /*
5 General macros for Amiga function calls. Not all the possibilities have
6 been created - only the ones which exist in OS 3.1. Third party libraries
7 and future versions of AmigaOS will maybe need some new ones...
8
9 LPX - functions that take X arguments.
10
11 Modifiers (variations are possible):
12 NR - no return (void),
13 A4, A5 - "a4" or "a5" is used as one of the arguments,
14 UB - base will be given explicitly by user (see cia.resource).
15 FP - one of the parameters has type "pointer to function".
16
17 "bt" arguments are not used - they are provided for backward compatibility
18 only.
19 */
20
21 #ifndef __INLINE_STUB_H
22 #include <inline/stubs.h>
23 #endif
24
25 #define LP0(offs, rt, name, bt, bn) \
26 ({ \
27 { \
28 register rt _##name##_re __asm("d0"); \
29 register struct Library *const _##name##_bn __asm("a6") = (struct Library*)(bn); \
30 __asm volatile ("jsr a6@(-"#offs":W)" \
31 : "=r" (_##name##_re) \
32 : "r" (_##name##_bn) \
33 : "d0", "d1", "a0", "a1", "fp0", "fp1", "cc", "memory"); \
34 _##name##_re; \
35 } \
36 })
37
38 #define LP0NR(offs, name, bt, bn) \
39 ({ \
40 { \
41 register struct Library *const _##name##_bn __asm("a6") = (struct Library*)(bn); \
42 __asm volatile ("jsr a6@(-"#offs":W)" \
43 : /* no output */ \
44 : "r" (_##name##_bn) \
45 : "d0", "d1", "a0", "a1", "fp0", "fp1", "cc", "memory"); \
46 } \
47 })
48
49 #define LP1(offs, rt, name, t1, v1, r1, bt, bn) \
50 ({ \
51 t1 _##name##_v1 = (v1); \
52 { \
53 register rt _##name##_re __asm("d0"); \
54 register struct Library *const _##name##_bn __asm("a6") = (struct Library*)(bn); \
55 register t1 _n1 __asm(#r1) = _##name##_v1; \
56 __asm volatile ("jsr a6@(-"#offs":W)" \
57 : "=r" (_##name##_re) \
58 : "r" (_##name##_bn), "rf"(_n1) \
59 : "d0", "d1", "a0", "a1", "fp0", "fp1", "cc", "memory"); \
60 _##name##_re; \
61 } \
62 })
63
64 #define LP1NR(offs, name, t1, v1, r1, bt, bn) \
65 ({ \
66 t1 _##name##_v1 = (v1); \
67 { \
68 register struct Library *const _##name##_bn __asm("a6") = (struct Library*)(bn); \
69 register t1 _n1 __asm(#r1) = _##name##_v1; \
70 __asm volatile ("jsr a6@(-"#offs":W)" \
71 : /* no output */ \
72 : "r" (_##name##_bn), "rf"(_n1) \
73 : "d0", "d1", "a0", "a1", "fp0", "fp1", "cc", "memory"); \
74 } \
75 })
76
77 /* Only graphics.library/AttemptLockLayerRom() */
78 #define LP1A5(offs, rt, name, t1, v1, r1, bt, bn) \
79 ({ \
80 t1 _##name##_v1 = (v1); \
81 { \
82 register rt _##name##_re __asm("d0"); \
83 register struct Library *const _##name##_bn __asm("a6") = (struct Library*)(bn); \
84 register t1 _n1 __asm(#r1) = _##name##_v1; \
85 __asm volatile ("exg d7,a5\n\tjsr a6@(-"#offs":W)\n\texg d7,a5" \
86 : "=r" (_##name##_re) \
87 : "r" (_##name##_bn), "rf"(_n1) \
88 : "d0", "d1", "a0", "a1", "fp0", "fp1", "cc", "memory"); \
89 _##name##_re; \
90 } \
91 })
92
93 /* Only graphics.library/LockLayerRom() and graphics.library/UnlockLayerRom() */
94 #define LP1NRA5(offs, name, t1, v1, r1, bt, bn) \
95 ({ \
96 t1 _##name##_v1 = (v1); \
97 { \
98 register struct Library *const _##name##_bn __asm("a6") = (struct Library*)(bn); \
99 register t1 _n1 __asm(#r1) = _##name##_v1; \
100 __asm volatile ("exg d7,a5\n\tjsr a6@(-"#offs":W)\n\texg d7,a5" \
101 : /* no output */ \
102 : "r" (_##name##_bn), "rf"(_n1) \
103 : "d0", "d1", "a0", "a1", "fp0", "fp1", "cc", "memory"); \
104 } \
105 })
106
107 /* Only exec.library/Supervisor() */
108 #define LP1A5FP(offs, rt, name, t1, v1, r1, bt, bn, fpt) \
109 ({ \
110 typedef fpt; \
111 t1 _##name##_v1 = (v1); \
112 { \
113 register rt _##name##_re __asm("d0"); \
114 register struct Library *const _##name##_bn __asm("a6") = (struct Library*)(bn); \
115 register t1 _n1 __asm(#r1) = _##name##_v1; \
116 __asm volatile ("exg d7,a5\n\tjsr a6@(-"#offs":W)\n\texg d7,a5" \
117 : "=r" (_##name##_re) \
118 : "r" (_##name##_bn), "rf"(_n1) \
119 : "d0", "d1", "a0", "a1", "fp0", "fp1", "cc", "memory"); \
120 _##name##_re; \
121 } \
122 })
123
124 #define LP2(offs, rt, name, t1, v1, r1, t2, v2, r2, bt, bn) \
125 ({ \
126 t1 _##name##_v1 = (v1); \
127 t2 _##name##_v2 = (v2); \
128 { \
129 register rt _##name##_re __asm("d0"); \
130 register struct Library *const _##name##_bn __asm("a6") = (struct Library*)(bn); \
131 register t1 _n1 __asm(#r1) = _##name##_v1; \
132 register t2 _n2 __asm(#r2) = _##name##_v2; \
133 __asm volatile ("jsr a6@(-"#offs":W)" \
134 : "=r" (_##name##_re) \
135 : "r" (_##name##_bn), "rf"(_n1), "rf"(_n2) \
136 : "d0", "d1", "a0", "a1", "fp0", "fp1", "cc", "memory"); \
137 _##name##_re; \
138 } \
139 })
140
141 #define LP2NR(offs, name, t1, v1, r1, t2, v2, r2, bt, bn) \
142 ({ \
143 t1 _##name##_v1 = (v1); \
144 t2 _##name##_v2 = (v2); \
145 { \
146 register struct Library *const _##name##_bn __asm("a6") = (struct Library*)(bn); \
147 register t1 _n1 __asm(#r1) = _##name##_v1; \
148 register t2 _n2 __asm(#r2) = _##name##_v2; \
149 __asm volatile ("jsr a6@(-"#offs":W)" \
150 : /* no output */ \
151 : "r" (_##name##_bn), "rf"(_n1), "rf"(_n2) \
152 : "d0", "d1", "a0", "a1", "fp0", "fp1", "cc", "memory"); \
153 } \
154 })
155
156 /* Only cia.resource/AbleICR() and cia.resource/SetICR() */
157 #define LP2UB(offs, rt, name, t1, v1, r1, t2, v2, r2) \
158 ({ \
159 t1 _##name##_v1 = (v1); \
160 t2 _##name##_v2 = (v2); \
161 { \
162 register rt _##name##_re __asm("d0"); \
163 register t1 _n1 __asm(#r1) = _##name##_v1; \
164 register t2 _n2 __asm(#r2) = _##name##_v2; \
165 __asm volatile ("jsr a6@(-"#offs":W)" \
166 : "=r" (_##name##_re) \
167 : "r"(_n1), "rf"(_n2) \
168 : "d0", "d1", "a0", "a1", "fp0", "fp1", "cc", "memory"); \
169 _##name##_re; \
170 } \
171 })
172
173 /* Only dos.library/InternalUnLoadSeg() */
174 #define LP2FP(offs, rt, name, t1, v1, r1, t2, v2, r2, bt, bn, fpt) \
175 ({ \
176 typedef fpt; \
177 t1 _##name##_v1 = (v1); \
178 t2 _##name##_v2 = (v2); \
179 { \
180 register rt _##name##_re __asm("d0"); \
181 register struct Library *const _##name##_bn __asm("a6") = (struct Library*)(bn); \
182 register t1 _n1 __asm(#r1) = _##name##_v1; \
183 register t2 _n2 __asm(#r2) = _##name##_v2; \
184 __asm volatile ("jsr a6@(-"#offs":W)" \
185 : "=r" (_##name##_re) \
186 : "r" (_##name##_bn), "rf"(_n1), "rf"(_n2) \
187 : "d0", "d1", "a0", "a1", "fp0", "fp1", "cc", "memory"); \
188 _##name##_re; \
189 } \
190 })
191
192 #define LP3(offs, rt, name, t1, v1, r1, t2, v2, r2, t3, v3, r3, bt, bn) \
193 ({ \
194 t1 _##name##_v1 = (v1); \
195 t2 _##name##_v2 = (v2); \
196 t3 _##name##_v3 = (v3); \
197 { \
198 register rt _##name##_re __asm("d0"); \
199 register struct Library *const _##name##_bn __asm("a6") = (struct Library*)(bn); \
200 register t1 _n1 __asm(#r1) = _##name##_v1; \
201 register t2 _n2 __asm(#r2) = _##name##_v2; \
202 register t3 _n3 __asm(#r3) = _##name##_v3; \
203 __asm volatile ("jsr a6@(-"#offs":W)" \
204 : "=r" (_##name##_re) \
205 : "r" (_##name##_bn), "rf"(_n1), "rf"(_n2), "rf"(_n3) \
206 : "d0", "d1", "a0", "a1", "fp0", "fp1", "cc", "memory"); \
207 _##name##_re; \
208 } \
209 })
210
211 #define LP3NR(offs, name, t1, v1, r1, t2, v2, r2, t3, v3, r3, bt, bn) \
212 ({ \
213 t1 _##name##_v1 = (v1); \
214 t2 _##name##_v2 = (v2); \
215 t3 _##name##_v3 = (v3); \
216 { \
217 register struct Library *const _##name##_bn __asm("a6") = (struct Library*)(bn); \
218 register t1 _n1 __asm(#r1) = _##name##_v1; \
219 register t2 _n2 __asm(#r2) = _##name##_v2; \
220 register t3 _n3 __asm(#r3) = _##name##_v3; \
221 __asm volatile ("jsr a6@(-"#offs":W)" \
222 : /* no output */ \
223 : "r" (_##name##_bn), "rf"(_n1), "rf"(_n2), "rf"(_n3) \
224 : "d0", "d1", "a0", "a1", "fp0", "fp1", "cc", "memory"); \
225 } \
226 })
227
228 /* Only cia.resource/AddICRVector() */
229 #define LP3UB(offs, rt, name, t1, v1, r1, t2, v2, r2, t3, v3, r3) \
230 ({ \
231 t1 _##name##_v1 = (v1); \
232 t2 _##name##_v2 = (v2); \
233 t3 _##name##_v3 = (v3); \
234 { \
235 register rt _##name##_re __asm("d0"); \
236 register t1 _n1 __asm(#r1) = _##name##_v1; \
237 register t2 _n2 __asm(#r2) = _##name##_v2; \
238 register t3 _n3 __asm(#r3) = _##name##_v3; \
239 __asm volatile ("jsr a6@(-"#offs":W)" \
240 : "=r" (_##name##_re) \
241 : "r"(_n1), "rf"(_n2), "rf"(_n3) \
242 : "d0", "d1", "a0", "a1", "fp0", "fp1", "cc", "memory"); \
243 _##name##_re; \
244 } \
245 })
246
247 /* Only cia.resource/RemICRVector() */
248 #define LP3NRUB(offs, name, t1, v1, r1, t2, v2, r2, t3, v3, r3) \
249 ({ \
250 t1 _##name##_v1 = (v1); \
251 t2 _##name##_v2 = (v2); \
252 t3 _##name##_v3 = (v3); \
253 { \
254 register t1 _n1 __asm(#r1) = _##name##_v1; \
255 register t2 _n2 __asm(#r2) = _##name##_v2; \
256 register t3 _n3 __asm(#r3) = _##name##_v3; \
257 __asm volatile ("jsr a6@(-"#offs":W)" \
258 : /* no output */ \
259 : "r"(_n1), "rf"(_n2), "rf"(_n3) \
260 : "d0", "d1", "a0", "a1", "fp0", "fp1", "cc", "memory"); \
261 } \
262 })
263
264 /* Only exec.library/SetFunction() */
265 #define LP3FP(offs, rt, name, t1, v1, r1, t2, v2, r2, t3, v3, r3, bt, bn, fpt) \
266 ({ \
267 typedef fpt; \
268 t1 _##name##_v1 = (v1); \
269 t2 _##name##_v2 = (v2); \
270 t3 _##name##_v3 = (v3); \
271 { \
272 register rt _##name##_re __asm("d0"); \
273 register struct Library *const _##name##_bn __asm("a6") = (struct Library*)(bn); \
274 register t1 _n1 __asm(#r1) = _##name##_v1; \
275 register t2 _n2 __asm(#r2) = _##name##_v2; \
276 register t3 _n3 __asm(#r3) = _##name##_v3; \
277 __asm volatile ("jsr a6@(-"#offs":W)" \
278 : "=r" (_##name##_re) \
279 : "r" (_##name##_bn), "rf"(_n1), "rf"(_n2), "rf"(_n3) \
280 : "d0", "d1", "a0", "a1", "fp0", "fp1", "cc", "memory"); \
281 _##name##_re; \
282 } \
283 })
284
285 /* Only graphics.library/SetCollision() */
286 #define LP3NRFP(offs, name, t1, v1, r1, t2, v2, r2, t3, v3, r3, bt, bn, fpt) \
287 ({ \
288 typedef fpt; \
289 t1 _##name##_v1 = (v1); \
290 t2 _##name##_v2 = (v2); \
291 t3 _##name##_v3 = (v3); \
292 { \
293 register struct Library *const _##name##_bn __asm("a6") = (struct Library*)(bn); \
294 register t1 _n1 __asm(#r1) = _##name##_v1; \
295 register t2 _n2 __asm(#r2) = _##name##_v2; \
296 register t3 _n3 __asm(#r3) = _##name##_v3; \
297 __asm volatile ("jsr a6@(-"#offs":W)" \
298 : /* no output */ \
299 : "r" (_##name##_bn), "rf"(_n1), "rf"(_n2), "rf"(_n3) \
300 : "d0", "d1", "a0", "a1", "fp0", "fp1", "cc", "memory"); \
301 } \
302 })
303
304 #define LP4(offs, rt, name, t1, v1, r1, t2, v2, r2, t3, v3, r3, t4, v4, r4, bt, bn) \
305 ({ \
306 t1 _##name##_v1 = (v1); \
307 t2 _##name##_v2 = (v2); \
308 t3 _##name##_v3 = (v3); \
309 t4 _##name##_v4 = (v4); \
310 { \
311 register rt _##name##_re __asm("d0"); \
312 register struct Library *const _##name##_bn __asm("a6") = (struct Library*)(bn); \
313 register t1 _n1 __asm(#r1) = _##name##_v1; \
314 register t2 _n2 __asm(#r2) = _##name##_v2; \
315 register t3 _n3 __asm(#r3) = _##name##_v3; \
316 register t4 _n4 __asm(#r4) = _##name##_v4; \
317 __asm volatile ("jsr a6@(-"#offs":W)" \
318 : "=r" (_##name##_re) \
319 : "r" (_##name##_bn), "rf"(_n1), "rf"(_n2), "rf"(_n3), "rf"(_n4) \
320 : "d0", "d1", "a0", "a1", "fp0", "fp1", "cc", "memory"); \
321 _##name##_re; \
322 } \
323 })
324
325 #define LP4NR(offs, name, t1, v1, r1, t2, v2, r2, t3, v3, r3, t4, v4, r4, bt, bn) \
326 ({ \
327 t1 _##name##_v1 = (v1); \
328 t2 _##name##_v2 = (v2); \
329 t3 _##name##_v3 = (v3); \
330 t4 _##name##_v4 = (v4); \
331 { \
332 register struct Library *const _##name##_bn __asm("a6") = (struct Library*)(bn); \
333 register t1 _n1 __asm(#r1) = _##name##_v1; \
334 register t2 _n2 __asm(#r2) = _##name##_v2; \
335 register t3 _n3 __asm(#r3) = _##name##_v3; \
336 register t4 _n4 __asm(#r4) = _##name##_v4; \
337 __asm volatile ("jsr a6@(-"#offs":W)" \
338 : /* no output */ \
339 : "r" (_##name##_bn), "rf"(_n1), "rf"(_n2), "rf"(_n3), "rf"(_n4) \
340 : "d0", "d1", "a0", "a1", "fp0", "fp1", "cc", "memory"); \
341 } \
342 })
343
344 /* Only exec.library/RawDoFmt() */
345 #define LP4FP(offs, rt, name, t1, v1, r1, t2, v2, r2, t3, v3, r3, t4, v4, r4, bt, bn, fpt) \
346 ({ \
347 typedef fpt; \
348 t1 _##name##_v1 = (v1); \
349 t2 _##name##_v2 = (v2); \
350 t3 _##name##_v3 = (v3); \
351 t4 _##name##_v4 = (v4); \
352 { \
353 register rt _##name##_re __asm("d0"); \
354 register struct Library *const _##name##_bn __asm("a6") = (struct Library*)(bn); \
355 register t1 _n1 __asm(#r1) = _##name##_v1; \
356 register t2 _n2 __asm(#r2) = _##name##_v2; \
357 register t3 _n3 __asm(#r3) = _##name##_v3; \
358 register t4 _n4 __asm(#r4) = _##name##_v4; \
359 __asm volatile ("jsr a6@(-"#offs":W)" \
360 : "=r" (_##name##_re) \
361 : "r" (_##name##_bn), "rf"(_n1), "rf"(_n2), "rf"(_n3), "rf"(_n4) \
362 : "d0", "d1", "a0", "a1", "fp0", "fp1", "cc", "memory"); \
363 _##name##_re; \
364 } \
365 })
366
367 #define LP5(offs, rt, name, t1, v1, r1, t2, v2, r2, t3, v3, r3, t4, v4, r4, t5, v5, r5, bt, bn) \
368 ({ \
369 t1 _##name##_v1 = (v1); \
370 t2 _##name##_v2 = (v2); \
371 t3 _##name##_v3 = (v3); \
372 t4 _##name##_v4 = (v4); \
373 t5 _##name##_v5 = (v5); \
374 { \
375 register rt _##name##_re __asm("d0"); \
376 register struct Library *const _##name##_bn __asm("a6") = (struct Library*)(bn); \
377 register t1 _n1 __asm(#r1) = _##name##_v1; \
378 register t2 _n2 __asm(#r2) = _##name##_v2; \
379 register t3 _n3 __asm(#r3) = _##name##_v3; \
380 register t4 _n4 __asm(#r4) = _##name##_v4; \
381 register t5 _n5 __asm(#r5) = _##name##_v5; \
382 __asm volatile ("jsr a6@(-"#offs":W)" \
383 : "=r" (_##name##_re) \
384 : "r" (_##name##_bn), "rf"(_n1), "rf"(_n2), "rf"(_n3), "rf"(_n4), "rf"(_n5) \
385 : "d0", "d1", "a0", "a1", "fp0", "fp1", "cc", "memory"); \
386 _##name##_re; \
387 } \
388 })
389
390 #define LP5NR(offs, name, t1, v1, r1, t2, v2, r2, t3, v3, r3, t4, v4, r4, t5, v5, r5, bt, bn) \
391 ({ \
392 t1 _##name##_v1 = (v1); \
393 t2 _##name##_v2 = (v2); \
394 t3 _##name##_v3 = (v3); \
395 t4 _##name##_v4 = (v4); \
396 t5 _##name##_v5 = (v5); \
397 { \
398 register struct Library *const _##name##_bn __asm("a6") = (struct Library*)(bn); \
399 register t1 _n1 __asm(#r1) = _##name##_v1; \
400 register t2 _n2 __asm(#r2) = _##name##_v2; \
401 register t3 _n3 __asm(#r3) = _##name##_v3; \
402 register t4 _n4 __asm(#r4) = _##name##_v4; \
403 register t5 _n5 __asm(#r5) = _##name##_v5; \
404 __asm volatile ("jsr a6@(-"#offs":W)" \
405 : /* no output */ \
406 : "r" (_##name##_bn), "rf"(_n1), "rf"(_n2), "rf"(_n3), "rf"(_n4), "rf"(_n5) \
407 : "d0", "d1", "a0", "a1", "fp0", "fp1", "cc", "memory"); \
408 } \
409 })
410
411 /* Only exec.library/MakeLibrary() */
412 #define LP5FP(offs, rt, name, t1, v1, r1, t2, v2, r2, t3, v3, r3, t4, v4, r4, t5, v5, r5, bt, bn, fpt) \
413 ({ \
414 typedef fpt; \
415 t1 _##name##_v1 = (v1); \
416 t2 _##name##_v2 = (v2); \
417 t3 _##name##_v3 = (v3); \
418 t4 _##name##_v4 = (v4); \
419 t5 _##name##_v5 = (v5); \
420 { \
421 register rt _##name##_re __asm("d0"); \
422 register struct Library *const _##name##_bn __asm("a6") = (struct Library*)(bn); \
423 register t1 _n1 __asm(#r1) = _##name##_v1; \
424 register t2 _n2 __asm(#r2) = _##name##_v2; \
425 register t3 _n3 __asm(#r3) = _##name##_v3; \
426 register t4 _n4 __asm(#r4) = _##name##_v4; \
427 register t5 _n5 __asm(#r5) = _##name##_v5; \
428 __asm volatile ("jsr a6@(-"#offs":W)" \
429 : "=r" (_##name##_re) \
430 : "r" (_##name##_bn), "rf"(_n1), "rf"(_n2), "rf"(_n3), "rf"(_n4), "rf"(_n5) \
431 : "d0", "d1", "a0", "a1", "fp0", "fp1", "cc", "memory"); \
432 _##name##_re; \
433 } \
434 })
435
436 #define LP6(offs, rt, name, t1, v1, r1, t2, v2, r2, t3, v3, r3, t4, v4, r4, t5, v5, r5, t6, v6, r6, bt, bn) \
437 ({ \
438 t1 _##name##_v1 = (v1); \
439 t2 _##name##_v2 = (v2); \
440 t3 _##name##_v3 = (v3); \
441 t4 _##name##_v4 = (v4); \
442 t5 _##name##_v5 = (v5); \
443 t6 _##name##_v6 = (v6); \
444 { \
445 register rt _##name##_re __asm("d0"); \
446 register struct Library *const _##name##_bn __asm("a6") = (struct Library*)(bn); \
447 register t1 _n1 __asm(#r1) = _##name##_v1; \
448 register t2 _n2 __asm(#r2) = _##name##_v2; \
449 register t3 _n3 __asm(#r3) = _##name##_v3; \
450 register t4 _n4 __asm(#r4) = _##name##_v4; \
451 register t5 _n5 __asm(#r5) = _##name##_v5; \
452 register t6 _n6 __asm(#r6) = _##name##_v6; \
453 __asm volatile ("jsr a6@(-"#offs":W)" \
454 : "=r" (_##name##_re) \
455 : "r" (_##name##_bn), "rf"(_n1), "rf"(_n2), "rf"(_n3), "rf"(_n4), "rf"(_n5), "rf"(_n6) \
456 : "d0", "d1", "a0", "a1", "fp0", "fp1", "cc", "memory"); \
457 _##name##_re; \
458 } \
459 })
460
461 #define LP6NR(offs, name, t1, v1, r1, t2, v2, r2, t3, v3, r3, t4, v4, r4, t5, v5, r5, t6, v6, r6, bt, bn) \
462 ({ \
463 t1 _##name##_v1 = (v1); \
464 t2 _##name##_v2 = (v2); \
465 t3 _##name##_v3 = (v3); \
466 t4 _##name##_v4 = (v4); \
467 t5 _##name##_v5 = (v5); \
468 t6 _##name##_v6 = (v6); \
469 { \
470 register struct Library *const _##name##_bn __asm("a6") = (struct Library*)(bn); \
471 register t1 _n1 __asm(#r1) = _##name##_v1; \
472 register t2 _n2 __asm(#r2) = _##name##_v2; \
473 register t3 _n3 __asm(#r3) = _##name##_v3; \
474 register t4 _n4 __asm(#r4) = _##name##_v4; \
475 register t5 _n5 __asm(#r5) = _##name##_v5; \
476 register t6 _n6 __asm(#r6) = _##name##_v6; \
477 __asm volatile ("jsr a6@(-"#offs":W)" \
478 : /* no output */ \
479 : "r" (_##name##_bn), "rf"(_n1), "rf"(_n2), "rf"(_n3), "rf"(_n4), "rf"(_n5), "rf"(_n6) \
480 : "d0", "d1", "a0", "a1", "fp0", "fp1", "cc", "memory"); \
481 } \
482 })
483
484 #define LP7(offs, rt, name, t1, v1, r1, t2, v2, r2, t3, v3, r3, t4, v4, r4, t5, v5, r5, t6, v6, r6, t7, v7, r7, bt, bn) \
485 ({ \
486 t1 _##name##_v1 = (v1); \
487 t2 _##name##_v2 = (v2); \
488 t3 _##name##_v3 = (v3); \
489 t4 _##name##_v4 = (v4); \
490 t5 _##name##_v5 = (v5); \
491 t6 _##name##_v6 = (v6); \
492 t7 _##name##_v7 = (v7); \
493 { \
494 register rt _##name##_re __asm("d0"); \
495 register struct Library *const _##name##_bn __asm("a6") = (struct Library*)(bn); \
496 register t1 _n1 __asm(#r1) = _##name##_v1; \
497 register t2 _n2 __asm(#r2) = _##name##_v2; \
498 register t3 _n3 __asm(#r3) = _##name##_v3; \
499 register t4 _n4 __asm(#r4) = _##name##_v4; \
500 register t5 _n5 __asm(#r5) = _##name##_v5; \
501 register t6 _n6 __asm(#r6) = _##name##_v6; \
502 register t7 _n7 __asm(#r7) = _##name##_v7; \
503 __asm volatile ("jsr a6@(-"#offs":W)" \
504 : "=r" (_##name##_re) \
505 : "r" (_##name##_bn), "rf"(_n1), "rf"(_n2), "rf"(_n3), "rf"(_n4), "rf"(_n5), "rf"(_n6), "rf"(_n7) \
506 : "d0", "d1", "a0", "a1", "fp0", "fp1", "cc", "memory"); \
507 _##name##_re; \
508 } \
509 })
510
511 #define LP7NR(offs, name, t1, v1, r1, t2, v2, r2, t3, v3, r3, t4, v4, r4, t5, v5, r5, t6, v6, r6, t7, v7, r7, bt, bn) \
512 ({ \
513 t1 _##name##_v1 = (v1); \
514 t2 _##name##_v2 = (v2); \
515 t3 _##name##_v3 = (v3); \
516 t4 _##name##_v4 = (v4); \
517 t5 _##name##_v5 = (v5); \
518 t6 _##name##_v6 = (v6); \
519 t7 _##name##_v7 = (v7); \
520 { \
521 register struct Library *const _##name##_bn __asm("a6") = (struct Library*)(bn); \
522 register t1 _n1 __asm(#r1) = _##name##_v1; \
523 register t2 _n2 __asm(#r2) = _##name##_v2; \
524 register t3 _n3 __asm(#r3) = _##name##_v3; \
525 register t4 _n4 __asm(#r4) = _##name##_v4; \
526 register t5 _n5 __asm(#r5) = _##name##_v5; \
527 register t6 _n6 __asm(#r6) = _##name##_v6; \
528 register t7 _n7 __asm(#r7) = _##name##_v7; \
529 __asm volatile ("jsr a6@(-"#offs":W)" \
530 : /* no output */ \
531 : "r" (_##name##_bn), "rf"(_n1), "rf"(_n2), "rf"(_n3), "rf"(_n4), "rf"(_n5), "rf"(_n6), "rf"(_n7) \
532 : "d0", "d1", "a0", "a1", "fp0", "fp1", "cc", "memory"); \
533 } \
534 })
535
536 /* Only workbench.library/AddAppIconA() */
537 #define LP7A4(offs, rt, name, t1, v1, r1, t2, v2, r2, t3, v3, r3, t4, v4, r4, t5, v5, r5, t6, v6, r6, t7, v7, r7, bt, bn) \
538 ({ \
539 t1 _##name##_v1 = (v1); \
540 t2 _##name##_v2 = (v2); \
541 t3 _##name##_v3 = (v3); \
542 t4 _##name##_v4 = (v4); \
543 t5 _##name##_v5 = (v5); \
544 t6 _##name##_v6 = (v6); \
545 t7 _##name##_v7 = (v7); \
546 { \
547 register rt _##name##_re __asm("d0"); \
548 register struct Library *const _##name##_bn __asm("a6") = (struct Library*)(bn); \
549 register t1 _n1 __asm(#r1) = _##name##_v1; \
550 register t2 _n2 __asm(#r2) = _##name##_v2; \
551 register t3 _n3 __asm(#r3) = _##name##_v3; \
552 register t4 _n4 __asm(#r4) = _##name##_v4; \
553 register t5 _n5 __asm(#r5) = _##name##_v5; \
554 register t6 _n6 __asm(#r6) = _##name##_v6; \
555 register t7 _n7 __asm(#r7) = _##name##_v7; \
556 __asm volatile ("exg d7,a4\n\tjsr a6@(-"#offs":W)\n\texg d7,a4" \
557 : "=r" (_##name##_re) \
558 : "r" (_##name##_bn), "rf"(_n1), "rf"(_n2), "rf"(_n3), "rf"(_n4), "rf"(_n5), "rf"(_n6), "rf"(_n7) \
559 : "d0", "d1", "a0", "a1", "fp0", "fp1", "cc", "memory"); \
560 _##name##_re; \
561 } \
562 })
563
564 /* Would you believe that there really are beasts that need more than 7
565 arguments? :-) */
566
567 /* For example intuition.library/AutoRequest() */
568 #define LP8(offs, rt, name, t1, v1, r1, t2, v2, r2, t3, v3, r3, t4, v4, r4, t5, v5, r5, t6, v6, r6, t7, v7, r7, t8, v8, r8, bt, bn) \
569 ({ \
570 t1 _##name##_v1 = (v1); \
571 t2 _##name##_v2 = (v2); \
572 t3 _##name##_v3 = (v3); \
573 t4 _##name##_v4 = (v4); \
574 t5 _##name##_v5 = (v5); \
575 t6 _##name##_v6 = (v6); \
576 t7 _##name##_v7 = (v7); \
577 t8 _##name##_v8 = (v8); \
578 { \
579 register rt _##name##_re __asm("d0"); \
580 register struct Library *const _##name##_bn __asm("a6") = (struct Library*)(bn); \
581 register t1 _n1 __asm(#r1) = _##name##_v1; \
582 register t2 _n2 __asm(#r2) = _##name##_v2; \
583 register t3 _n3 __asm(#r3) = _##name##_v3; \
584 register t4 _n4 __asm(#r4) = _##name##_v4; \
585 register t5 _n5 __asm(#r5) = _##name##_v5; \
586 register t6 _n6 __asm(#r6) = _##name##_v6; \
587 register t7 _n7 __asm(#r7) = _##name##_v7; \
588 register t8 _n8 __asm(#r8) = _##name##_v8; \
589 __asm volatile ("jsr a6@(-"#offs":W)" \
590 : "=r" (_##name##_re) \
591 : "r" (_##name##_bn), "rf"(_n1), "rf"(_n2), "rf"(_n3), "rf"(_n4), "rf"(_n5), "rf"(_n6), "rf"(_n7), "rf"(_n8) \
592 : "d0", "d1", "a0", "a1", "fp0", "fp1", "cc", "memory"); \
593 _##name##_re; \
594 } \
595 })
596
597 /* For example intuition.library/ModifyProp() */
598 #define LP8NR(offs, name, t1, v1, r1, t2, v2, r2, t3, v3, r3, t4, v4, r4, t5, v5, r5, t6, v6, r6, t7, v7, r7, t8, v8, r8, bt, bn) \
599 ({ \
600 t1 _##name##_v1 = (v1); \
601 t2 _##name##_v2 = (v2); \
602 t3 _##name##_v3 = (v3); \
603 t4 _##name##_v4 = (v4); \
604 t5 _##name##_v5 = (v5); \
605 t6 _##name##_v6 = (v6); \
606 t7 _##name##_v7 = (v7); \
607 t8 _##name##_v8 = (v8); \
608 { \
609 register struct Library *const _##name##_bn __asm("a6") = (struct Library*)(bn); \
610 register t1 _n1 __asm(#r1) = _##name##_v1; \
611 register t2 _n2 __asm(#r2) = _##name##_v2; \
612 register t3 _n3 __asm(#r3) = _##name##_v3; \
613 register t4 _n4 __asm(#r4) = _##name##_v4; \
614 register t5 _n5 __asm(#r5) = _##name##_v5; \
615 register t6 _n6 __asm(#r6) = _##name##_v6; \
616 register t7 _n7 __asm(#r7) = _##name##_v7; \
617 register t8 _n8 __asm(#r8) = _##name##_v8; \
618 __asm volatile ("jsr a6@(-"#offs":W)" \
619 : /* no output */ \
620 : "r" (_##name##_bn), "rf"(_n1), "rf"(_n2), "rf"(_n3), "rf"(_n4), "rf"(_n5), "rf"(_n6), "rf"(_n7), "rf"(_n8) \
621 : "d0", "d1", "a0", "a1", "fp0", "fp1", "cc", "memory"); \
622 } \
623 })
624
625 /* For example layers.library/CreateUpfrontHookLayer() */
626 #define LP9(offs, rt, name, t1, v1, r1, t2, v2, r2, t3, v3, r3, t4, v4, r4, t5, v5, r5, t6, v6, r6, t7, v7, r7, t8, v8, r8, t9, v9, r9, bt, bn) \
627 ({ \
628 t1 _##name##_v1 = (v1); \
629 t2 _##name##_v2 = (v2); \
630 t3 _##name##_v3 = (v3); \
631 t4 _##name##_v4 = (v4); \
632 t5 _##name##_v5 = (v5); \
633 t6 _##name##_v6 = (v6); \
634 t7 _##name##_v7 = (v7); \
635 t8 _##name##_v8 = (v8); \
636 t9 _##name##_v9 = (v9); \
637 { \
638 register rt _##name##_re __asm("d0"); \
639 register struct Library *const _##name##_bn __asm("a6") = (struct Library*)(bn); \
640 register t1 _n1 __asm(#r1) = _##name##_v1; \
641 register t2 _n2 __asm(#r2) = _##name##_v2; \
642 register t3 _n3 __asm(#r3) = _##name##_v3; \
643 register t4 _n4 __asm(#r4) = _##name##_v4; \
644 register t5 _n5 __asm(#r5) = _##name##_v5; \
645 register t6 _n6 __asm(#r6) = _##name##_v6; \
646 register t7 _n7 __asm(#r7) = _##name##_v7; \
647 register t8 _n8 __asm(#r8) = _##name##_v8; \
648 register t9 _n9 __asm(#r9) = _##name##_v9; \
649 __asm volatile ("jsr a6@(-"#offs":W)" \
650 : "=r" (_##name##_re) \
651 : "r" (_##name##_bn), "rf"(_n1), "rf"(_n2), "rf"(_n3), "rf"(_n4), "rf"(_n5), "rf"(_n6), "rf"(_n7), "rf"(_n8), "rf"(_n9) \
652 : "d0", "d1", "a0", "a1", "fp0", "fp1", "cc", "memory"); \
653 _##name##_re; \
654 } \
655 })
656
657 /* For example intuition.library/NewModifyProp() */
658 #define LP9NR(offs, name, t1, v1, r1, t2, v2, r2, t3, v3, r3, t4, v4, r4, t5, v5, r5, t6, v6, r6, t7, v7, r7, t8, v8, r8, t9, v9, r9, bt, bn) \
659 ({ \
660 t1 _##name##_v1 = (v1); \
661 t2 _##name##_v2 = (v2); \
662 t3 _##name##_v3 = (v3); \
663 t4 _##name##_v4 = (v4); \
664 t5 _##name##_v5 = (v5); \
665 t6 _##name##_v6 = (v6); \
666 t7 _##name##_v7 = (v7); \
667 t8 _##name##_v8 = (v8); \
668 t9 _##name##_v9 = (v9); \
669 { \
670 register struct Library *const _##name##_bn __asm("a6") = (struct Library*)(bn); \
671 register t1 _n1 __asm(#r1) = _##name##_v1; \
672 register t2 _n2 __asm(#r2) = _##name##_v2; \
673 register t3 _n3 __asm(#r3) = _##name##_v3; \
674 register t4 _n4 __asm(#r4) = _##name##_v4; \
675 register t5 _n5 __asm(#r5) = _##name##_v5; \
676 register t6 _n6 __asm(#r6) = _##name##_v6; \
677 register t7 _n7 __asm(#r7) = _##name##_v7; \
678 register t8 _n8 __asm(#r8) = _##name##_v8; \
679 register t9 _n9 __asm(#r9) = _##name##_v9; \
680 __asm volatile ("jsr a6@(-"#offs":W)" \
681 : /* no output */ \
682 : "r" (_##name##_bn), "rf"(_n1), "rf"(_n2), "rf"(_n3), "rf"(_n4), "rf"(_n5), "rf"(_n6), "rf"(_n7), "rf"(_n8), "rf"(_n9) \
683 : "d0", "d1", "a0", "a1", "fp0", "fp1", "cc", "memory"); \
684 } \
685 })
686
687 /* Kriton Kyrimis <kyrimis@cti.gr> says CyberGraphics needs the following */
688 #define LP10(offs, rt, name, t1, v1, r1, t2, v2, r2, t3, v3, r3, t4, v4, r4, t5, v5, r5, t6, v6, r6, t7, v7, r7, t8, v8, r8, t9, v9, r9, t10, v10, r10, bt, bn) \
689 ({ \
690 t1 _##name##_v1 = (v1); \
691 t2 _##name##_v2 = (v2); \
692 t3 _##name##_v3 = (v3); \
693 t4 _##name##_v4 = (v4); \
694 t5 _##name##_v5 = (v5); \
695 t6 _##name##_v6 = (v6); \
696 t7 _##name##_v7 = (v7); \
697 t8 _##name##_v8 = (v8); \
698 t9 _##name##_v9 = (v9); \
699 t10 _##name##_v10 = (v10); \
700 { \
701 register rt _##name##_re __asm("d0"); \
702 register struct Library *const _##name##_bn __asm("a6") = (struct Library*)(bn); \
703 register t1 _n1 __asm(#r1) = _##name##_v1; \
704 register t2 _n2 __asm(#r2) = _##name##_v2; \
705 register t3 _n3 __asm(#r3) = _##name##_v3; \
706 register t4 _n4 __asm(#r4) = _##name##_v4; \
707 register t5 _n5 __asm(#r5) = _##name##_v5; \
708 register t6 _n6 __asm(#r6) = _##name##_v6; \
709 register t7 _n7 __asm(#r7) = _##name##_v7; \
710 register t8 _n8 __asm(#r8) = _##name##_v8; \
711 register t9 _n9 __asm(#r9) = _##name##_v9; \
712 register t10 _n10 __asm(#r10) = _##name##_v10; \
713 __asm volatile ("jsr a6@(-"#offs":W)" \
714 : "=r" (_##name##_re) \
715 : "r" (_##name##_bn), "rf"(_n1), "rf"(_n2), "rf"(_n3), "rf"(_n4), "rf"(_n5), "rf"(_n6), "rf"(_n7), "rf"(_n8), "rf"(_n9), "rf"(_n10) \
716 : "d0", "d1", "a0", "a1", "fp0", "fp1", "cc", "memory"); \
717 _##name##_re; \
718 } \
719 })
720
721 /* Only graphics.library/BltMaskBitMapRastPort() */
722 #define LP10NR(offs, name, t1, v1, r1, t2, v2, r2, t3, v3, r3, t4, v4, r4, t5, v5, r5, t6, v6, r6, t7, v7, r7, t8, v8, r8, t9, v9, r9, t10, v10, r10, bt, bn) \
723 ({ \
724 t1 _##name##_v1 = (v1); \
725 t2 _##name##_v2 = (v2); \
726 t3 _##name##_v3 = (v3); \
727 t4 _##name##_v4 = (v4); \
728 t5 _##name##_v5 = (v5); \
729 t6 _##name##_v6 = (v6); \
730 t7 _##name##_v7 = (v7); \
731 t8 _##name##_v8 = (v8); \
732 t9 _##name##_v9 = (v9); \
733 t10 _##name##_v10 = (v10); \
734 { \
735 register struct Library *const _##name##_bn __asm("a6") = (struct Library*)(bn); \
736 register t1 _n1 __asm(#r1) = _##name##_v1; \
737 register t2 _n2 __asm(#r2) = _##name##_v2; \
738 register t3 _n3 __asm(#r3) = _##name##_v3; \
739 register t4 _n4 __asm(#r4) = _##name##_v4; \
740 register t5 _n5 __asm(#r5) = _##name##_v5; \
741 register t6 _n6 __asm(#r6) = _##name##_v6; \
742 register t7 _n7 __asm(#r7) = _##name##_v7; \
743 register t8 _n8 __asm(#r8) = _##name##_v8; \
744 register t9 _n9 __asm(#r9) = _##name##_v9; \
745 register t10 _n10 __asm(#r10) = _##name##_v10; \
746 __asm volatile ("jsr a6@(-"#offs":W)" \
747 : /* no output */ \
748 : "r" (_##name##_bn), "rf"(_n1), "rf"(_n2), "rf"(_n3), "rf"(_n4), "rf"(_n5), "rf"(_n6), "rf"(_n7), "rf"(_n8), "rf"(_n9), "rf"(_n10) \
749 : "d0", "d1", "a0", "a1", "fp0", "fp1", "cc", "memory"); \
750 } \
751 })
752
753 /* Only graphics.library/BltBitMap() */
754 #define LP11(offs, rt, name, t1, v1, r1, t2, v2, r2, t3, v3, r3, t4, v4, r4, t5, v5, r5, t6, v6, r6, t7, v7, r7, t8, v8, r8, t9, v9, r9, t10, v10, r10, t11, v11, r11, bt, bn) \
755 ({ \
756 t1 _##name##_v1 = (v1); \
757 t2 _##name##_v2 = (v2); \
758 t3 _##name##_v3 = (v3); \
759 t4 _##name##_v4 = (v4); \
760 t5 _##name##_v5 = (v5); \
761 t6 _##name##_v6 = (v6); \
762 t7 _##name##_v7 = (v7); \
763 t8 _##name##_v8 = (v8); \
764 t9 _##name##_v9 = (v9); \
765 t10 _##name##_v10 = (v10); \
766 t11 _##name##_v11 = (v11); \
767 { \
768 register rt _##name##_re __asm("d0"); \
769 register struct Library *const _##name##_bn __asm("a6") = (struct Library*)(bn); \
770 register t1 _n1 __asm(#r1) = _##name##_v1; \
771 register t2 _n2 __asm(#r2) = _##name##_v2; \
772 register t3 _n3 __asm(#r3) = _##name##_v3; \
773 register t4 _n4 __asm(#r4) = _##name##_v4; \
774 register t5 _n5 __asm(#r5) = _##name##_v5; \
775 register t6 _n6 __asm(#r6) = _##name##_v6; \
776 register t7 _n7 __asm(#r7) = _##name##_v7; \
777 register t8 _n8 __asm(#r8) = _##name##_v8; \
778 register t9 _n9 __asm(#r9) = _##name##_v9; \
779 register t10 _n10 __asm(#r10) = _##name##_v10; \
780 register t11 _n11 __asm(#r11) = _##name##_v11; \
781 __asm volatile ("jsr a6@(-"#offs":W)" \
782 : "=r" (_##name##_re) \
783 : "r" (_##name##_bn), "rf"(_n1), "rf"(_n2), "rf"(_n3), "rf"(_n4), "rf"(_n5), "rf"(_n6), "rf"(_n7), "rf"(_n8), "rf"(_n9), "rf"(_n10), "rf"(_n11) \
784 : "d0", "d1", "a0", "a1", "fp0", "fp1", "cc", "memory"); \
785 _##name##_re; \
786 } \
787 })
788
789 #endif /* __INLINE_MACROS_H */
Mirror of AROS' svn.