workbench/devs/AHI/Drivers/VIA-AC97/hwaccess.h

   1 /*
   2     Copyright © 2005-2013, Davy Wentzler. All rights reserved.
   3     Copyright © 2010-2013, The AROS Development Team. All rights reserved.
   4     $Id$
   5 */
   6
   7 #ifndef _HWACCESS_H
   8 #define _HWACCESS_H
   9
  10 #define VIA_TABLE_SIZE  255
  11
  12 #define RECORD 0x10
  13
  14 /* common offsets */
  15 #define VIA_REG_OFFSET_STATUS           0x00    /* byte - channel status */
  16 #define   VIA_REG_STAT_ACTIVE           0x80    /* RO */
  17 #define   VIA_REG_STAT_PAUSED           0x40    /* RO */
  18 #define   VIA_REG_STAT_TRIGGER_QUEUED   0x08    /* RO */
  19 #define   VIA_REG_STAT_STOPPED          0x04    /* RWC */
  20 #define   VIA_REG_STAT_EOL              0x02    /* RWC */
  21 #define   VIA_REG_STAT_FLAG             0x01    /* RWC */
  22 #define VIA_REG_OFFSET_CONTROL          0x01    /* byte - channel control */
  23 #define   VIA_REG_CTRL_START            0x80    /* WO */
  24 #define   VIA_REG_CTRL_TERMINATE        0x40    /* WO */
  25 #define   VIA_REG_CTRL_AUTOSTART        0x20
  26 #define   VIA_REG_CTRL_PAUSE            0x08    /* RW */
  27 #define   VIA_REG_CTRL_INT_STOP         0x04
  28 #define   VIA_REG_CTRL_INT_EOL          0x02
  29 #define   VIA_REG_CTRL_INT_FLAG         0x01
  30 #define   VIA_REG_CTRL_RESET            0x01    /* RW - probably reset? undocumented */
  31 #define   VIA_REG_CTRL_INT (VIA_REG_CTRL_INT_FLAG | VIA_REG_CTRL_INT_EOL | VIA_REG_CTRL_AUTOSTART)
  32 #define VIA_REG_OFFSET_TYPE             0x02    /* byte - channel type (686 only) */
  33 #define   VIA_REG_TYPE_AUTOSTART        0x80    /* RW - autostart at EOL */
  34 #define   VIA_REG_TYPE_16BIT            0x20    /* RW */
  35 #define   VIA_REG_TYPE_STEREO           0x10    /* RW */
  36 #define   VIA_REG_TYPE_INT_LLINE        0x00
  37 #define   VIA_REG_TYPE_INT_LSAMPLE      0x04
  38 #define   VIA_REG_TYPE_INT_LESSONE      0x08
  39 #define   VIA_REG_TYPE_INT_MASK         0x0c
  40 #define   VIA_REG_TYPE_INT_EOL          0x02
  41 #define   VIA_REG_TYPE_INT_FLAG         0x01
  42 #define VIA_REG_OFFSET_TABLE_PTR        0x04    /* dword - channel table pointer */
  43 #define VIA_REG_OFFSET_CURR_PTR         0x04    /* dword - channel current pointer */
  44 #define VIA_REG_OFFSET_STOP_IDX         0x08    /* dword - stop index, channel type, sample rate */
  45 #define   VIA8233_REG_TYPE_16BIT        0x00200000      /* RW */
  46 #define   VIA8233_REG_TYPE_STEREO       0x00100000      /* RW */
  47 #define VIA_REG_OFFSET_CURR_COUNT       0x0c    /* dword - channel current count (24 bit) */
  48 #define VIA_REG_OFFSET_CURR_INDEX       0x0f    /* byte - channel current index (for via8233 only) */
  49
  50
  51
  52
  53 /* AC'97 */
  54 #define VIA_REG_AC97                    0x80    /* dword */
  55 #define   VIA_REG_AC97_CODEC_ID_MASK    (3<<30)
  56 #define   VIA_REG_AC97_CODEC_ID_SHIFT   30
  57 #define   VIA_REG_AC97_CODEC_ID_PRIMARY 0x00
  58 #define   VIA_REG_AC97_CODEC_ID_SECONDARY 0x01
  59 #define   VIA_REG_AC97_SECONDARY_VALID  (1<<27)
  60 #define   VIA_REG_AC97_PRIMARY_VALID    (1<<25)
  61 #define   VIA_REG_AC97_BUSY             (1<<24)
  62 #define   VIA_REG_AC97_READ             (1<<23)
  63 #define   VIA_REG_AC97_CMD_SHIFT        16
  64 #define   VIA_REG_AC97_CMD_MASK         0x7e
  65 #define   VIA_REG_AC97_DATA_SHIFT       0
  66 #define   VIA_REG_AC97_DATA_MASK        0xffff
  67
  68 #define VIA_REG_SGD_SHADOW              0x84    /* dword */
  69 /* via686 */
  70 #define   VIA_REG_SGD_STAT_PB_FLAG      (1<<0)
  71 #define   VIA_REG_SGD_STAT_CP_FLAG      (1<<1)
  72 #define   VIA_REG_SGD_STAT_FM_FLAG      (1<<2)
  73 #define   VIA_REG_SGD_STAT_PB_EOL       (1<<4)
  74 #define   VIA_REG_SGD_STAT_CP_EOL       (1<<5)
  75 #define   VIA_REG_SGD_STAT_FM_EOL       (1<<6)
  76 #define   VIA_REG_SGD_STAT_PB_STOP      (1<<8)
  77 #define   VIA_REG_SGD_STAT_CP_STOP      (1<<9)
  78 #define   VIA_REG_SGD_STAT_FM_STOP      (1<<10)
  79 #define   VIA_REG_SGD_STAT_PB_ACTIVE    (1<<12)
  80 #define   VIA_REG_SGD_STAT_CP_ACTIVE    (1<<13)
  81 #define   VIA_REG_SGD_STAT_FM_ACTIVE    (1<<14)
  82 /* via8233 */
  83 #define   VIA8233_REG_SGD_STAT_FLAG     (1<<0)
  84 #define   VIA8233_REG_SGD_STAT_EOL      (1<<1)
  85 #define   VIA8233_REG_SGD_STAT_STOP     (1<<2)
  86 #define   VIA8233_REG_SGD_STAT_ACTIVE   (1<<3)
  87 #define VIA8233_INTR_MASK(chan) ((VIA8233_REG_SGD_STAT_FLAG|VIA8233_REG_SGD_STAT_EOL) << ((chan) * 4))
  88 #define   VIA8233_REG_SGD_CHAN_SDX      0
  89 #define   VIA8233_REG_SGD_CHAN_MULTI    4
  90 #define   VIA8233_REG_SGD_CHAN_REC      6
  91 #define   VIA8233_REG_SGD_CHAN_REC1     7
  92
  93 #define VIA_REG_GPI_STATUS              0x88
  94 #define VIA_REG_GPI_INTR                0x8c
  95
  96 /* multi-channel and capture registers for via8233 */
  97 //DEFINE_VIA_REGSET(MULTPLAY, 0x40);
  98 //DEFINE_VIA_REGSET(CAPTURE_8233, 0x60);
  99
 100 /* via8233-specific registers */
 101 #define VIA_REG_OFS_PLAYBACK_VOLUME_L   0x02    /* byte */
 102 #define VIA_REG_OFS_PLAYBACK_VOLUME_R   0x03    /* byte */
 103 #define VIA_REG_OFS_MULTPLAY_FORMAT     0x02    /* byte - format and channels */
 104 #define   VIA_REG_MULTPLAY_FMT_8BIT     0x00
 105 #define   VIA_REG_MULTPLAY_FMT_16BIT    0x80
 106 #define   VIA_REG_MULTPLAY_FMT_CH_MASK  0x70    /* # channels << 4 (valid = 1,2,4,6) */
 107 #define VIA_REG_OFS_CAPTURE_FIFO        0x02    /* byte - bit 6 = fifo  enable */
 108 #define   VIA_REG_CAPTURE_FIFO_ENABLE   0x40
 109
 110 #define VIA_DXS_MAX_VOLUME              31      /* max. volume (attenuation) of reg 0x32/33 */
 111
 112 #define VIA_REG_CAPTURE_CHANNEL         0x63    /* byte - input select */
 113 #define   VIA_REG_CAPTURE_CHANNEL_MIC   0x4
 114 #define   VIA_REG_CAPTURE_CHANNEL_LINE  0
 115 #define   VIA_REG_CAPTURE_SELECT_CODEC  0x03    /* recording source codec (0 = primary) */
 116
 117 #define VIA_TBL_BIT_FLAG        0x40000000
 118 #define VIA_TBL_BIT_EOL         0x80000000
 119
 120 /* pci space */
 121 #define VIA_ACLINK_STAT         0x40
 122 #define  VIA_ACLINK_C11_READY   0x20
 123 #define  VIA_ACLINK_C10_READY   0x10
 124 #define  VIA_ACLINK_C01_READY   0x04 /* secondary codec ready */
 125 #define  VIA_ACLINK_LOWPOWER    0x02 /* low-power state */
 126 #define  VIA_ACLINK_C00_READY   0x01 /* primary codec ready */
 127 #define VIA_ACLINK_CTRL         0x41
 128 #define  VIA_ACLINK_CTRL_ENABLE 0x80 /* 0: disable, 1: enable */
 129 #define  VIA_ACLINK_CTRL_RESET  0x40 /* 0: assert, 1: de-assert */
 130 #define  VIA_ACLINK_CTRL_SYNC   0x20 /* 0: release SYNC, 1: force SYNC hi */
 131 #define  VIA_ACLINK_CTRL_SDO    0x10 /* 0: release SDO, 1: force SDO hi */
 132 #define  VIA_ACLINK_CTRL_VRA    0x08 /* 0: disable VRA, 1: enable VRA */
 133 #define  VIA_ACLINK_CTRL_PCM    0x04 /* 0: disable PCM, 1: enable PCM */
 134 #define  VIA_ACLINK_CTRL_FM     0x02 /* via686 only */
 135 #define  VIA_ACLINK_CTRL_SB     0x01 /* via686 only */
 136 #define  VIA_ACLINK_CTRL_INIT   (VIA_ACLINK_CTRL_ENABLE|\
 137                                  VIA_ACLINK_CTRL_RESET|\
 138                                  VIA_ACLINK_CTRL_PCM|\
 139                                  VIA_ACLINK_CTRL_VRA)
 140 #define VIA_FUNC_ENABLE         0x42
 141 #define  VIA_FUNC_MIDI_PNP      0x80 /* FIXME: it's 0x40 in the datasheet! */
 142 #define  VIA_FUNC_MIDI_IRQMASK  0x40 /* FIXME: not documented! */
 143 #define  VIA_FUNC_RX2C_WRITE    0x20
 144 #define  VIA_FUNC_SB_FIFO_EMPTY 0x10
 145 #define  VIA_FUNC_ENABLE_GAME   0x08
 146 #define  VIA_FUNC_ENABLE_FM     0x04
 147 #define  VIA_FUNC_ENABLE_MIDI   0x02
 148 #define  VIA_FUNC_ENABLE_SB     0x01
 149 #define VIA_PNP_CONTROL         0x43
 150 #define VIA_FM_NMI_CTRL         0x48
 151 #define VIA8233_VOLCHG_CTRL     0x48
 152 #define VIA8233_SPDIF_CTRL      0x49
 153 #define  VIA8233_SPDIF_DX3      0x08
 154 #define  VIA8233_SPDIF_SLOT_MASK        0x03
 155 #define  VIA8233_SPDIF_SLOT_1011        0x00
 156 #define  VIA8233_SPDIF_SLOT_34          0x01
 157 #define  VIA8233_SPDIF_SLOT_78          0x02
 158 #define  VIA8233_SPDIF_SLOT_69          0x03
 159
 160 /*
 161  */
 162
 163 #define VIA_DXS_AUTO    0
 164 #define VIA_DXS_ENABLE  1
 165 #define VIA_DXS_DISABLE 2
 166 #define VIA_DXS_48K     3
 167 #define VIA_DXS_NO_VRA  4
 168 #define VIA_DXS_SRC     5
 169
 170
 171 #define VOL_6BIT 0x40
 172 #define VOL_5BIT 0x20
 173 #define VOL_4BIT 0x10
 174
 175
 176 #endif  /* _HWACCESS_H */