workbench/devs/monitors/IntelGMA/intelG45_regs.h

   1 /*
   2  * intelG45_regs.h
   3  *
   4  *  Created on: Apr 17, 2010
   5  *      $Id$
   6  */
   7
   8 #include <stdint.h>
   9
  10 #ifndef INTELG45_REGS_H_
  11 #define INTELG45_REGS_H_
  12
  13 #define G45_MGCC                        0x52    /* Mirror of Dev0 GMCH Graphics Control */
  14
  15 #define G45_MGCC_IVD            0x0002  /* IGP VGA Disable */
  16
  17 #define G45_MGCC_GMS_MASK       0x00f0  /* Graphics Mode Select */
  18 #define G45_MGCC_GMS_1M         0x0010
  19 #define G45_MGCC_GMS_4M         0x0020
  20 #define G45_MGCC_GMS_8M         0x0030
  21 #define G45_MGCC_GMS_16M        0x0040
  22 #define G45_MGCC_GMS_32M        0x0050
  23 #define G45_MGCC_GMS_48M        0x0060
  24 #define G45_MGCC_GMS_64M        0x0070
  25
  26 #define G45_BSM                 0x5c
  27 #define G45_MSAC                        0x62
  28 #define G45_MSAC2                       0x66
  29
  30
  31 #define G45_GATT_CONTROL                                0x2020
  32
  33 /* Ring buffer registers */
  34 #define G45_RING_TAIL                                   0x2030
  35 #define G45_RING_TAIL_MASK                              0x1ffff8
  36
  37 #define G45_RING_HEAD                                   0x2034
  38 #define G45_RING_HEAD_WRAP_MASK         0x7ff
  39 #define G45_RING_HEAD_WRAP_SHIFT                21
  40 #define G45_RING_HEAD_MASK                              0x1ffffc
  41
  42 #define G45_RING_BASE                                   0x2038
  43 #define G45_RING_BASE_MASK                              0xfffff000
  44
  45 #define G45_RING_CONTROL                                0x203c
  46 #define G45_RING_CONTROL_LENGTH_MASK    0x1ff
  47 #define G45_RING_CONTROL_LENGTH_SHIFT   12
  48 #define G45_RING_CONTROL_WAIT                   0x00000800
  49 #define G45_RING_CONTROL_REPORT_OFF     0x00000000
  50 #define G45_RING_CONTROL_REPORT_64K     0x00000002
  51 #define G45_RING_CONTROL_REPORT_128K    0x00000006
  52 #define G45_RING_CONTROL_ENABLE         0x00000001
  53
  54 #define G45_GPIOA                       0x5010
  55 #define G45_GPIOB                       0x5014
  56 #define G45_GPIOC                       0x5018
  57 #define G45_GPIOD                       0x501c
  58 #define G45_GPIOE                       0x5020
  59 #define G45_GPIOF                       0x5024
  60 #define G45_GPIOG                       0x5028
  61 #define G45_GPIOH                       0x502c
  62
  63 #define G45_GPIO_CLOCK_DIR_MASK 0x0001
  64 #define G45_GPIO_CLOCK_DIR_VAL          0x0002
  65 #define G45_GPIO_CLOCK_DATA_MASK        0x0004
  66 #define G45_GPIO_CLOCK_DATA_VAL 0x0008
  67 #define G45_GPIO_CLOCK_DATA_IN          0x0010
  68 #define G45_GPIO_DATA_DIR_MASK          0x0100
  69 #define G45_GPIO_DATA_DIR_VAL           0x0200
  70 #define G45_GPIO_DATA_MASK                      0x0400
  71 #define G45_GPIO_DATA_VAL                       0x0800
  72 #define G45_GPIO_DATA_IN                        0x1000
  73
  74 #define G45_GMBUS                       0x5100
  75
  76 #define G45_PIPEASRC                            0x6001c
  77 #define G45_PIPEBSRC                            0x6101c
  78 #define G45_PIPEACONF           0x70008
  79 #define G45_PIPEBCONF       0x71008
  80
  81 #define G45_PIPECONF_ENABLE             0x80000000
  82 #define G45_PIPECONF_ENABLED            0x40000000
  83 #define G45_PIPECONF_DELAY_00           0
  84 #define G45_PIPECONF_DELAY_01           0x08000000
  85 #define G45_PIPECONF_DELAY_02           0x10000000
  86 #define G45_PIPECONF_DELAY_03           0x18000000
  87 #define G45_PIPECONF_FORCE_BORDER       0x02000000
  88 #define G45_PIPECONF_10BIT_GAMMA        0x01000000
  89 #define G45_PIPECONF_INTERLACE          0x00800000
  90
  91 #define G45_VGACNTRL            0x71400
  92 #define G45_VGACNTRL_VGA_DISABLE        0x80000000
  93
  94 #define G45_DPLLA_CTRL          0x6014
  95 #define G45_DPLLB_CTRL          0x6018
  96
  97 #define G45_DPLL_VCO_ENABLE             0x80000000
  98 #define G45_DPLL_DVO_HIGH_SPEED 0x40000000
  99 #define G45_DPLL_VGA_MODE_DISABLE       0x10000000
 100 #define G45_DPLL_MODE_LVDS                      0x08000000
 101 #define G45_DPLL_MODE_DAC_SERIAL        0x04000000
 102 #define G45_DPLL_DAC_SERIAL_P2_DIV_5    0x01000000
 103 #define G45_DPLL_DAC_SERIAL_P2_DIV_10   0x00000000
 104 #define G45_DPLL_LVDS_P2_DIV_7          0x01000000
 105 #define G45_DPLL_LVDS_P2_DIV_14 0x00000000
 106 #define G45_DPLL_P1_MASK                        0x00ff0000
 107 #define G45_DPLL_P1_SHIFT                       16
 108 #define G45_DPLL_PHASE_MASK             0x00001e00
 109 #define G45_DPLL_PHASE_SHIFT            9
 110
 111 #define G45_FPA0                                        0x6040
 112 #define G45_FPA1                                        0x6044
 113 #define G45_FPB0                                        0x6048
 114 #define G45_FPB1                                        0x604c
 115
 116 #define G45_DSPACNTR                            0x70180
 117 #define G45_DSPBCNTR                            0x71180
 118
 119 #define G45_DSPASIZE            0x70190
 120 #define G45_DSPBSIZE            0x71190
 121
 122 #define G45_DSPCNTR_SEL_PIPE_B          (1<<24)
 123 #define G45_DSPCNTR_PLANE_ENABLE        0x80000000
 124 #define G45_DSPCNTR_GAMMA_ENABLE        0x40000000
 125 #define G45_DSPCNTR_PIXEL_MASK          (0xf << 26)
 126 #define G45_DSPCNTR_8BPP                        (0x2 << 26)
 127 #define G45_DSPCNTR_15BPP                       (0x4 << 26)
 128 #define G45_DSPCNTR_16BPP                       (0x5 << 26)
 129 #define G45_DSPCNTR_32BPP                       (0x6 << 26)
 130
 131 #define G45_DSPALINOFF                          0x70184
 132 #define G45_DSPABASE G45_DSPALINOFF
 133 #define G45_DSPASTRIDE                          0x70188
 134 #define G45_DSPASURF                            0x7019c
 135
 136 #define G45_DSPBLINOFF                          0x71184
 137 #define G45_DSPBBASE G45_DSPBLINOFF
 138 #define G45_DSPBSTRIDE                          0x71188
 139 #define G45_DSPBSURF                            0x7119C
 140
 141 #define G45_HTOTAL_A                            0x60000
 142 #define G45_HBLANK_A                            0x60004
 143 #define G45_HSYNC_A                             0x60008
 144 #define G45_VTOTAL_A                            0x6000c
 145 #define G45_VBLANK_A                            0x60010
 146 #define G45_VSYNC_A                             0x60014
 147
 148 #define G45_HTOTAL_B    0x61000
 149 #define G45_HBLANK_B    0x61004
 150 #define G45_HSYNC_B     0x61008
 151 #define G45_VTOTAL_B    0x6100c
 152 #define G45_VBLANK_B    0x61010
 153 #define G45_VSYNC_B     0x61014
 154
 155
 156 #define G45_PIPEASRC                            0x6001c
 157 #define PIPEBCONF 0x71008
 158 #define G45_ADPA                                        0x61100
 159 #define G45_ADPA_MASK                           0x3fff43e7
 160 #define G45_ADPA_ENABLE                 0x80000000
 161 #define G45_ADPA_PIPESEL                        0x40000000
 162 #define G45_ADPA_VGA_SYNC                       0x00008000
 163 #define G45_ADPA_DPMS_ON                        0x00000000
 164 #define G45_ADPA_DPMS_OFF                       0x00000c00
 165 #define G45_ADPA_DPMS_MASK                      0x00000c00
 166 #define G45_ADPA_DPMS_STANDBY           0x00000800
 167 #define G45_ADPA_DPMS_SUSPEND           0x00000400
 168 #define G45_ADPA_VSYNC_PLUS             0x00000010
 169 #define G45_ADPA_HSYNC_PLUS             0x00000008
 170
 171 #define G45_LVDS                                        0x61180
 172 #define G45_LVDS_PORT_EN                        (1 << 31)
 173 #define G45_LVDS_PIPEB_SELECT           (1 << 30) /* Selects pipe B for LVDS data.  Must be set on pre-965. */
 174
 175 #define G45_PFIT_CONTROL                        0x61230
 176 #define G45_PFIT_ENABLE                         (1 << 31)
 177 #define G45_PFIT_PGM_RATIOS                     0x61234
 178
 179 #define G45_CURACNTR                            0x70080
 180 #define G45_CURBCNTR                            0x700C0
 181 #define G45_CURCNTR_PIPE_A                      0x00000000
 182 #define G45_CURCNTR_PIPE_B                      0x10000000
 183 #define G45_CURCNTR_PIPE_C                      0x20000000
 184 #define G45_CURCNTR_PIPE_D                      0x30000000
 185 #define G45_CURCNTR_PIPE_MASK           0x30000000
 186 #define G45_CURCNTR_POPUP_ENABLE        0x08000000
 187 #define G45_CURCNTR_GAMMA_ENABLE        0x04000000
 188 #define G45_CURCNTR_ROTATE_180          0x00008000
 189 #define G45_CURCNTR_TYPE_MASK           0x00000027
 190 #define G45_CURCNTR_TYPE_OFF            0x00000000
 191 #define G45_CURCNTR_TYPE_ARGB           0x00000027              /* The only one used by AROS. 64x64 ARGB */
 192
 193 #define G45_CURABASE                            0x70084         /* Base address of cursor (4K aligned) and trigger for update operations */
 194 #define G45_CURBBASE                            0x700C4
 195 #define G45_CURAPOS                             0x70088                 /* Cursor position */
 196 #define G45_CURBPOS                             0x700C8
 197
 198 #define G45_CURPOS_XSHIFT                       0
 199 #define G45_CURPOS_YSHIFT                       16
 200 #define G45_CURPOS_SIGN                 0x8000
 201
 202 #define   MI_READ_FLUSH         (1 << 0)
 203 #define   MI_EXE_FLUSH          (1 << 1)
 204 #define   MI_NO_WRITE_FLUSH     (1 << 2)
 205
 206 #define PIPE_A 0
 207 #define PIPE_B 1
 208
 209 #define readl(addr) ( *(volatile uint32_t *) (addr) )
 210 #define readw(addr) ( *(volatile uint16_t *) (addr) )
 211 #define readb(addr) ( *(volatile uint8_t *)  (addr) )
 212
 213 #define writeb(b,addr) do { (*(volatile uint8_t *)  (addr)) = (b); } while (0)
 214 #define writew(b,addr) do { (*(volatile uint16_t *) (addr)) = (b); } while (0)
 215 #define writel(b,addr) do { (*(volatile uint32_t *) (addr)) = (b); } while (0)
 216
 217 #define OUT_RING(n) do { \
 218         writel((n), &sd->RingBufferPhys[sd->RingBufferTail]); \
 219         sd->RingBufferTail += 4; \
 220         sd->RingBufferTail %= sd->RingBufferSize; \
 221 } while(0)
 222
 223 #define START_RING(n) do { \
 224         uint32_t head, tail, space; \
 225         do { \
 226                 head = readl(sd->Card.MMIO + G45_RING_HEAD) & G45_RING_HEAD_MASK; \
 227                 tail = sd->RingBufferTail; \
 228                 if (tail >= head) \
 229                         space = sd->RingBufferSize - (tail - head); \
 230                 else \
 231                         space = head - tail; \
 232                 if (space > 256) space-= 256; \
 233                 else space = 0; \
 234         } while(space < (n)*4); \
 235 } while(0)
 236
 237 #define ADVANCE_RING() do { sd->RingActive = 1; writel(sd->RingBufferTail, sd->Card.MMIO + G45_RING_TAIL); } while(0)
 238
 239 #define WAIT_IDLE() if (sd->RingActive) do { \
 240         uint32_t head, tail; \
 241         do { \
 242                 head = readl(sd->Card.MMIO + G45_RING_HEAD) & G45_RING_HEAD_MASK; \
 243                 tail = readl(sd->Card.MMIO + G45_RING_TAIL) & G45_RING_TAIL_MASK; \
 244         } while(head != tail); sd->RingActive = 0; \
 245 } while(0)
 246
 247 struct __ROP {
 248     int rop;
 249     int pattern;
 250 };
 251
 252 extern struct __ROP ROP_table[];
 253
 254 #define ROP3_ZERO             0x00000000
 255 #define ROP3_DSa              0x00880000
 256 #define ROP3_SDna             0x00440000
 257 #define ROP3_S                0x00cc0000
 258 #define ROP3_DSna             0x00220000
 259 #define ROP3_D                0x00aa0000
 260 #define ROP3_DSx              0x00660000
 261 #define ROP3_DSo              0x00ee0000
 262 #define ROP3_DSon             0x00110000
 263 #define ROP3_DSxn             0x00990000
 264 #define ROP3_Dn               0x00550000
 265 #define ROP3_SDno             0x00dd0000
 266 #define ROP3_Sn               0x00330000
 267 #define ROP3_DSno             0x00bb0000
 268 #define ROP3_DSan             0x00770000
 269 #define ROP3_ONE              0x00ff0000
 270 #define ROP3_DPa              0x00a00000
 271 #define ROP3_PDna             0x00500000
 272 #define ROP3_P                0x00f00000
 273 #define ROP3_DPna             0x000a0000
 274 #define ROP3_D                0x00aa0000
 275 #define ROP3_DPx              0x005a0000
 276 #define ROP3_DPo              0x00fa0000
 277 #define ROP3_DPon             0x00050000
 278 #define ROP3_PDxn             0x00a50000
 279 #define ROP3_PDno             0x00f50000
 280 #define ROP3_Pn               0x000f0000
 281 #define ROP3_DPno             0x00af0000
 282 #define ROP3_DPan             0x005f0000
 283  //  | (1 << 4) | (1 << 0)
 284 #define DO_FLUSH() do { if (sd->RingActive) { START_RING(2); OUT_RING((4 << 23)); OUT_RING(0); ADVANCE_RING(); WAIT_IDLE(); } } while(0)
 285
 286 #endif /* INTELG45_REGS_H_ */