workbench/devs/networks/atheros5000/hal/ah_desc.h

   1 /*
   2  * Copyright (c) 2002-2008 Sam Leffler, Errno Consulting
   3  * Copyright (c) 2002-2008 Atheros Communications, Inc.
   4  *
   5  * Permission to use, copy, modify, and/or distribute this software for any
   6  * purpose with or without fee is hereby granted, provided that the above
   7  * copyright notice and this permission notice appear in all copies.
   8  *
   9  * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
  10  * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
  11  * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
  12  * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
  13  * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
  14  * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF
  15  * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
  16  *
  17  * $Id$
  18  */
  19
  20 #ifndef _DEV_ATH_DESC_H
  21 #define _DEV_ATH_DESC_H
  22
  23 #include "opt_ah.h"             /* NB: required for AH_SUPPORT_AR5416 */
  24
  25 /*
  26  * Transmit descriptor status.  This structure is filled
  27  * in only after the tx descriptor process method finds a
  28  * ``done'' descriptor; at which point it returns something
  29  * other than HAL_EINPROGRESS.
  30  *
  31  * Note that ts_antenna may not be valid for all h/w.  It
  32  * should be used only if non-zero.
  33  */
  34 struct ath_tx_status {
  35         uint16_t        ts_seqnum;      /* h/w assigned sequence number */
  36         uint16_t        ts_tstamp;      /* h/w assigned timestamp */
  37         uint8_t         ts_status;      /* frame status, 0 => xmit ok */
  38         uint8_t         ts_rate;        /* h/w transmit rate index */
  39 #define HAL_TXSTAT_ALTRATE      0x80    /* alternate xmit rate used */
  40         int8_t          ts_rssi;        /* tx ack RSSI */
  41         uint8_t         ts_shortretry;  /* # short retries */
  42         uint8_t         ts_longretry;   /* # long retries */
  43         uint8_t         ts_virtcol;     /* virtual collision count */
  44         uint8_t         ts_antenna;     /* antenna information */
  45         uint8_t         ts_finaltsi;    /* final transmit series index */
  46 #ifdef AH_SUPPORT_AR5416
  47                                         /* 802.11n status */
  48         uint8_t         ts_flags;       /* misc flags */
  49         int8_t          ts_rssi_ctl[3]; /* tx ack RSSI [ctl, chain 0-2] */
  50         int8_t          ts_rssi_ext[3]; /* tx ack RSSI [ext, chain 0-2] */
  51 /* #define ts_rssi ts_rssi_combined */
  52         uint32_t        ts_ba_low;      /* blockack bitmap low */
  53         uint32_t        ts_ba_high;     /* blockack bitmap high */
  54         uint32_t        ts_evm0;        /* evm bytes */
  55         uint32_t        ts_evm1;
  56         uint32_t        ts_evm2;
  57 #endif /* AH_SUPPORT_AR5416 */
  58 };
  59
  60 /* bits found in ts_status */
  61 #define HAL_TXERR_XRETRY        0x01    /* excessive retries */
  62 #define HAL_TXERR_FILT          0x02    /* blocked by tx filtering */
  63 #define HAL_TXERR_FIFO          0x04    /* fifo underrun */
  64 #define HAL_TXERR_XTXOP         0x08    /* txop exceeded */
  65 #define HAL_TXERR_TIMER_EXPIRED 0x10    /* Tx timer expired */
  66
  67 /* bits found in ts_flags */
  68 #define HAL_TX_BA               0x01    /* Block Ack seen */
  69 #define HAL_TX_AGGR             0x02    /* Aggregate */
  70 #define HAL_TX_DESC_CFG_ERR     0x10    /* Error in 20/40 desc config */
  71 #define HAL_TX_DATA_UNDERRUN    0x20    /* Tx buffer underrun */
  72 #define HAL_TX_DELIM_UNDERRUN   0x40    /* Tx delimiter underrun */
  73
  74 /*
  75  * Receive descriptor status.  This structure is filled
  76  * in only after the rx descriptor process method finds a
  77  * ``done'' descriptor; at which point it returns something
  78  * other than HAL_EINPROGRESS.
  79  *
  80  * If rx_status is zero, then the frame was received ok;
  81  * otherwise the error information is indicated and rs_phyerr
  82  * contains a phy error code if HAL_RXERR_PHY is set.  In general
  83  * the frame contents is undefined when an error occurred thought
  84  * for some errors (e.g. a decryption error), it may be meaningful.
  85  *
  86  * Note that the receive timestamp is expanded using the TSF to
  87  * at least 15 bits (regardless of what the h/w provides directly).
  88  * Newer hardware supports a full 32-bits; use HAL_CAP_32TSTAMP to
  89  * find out if the hardware is capable.
  90  *
  91  * rx_rssi is in units of dbm above the noise floor.  This value
  92  * is measured during the preamble and PLCP; i.e. with the initial
  93  * 4us of detection.  The noise floor is typically a consistent
  94  * -96dBm absolute power in a 20MHz channel.
  95  */
  96 struct ath_rx_status {
  97         uint16_t        rs_datalen;     /* rx frame length */
  98         uint8_t         rs_status;      /* rx status, 0 => recv ok */
  99         uint8_t         rs_phyerr;      /* phy error code */
 100         int8_t          rs_rssi;        /* rx frame RSSI (combined for 11n) */
 101         uint8_t         rs_keyix;       /* key cache index */
 102         uint8_t         rs_rate;        /* h/w receive rate index */
 103         uint8_t         rs_more;        /* more descriptors follow */
 104         uint32_t        rs_tstamp;      /* h/w assigned timestamp */
 105         uint32_t        rs_antenna;     /* antenna information */
 106 #ifdef AH_SUPPORT_AR5416
 107                                         /* 802.11n status */
 108         int8_t          rs_rssi_ctl[3]; /* rx frame RSSI [ctl, chain 0-2] */
 109         int8_t          rs_rssi_ext[3]; /* rx frame RSSI [ext, chain 0-2] */
 110         uint8_t         rs_isaggr;      /* is part of the aggregate */
 111         uint8_t         rs_moreaggr;    /* more frames in aggr to follow */
 112         uint8_t         rs_num_delims;  /* number of delims in aggr */
 113         uint8_t         rs_flags;       /* misc flags */
 114         uint32_t        rs_evm0;        /* evm bytes */
 115         uint32_t        rs_evm1;
 116         uint32_t        rs_evm2;
 117 #endif /* AH_SUPPORT_AR5416 */
 118 };
 119
 120 /* bits found in rs_status */
 121 #define HAL_RXERR_CRC           0x01    /* CRC error on frame */
 122 #define HAL_RXERR_PHY           0x02    /* PHY error, rs_phyerr is valid */
 123 #define HAL_RXERR_FIFO          0x04    /* fifo overrun */
 124 #define HAL_RXERR_DECRYPT       0x08    /* non-Michael decrypt error */
 125 #define HAL_RXERR_MIC           0x10    /* Michael MIC decrypt error */
 126
 127 /* bits found in rs_flags */
 128 #define HAL_RX_MORE             0x01    /* more descriptors follow */
 129 #define HAL_RX_MORE_AGGR        0x02    /* more frames in aggr */
 130 #define HAL_RX_GI               0x04    /* full gi */
 131 #define HAL_RX_2040             0x08    /* 40 Mhz */
 132 #define HAL_RX_DELIM_CRC_PRE    0x10    /* crc error in delimiter pre */
 133 #define HAL_RX_DELIM_CRC_POST   0x20    /* crc error in delim after */
 134 #define HAL_RX_DECRYPT_BUSY     0x40    /* decrypt was too slow */
 135 #define HAL_RX_HI_RX_CHAIN      0x80    /* SM power save: hi Rx chain control */
 136
 137 enum {
 138         HAL_PHYERR_UNDERRUN             = 0,    /* Transmit underrun */
 139         HAL_PHYERR_TIMING               = 1,    /* Timing error */
 140         HAL_PHYERR_PARITY               = 2,    /* Illegal parity */
 141         HAL_PHYERR_RATE                 = 3,    /* Illegal rate */
 142         HAL_PHYERR_LENGTH               = 4,    /* Illegal length */
 143         HAL_PHYERR_RADAR                = 5,    /* Radar detect */
 144         HAL_PHYERR_SERVICE              = 6,    /* Illegal service */
 145         HAL_PHYERR_TOR                  = 7,    /* Transmit override receive */
 146         /* NB: these are specific to the 5212 */
 147         HAL_PHYERR_OFDM_TIMING          = 17,   /* */
 148         HAL_PHYERR_OFDM_SIGNAL_PARITY   = 18,   /* */
 149         HAL_PHYERR_OFDM_RATE_ILLEGAL    = 19,   /* */
 150         HAL_PHYERR_OFDM_LENGTH_ILLEGAL  = 20,   /* */
 151         HAL_PHYERR_OFDM_POWER_DROP      = 21,   /* */
 152         HAL_PHYERR_OFDM_SERVICE         = 22,   /* */
 153         HAL_PHYERR_OFDM_RESTART         = 23,   /* */
 154         HAL_PHYERR_CCK_TIMING           = 25,   /* */
 155         HAL_PHYERR_CCK_HEADER_CRC       = 26,   /* */
 156         HAL_PHYERR_CCK_RATE_ILLEGAL     = 27,   /* */
 157         HAL_PHYERR_CCK_SERVICE          = 30,   /* */
 158         HAL_PHYERR_CCK_RESTART          = 31,   /* */
 159 };
 160
 161 /* value found in rs_keyix to mark invalid entries */
 162 #define HAL_RXKEYIX_INVALID     ((uint8_t) -1)
 163 /* value used to specify no encryption key for xmit */
 164 #define HAL_TXKEYIX_INVALID     ((u_int) -1)
 165
 166 /* XXX rs_antenna definitions */
 167
 168 /*
 169  * Definitions for the software frame/packet descriptors used by
 170  * the Atheros HAL. Drivers are expected to fillin the
 171  * portions of a descriptor that are not opaque then use HAL calls
 172  * to complete the work.  Status for completed frames is returned
 173  * in a device-independent format.
 174  */
 175 #ifdef AH_SUPPORT_AR5416
 176 #define HAL_DESC_HW_SIZE        20
 177 #else
 178 #define HAL_DESC_HW_SIZE        4
 179 #endif /* AH_SUPPORT_AR5416 */
 180
 181 struct ath_desc {
 182         /*
 183          * The following definitions are passed directly
 184          * the hardware and managed by the HAL.  Drivers
 185          * should not touch those elements marked opaque.
 186          */
 187         uint32_t        ds_link;        /* phys address of next descriptor */
 188         uint32_t        ds_data;        /* phys address of data buffer */
 189         uint32_t        ds_ctl0;        /* opaque DMA control 0 */
 190         uint32_t        ds_ctl1;        /* opaque DMA control 1 */
 191         uint32_t        ds_hw[HAL_DESC_HW_SIZE];        /* opaque h/w region */
 192 };
 193
 194 struct ath_desc_status {
 195         union {
 196                 struct ath_tx_status tx;/* xmit status */
 197                 struct ath_rx_status rx;/* recv status */
 198         } ds_us;
 199 };
 200
 201 #define ds_txstat       ds_us.tx
 202 #define ds_rxstat       ds_us.rx
 203
 204 /* flags passed to tx descriptor setup methods */
 205 #define HAL_TXDESC_CLRDMASK     0x0001  /* clear destination filter mask */
 206 #define HAL_TXDESC_NOACK        0x0002  /* don't wait for ACK */
 207 #define HAL_TXDESC_RTSENA       0x0004  /* enable RTS */
 208 #define HAL_TXDESC_CTSENA       0x0008  /* enable CTS */
 209 #define HAL_TXDESC_INTREQ       0x0010  /* enable per-descriptor interrupt */
 210 #define HAL_TXDESC_VEOL         0x0020  /* mark virtual EOL */
 211 /* NB: this only affects frame, not any RTS/CTS */
 212 #define HAL_TXDESC_DURENA       0x0040  /* enable h/w write of duration field */
 213 #define HAL_TXDESC_EXT_ONLY     0x0080  /* send on ext channel only (11n) */
 214 #define HAL_TXDESC_EXT_AND_CTL  0x0100  /* send on ext + ctl channels (11n) */
 215 #define HAL_TXDESC_VMF          0x0200  /* virtual more frag */
 216
 217 /* flags passed to rx descriptor setup methods */
 218 #define HAL_RXDESC_INTREQ       0x0020  /* enable per-descriptor interrupt */
 219 #endif /* _DEV_ATH_DESC_H */