workbench/devs/networks/atheros5000/hal/amigaos/ah_osdep.h

   1 /*
   2  * Copyright (c) 2002-2008 Sam Leffler, Errno Consulting
   3  * Copyright (c) 2002-2008 Atheros Communications, Inc.
   4  * Copyright (c) 2010-2011 Neil Cafferkey
   5  *
   6  * Permission to use, copy, modify, and/or distribute this software for any
   7  * purpose with or without fee is hereby granted, provided that the above
   8  * copyright notice and this permission notice appear in all copies.
   9  *
  10  * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
  11  * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
  12  * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
  13  * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
  14  * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
  15  * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF
  16  * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
  17  *
  18  * $Id$
  19  */
  20 #ifndef _ATH_AH_OSDEP_H_
  21 #define _ATH_AH_OSDEP_H_
  22 /*
  23  * Atheros Hardware Access Layer (HAL) OS Dependent Definitions.
  24  */
  25
  26 #include <exec/types.h>
  27
  28 #define __ahdecl
  29 #ifndef __packed
  30 #define __packed        __attribute__((__packed__))
  31 #endif
  32
  33 /* NB: arm defaults to unsigned so be explicit */
  34 typedef BYTE int8_t;
  35 typedef WORD int16_t;
  36 typedef LONG int32_t;
  37 typedef QUAD int64_t;
  38
  39 typedef UBYTE uint8_t;
  40 typedef UWORD uint16_t;
  41 typedef ULONG uint32_t;
  42 typedef unsigned long long uint64_t;
  43
  44 typedef unsigned int size_t;
  45 typedef unsigned int u_int;
  46 #ifndef _VA_LIST_
  47 typedef void *va_list;
  48 #endif
  49
  50 /*
  51  * Linux/BSD gcc compatibility shims.
  52  */
  53 #define __printflike(_a,_b) \
  54         __attribute__ ((__format__ (__printf__, _a, _b)))
  55 #define __va_list       va_list
  56 #define OS_INLINE       __inline
  57
  58 /*
  59  * Delay n microseconds.
  60  */
  61 extern  void __ahdecl ath_hal_delay(int);
  62 #define OS_DELAY(_n)    ath_hal_delay(_n)
  63
  64 #define OS_MEMZERO(_a, _n)      ath_hal_memzero((_a), (_n))
  65 extern void __ahdecl ath_hal_memzero(void *, size_t);
  66 #define OS_MEMCPY(_d, _s, _n)   ath_hal_memcpy(_d,_s,_n)
  67 extern void * __ahdecl ath_hal_memcpy(void *, const void *, size_t);
  68
  69 #ifndef abs
  70 #define abs(_a)         __builtin_abs(_a)
  71 #endif
  72
  73 struct ath_hal;
  74 extern  uint32_t __ahdecl ath_hal_getuptime(struct ath_hal *);
  75 #define OS_GETUPTIME(_ah)       ath_hal_getuptime(_ah)
  76
  77 /*
  78  * Byte order/swapping support.
  79  */
  80 #define AH_LITTLE_ENDIAN        1234
  81 #define AH_BIG_ENDIAN           4321
  82
  83 #ifndef AH_BYTE_ORDER
  84 /*
  85  * When the .inc file is not available (e.g. when building
  86  * in a kernel source tree); look for some other way to
  87  * setup the host byte order.
  88  */
  89 #if defined(__AROS__) && !defined(AROS_BIG_ENDIAN)
  90 #define AH_BYTE_ORDER   AH_LITTLE_ENDIAN
  91 #else
  92 #define AH_BYTE_ORDER   AH_BIG_ENDIAN
  93 #endif
  94 #endif /* AH_BYTE_ORDER */
  95
  96 #if AH_BYTE_ORDER == AH_BIG_ENDIAN
  97 #ifdef __MORPHOS__
  98 #include <hardware/byteswap.h>
  99 #define __bswap32       SWAPLONG
 100 #else
 101 /*
 102  * This could be optimized but since we only use it for
 103  * a few registers there's little reason to do so.
 104  */
 105 static __inline__ uint32_t
 106 __bswap32(uint32_t _x)
 107 {
 108         return ((uint32_t)(
 109               (((const uint8_t *)(&_x))[0]    ) |
 110               (((const uint8_t *)(&_x))[1]<< 8) |
 111               (((const uint8_t *)(&_x))[2]<<16) |
 112               (((const uint8_t *)(&_x))[3]<<24))
 113         );
 114 }
 115 #endif
 116 #else
 117 #define __bswap32(_x)   (_x)
 118 #endif
 119
 120 #ifdef __MORPHOS__
 121 #define SYNCIO  __asm("eieio");\
 122                 __asm("sync");
 123 #else
 124 #define SYNCIO
 125 #endif
 126
 127 /*
 128  * Register read/write; we assume the registers will always
 129  * be memory-mapped.  Note that register accesses are done
 130  * using target-specific functions when debugging is enabled
 131  * (AH_DEBUG) or we are explicitly configured this way.  The
 132  * latter is used on some platforms where the full i/o space
 133  * cannot be directly mapped.
 134  *
 135  * The hardware registers are native little-endian byte order.
 136  * Big-endian hosts are handled by enabling hardware byte-swap
 137  * of register reads and writes at reset.  But the PCI clock
 138  * domain registers are not byte swapped!  Thus, on big-endian
 139  * platforms we have to byte-swap those registers specifically.
 140  * Most of this code is collapsed at compile time because the
 141  * register values are constants.
 142  */
 143 #if AH_BYTE_ORDER == AH_BIG_ENDIAN
 144 #define OS_REG_UNSWAPPED(_reg) \
 145         (((_reg) >= 0x4000 && (_reg) < 0x5000) || \
 146          ((_reg) >= 0x7000 && (_reg) < 0x8000))
 147 #define _OS_REG_WRITE(_ah, _reg, _val) do {                                 \
 148         if (OS_REG_UNSWAPPED(_reg))                                         \
 149                 *((volatile uint32_t *)((_ah)->ah_sh + (_reg))) =           \
 150                         __bswap32((_val));                                  \
 151         else                                                                \
 152                 *((volatile uint32_t *)((_ah)->ah_sh + (_reg))) = (_val);  \
 153         SYNCIO; \
 154 } while (0)
 155 #define _OS_REG_READ(_ah, _reg) \
 156         (OS_REG_UNSWAPPED(_reg) ? \
 157                 __bswap32(*((volatile uint32_t *)((_ah)->ah_sh + (_reg)))) : \
 158                 *((volatile uint32_t *)((_ah)->ah_sh + (_reg))))
 159 #else /* AH_LITTLE_ENDIAN */
 160 #define OS_REG_UNSWAPPED(_reg)  (0)
 161 #define _OS_REG_WRITE(_ah, _reg, _val) do { \
 162         *((volatile uint32_t *)((_ah)->ah_sh + (_reg))) = (_val); \
 163 } while (0)
 164 #define _OS_REG_READ(_ah, _reg) \
 165         *((volatile uint32_t *)((_ah)->ah_sh + (_reg)))
 166 #endif /* AH_BYTE_ORDER */
 167
 168 #if 0 && defined(AH_DEBUG) || defined(AH_REGOPS_FUNC) || defined(AH_DEBUG_ALQ)
 169 /* use functions to do register operations */
 170 #define OS_REG_WRITE(_ah, _reg, _val)   ath_hal_reg_write(_ah, _reg, _val)
 171 #define OS_REG_READ(_ah, _reg)          ath_hal_reg_read(_ah, _reg)
 172
 173 extern  void __ahdecl ath_hal_reg_write(struct ath_hal *ah,
 174                 u_int reg, uint32_t val);
 175 extern  uint32_t __ahdecl ath_hal_reg_read(struct ath_hal *ah, u_int reg);
 176 #else
 177 /* inline register operations */
 178 #define OS_REG_WRITE(_ah, _reg, _val)   _OS_REG_WRITE(_ah, _reg, _val)
 179 #define OS_REG_READ(_ah, _reg)          _OS_REG_READ(_ah, _reg)
 180 #endif /* AH_DEBUG || AH_REGFUNC || AH_DEBUG_ALQ */
 181
 182 #ifdef AH_DEBUG_ALQ
 183 extern  void __ahdecl OS_MARK(struct ath_hal *, u_int id, uint32_t value);
 184 #else
 185 #define OS_MARK(_ah, _id, _v)
 186 #endif
 187
 188 #endif /* _ATH_AH_OSDEP_H_ */