workbench/devs/networks/atheros5000/hal/ar5210/ar5210_beacon.c

   1 /*
   2  * Copyright (c) 2002-2008 Sam Leffler, Errno Consulting
   3  * Copyright (c) 2002-2004 Atheros Communications, Inc.
   4  *
   5  * Permission to use, copy, modify, and/or distribute this software for any
   6  * purpose with or without fee is hereby granted, provided that the above
   7  * copyright notice and this permission notice appear in all copies.
   8  *
   9  * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
  10  * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
  11  * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
  12  * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
  13  * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
  14  * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF
  15  * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
  16  *
  17  * $Id$
  18  */
  19 #include "opt_ah.h"
  20
  21 #ifdef AH_SUPPORT_AR5210
  22
  23 #include "ah.h"
  24 #include "ah_internal.h"
  25 #include "ah_desc.h"
  26
  27 #include "ar5210/ar5210.h"
  28 #include "ar5210/ar5210reg.h"
  29 #include "ar5210/ar5210desc.h"
  30
  31 /*
  32  * Initialize all of the hardware registers used to send beacons.
  33  */
  34 void
  35 ar5210SetBeaconTimers(struct ath_hal *ah, const HAL_BEACON_TIMERS *bt)
  36 {
  37
  38         OS_REG_WRITE(ah, AR_TIMER0, bt->bt_nexttbtt);
  39         OS_REG_WRITE(ah, AR_TIMER1, bt->bt_nextdba);
  40         OS_REG_WRITE(ah, AR_TIMER2, bt->bt_nextswba);
  41         OS_REG_WRITE(ah, AR_TIMER3, bt->bt_nextatim);
  42         /*
  43          * Set the Beacon register after setting all timers.
  44          */
  45         OS_REG_WRITE(ah, AR_BEACON, bt->bt_intval);
  46 }
  47
  48 /*
  49  * Legacy api to Initialize all of the beacon registers.
  50  */
  51 void
  52 ar5210BeaconInit(struct ath_hal *ah,
  53         uint32_t next_beacon, uint32_t beacon_period)
  54 {
  55         HAL_BEACON_TIMERS bt;
  56
  57         bt.bt_nexttbtt = next_beacon;
  58
  59         if (AH_PRIVATE(ah)->ah_opmode != HAL_M_STA) {
  60                 bt.bt_nextdba = (next_beacon -
  61                         ath_hal_dma_beacon_response_time) << 3; /* 1/8 TU */
  62                 bt.bt_nextswba = (next_beacon -
  63                         ath_hal_sw_beacon_response_time) << 3;  /* 1/8 TU */
  64                 /*
  65                  * The SWBA interrupt is not used for beacons in ad hoc mode
  66                  * as we don't yet support ATIMs. So since the beacon never
  67                  * changes, the beacon descriptor is set up once and read
  68                  * into a special HW buffer, from which it will be
  69                  * automagically retrieved at each DMA Beacon Alert (DBA).
  70                  */
  71
  72                 /* Set the ATIM window */
  73                 bt.bt_nextatim = next_beacon + 0;       /* NB: no ATIMs */
  74         } else {
  75                 bt.bt_nextdba = ~0;
  76                 bt.bt_nextswba = ~0;
  77                 bt.bt_nextatim = 1;
  78         }
  79         bt.bt_intval = beacon_period &
  80                 (AR_BEACON_PERIOD | AR_BEACON_RESET_TSF | AR_BEACON_EN);
  81         ar5210SetBeaconTimers(ah, &bt);
  82 }
  83
  84 void
  85 ar5210ResetStaBeaconTimers(struct ath_hal *ah)
  86 {
  87         uint32_t val;
  88
  89         OS_REG_WRITE(ah, AR_TIMER0, 0);         /* no beacons */
  90         val = OS_REG_READ(ah, AR_STA_ID1);
  91         val |= AR_STA_ID1_NO_PSPOLL;            /* XXX */
  92         /* tell the h/w that the associated AP is not PCF capable */
  93         OS_REG_WRITE(ah, AR_STA_ID1,
  94                 val & ~(AR_STA_ID1_DEFAULT_ANTENNA | AR_STA_ID1_PCF));
  95         OS_REG_WRITE(ah, AR_BEACON, AR_BEACON_PERIOD);
  96 }
  97
  98 /*
  99  * Set all the beacon related bits on the h/w for stations
 100  * i.e. initializes the corresponding h/w timers;
 101  * also tells the h/w whether to anticipate PCF beacons
 102  *
 103  * dtim_count and cfp_count from the current beacon - their current
 104  * values aren't necessarily maintained in the device struct
 105  */
 106 void
 107 ar5210SetStaBeaconTimers(struct ath_hal *ah, const HAL_BEACON_STATE *bs)
 108 {
 109         struct ath_hal_5210 *ahp = AH5210(ah);
 110
 111         HALDEBUG(ah, HAL_DEBUG_BEACON, "%s: setting beacon timers\n", __func__);
 112
 113         HALASSERT(bs->bs_intval != 0);
 114         /* if the AP will do PCF */
 115         if (bs->bs_cfpmaxduration != 0) {
 116                 /* tell the h/w that the associated AP is PCF capable */
 117                 OS_REG_WRITE(ah, AR_STA_ID1,
 118                         (OS_REG_READ(ah, AR_STA_ID1) &~ AR_STA_ID1_DEFAULT_ANTENNA)
 119                         | AR_STA_ID1_PCF);
 120
 121                 /* set CFP_PERIOD(1.024ms) register */
 122                 OS_REG_WRITE(ah, AR_CFP_PERIOD, bs->bs_cfpperiod);
 123
 124                 /* set CFP_DUR(1.024ms) register to max cfp duration */
 125                 OS_REG_WRITE(ah, AR_CFP_DUR, bs->bs_cfpmaxduration);
 126
 127                 /* set TIMER2(128us) to anticipated time of next CFP */
 128                 OS_REG_WRITE(ah, AR_TIMER2, bs->bs_cfpnext << 3);
 129         } else {
 130                 /* tell the h/w that the associated AP is not PCF capable */
 131                 OS_REG_WRITE(ah, AR_STA_ID1,
 132                         OS_REG_READ(ah, AR_STA_ID1) &~ (AR_STA_ID1_DEFAULT_ANTENNA | AR_STA_ID1_PCF));
 133         }
 134
 135         /*
 136          * Set TIMER0(1.024ms) to the anticipated time of the next beacon.
 137          */
 138         OS_REG_WRITE(ah, AR_TIMER0, bs->bs_nexttbtt);
 139
 140         /*
 141          * Start the beacon timers by setting the BEACON register
 142          * to the beacon interval; also write the tim offset which
 143          * we should know by now.  The code, in ar5211WriteAssocid,
 144          * also sets the tim offset once the AID is known which can
 145          * be left as such for now.
 146          */
 147         OS_REG_WRITE(ah, AR_BEACON,
 148                 (OS_REG_READ(ah, AR_BEACON) &~ (AR_BEACON_PERIOD|AR_BEACON_TIM))
 149                 | SM(bs->bs_intval, AR_BEACON_PERIOD)
 150                 | SM(bs->bs_timoffset ? bs->bs_timoffset + 4 : 0, AR_BEACON_TIM)
 151         );
 152
 153         /*
 154          * Configure the BMISS interrupt.  Note that we
 155          * assume the caller blocks interrupts while enabling
 156          * the threshold.
 157          */
 158
 159         /*
 160          * Interrupt works only on Crete.
 161          */
 162         if (AH_PRIVATE(ah)->ah_macRev < AR_SREV_CRETE)
 163                 return;
 164         /*
 165          * Counter is only 3-bits.
 166          * Count of 0 with BMISS interrupt enabled will hang the system
 167          * with too many interrupts
 168          */
 169         if (AH_PRIVATE(ah)->ah_macRev >= AR_SREV_CRETE &&
 170             (bs->bs_bmissthreshold&7) == 0) {
 171 #ifdef AH_DEBUG
 172                 ath_hal_printf(ah, "%s: invalid beacon miss threshold %u\n",
 173                         __func__, bs->bs_bmissthreshold);
 174 #endif
 175                 return;
 176         }
 177 #define BMISS_MAX       (AR_RSSI_THR_BM_THR >> AR_RSSI_THR_BM_THR_S)
 178         /*
 179          * Configure the BMISS interrupt.  Note that we
 180          * assume the caller blocks interrupts while enabling
 181          * the threshold.
 182          *
 183          * NB: the beacon miss count field is only 3 bits which
 184          *     is much smaller than what's found on later parts;
 185          *     clamp overflow values as a safeguard.
 186          */
 187         ahp->ah_rssiThr = (ahp->ah_rssiThr &~ AR_RSSI_THR_BM_THR)
 188                         | SM(bs->bs_bmissthreshold > BMISS_MAX ?
 189                                 BMISS_MAX : bs->bs_bmissthreshold,
 190                              AR_RSSI_THR_BM_THR);
 191         OS_REG_WRITE(ah, AR_RSSI_THR, ahp->ah_rssiThr);
 192 #undef BMISS_MAX
 193 }
 194 #endif /* AH_SUPPORT_AR5210 */