workbench/devs/networks/atheros5000/hal/ar5210/ar5210_interrupts.c

   1 /*
   2  * Copyright (c) 2002-2008 Sam Leffler, Errno Consulting
   3  * Copyright (c) 2002-2004 Atheros Communications, Inc.
   4  *
   5  * Permission to use, copy, modify, and/or distribute this software for any
   6  * purpose with or without fee is hereby granted, provided that the above
   7  * copyright notice and this permission notice appear in all copies.
   8  *
   9  * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
  10  * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
  11  * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
  12  * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
  13  * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
  14  * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF
  15  * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
  16  *
  17  * $Id$
  18  */
  19 #include "opt_ah.h"
  20
  21 #ifdef AH_SUPPORT_AR5210
  22
  23 #include "ah.h"
  24 #include "ah_internal.h"
  25
  26 #include "ar5210/ar5210.h"
  27 #include "ar5210/ar5210reg.h"
  28
  29 /*
  30  * Return non-zero if an interrupt is pending.
  31  */
  32 HAL_BOOL
  33 ar5210IsInterruptPending(struct ath_hal *ah)
  34 {
  35         return (OS_REG_READ(ah, AR_INTPEND) ? AH_TRUE : AH_FALSE);
  36 }
  37
  38 /*
  39  * Read the Interrupt Status Register value and return
  40  * an abstracted bitmask of the data found in the ISR.
  41  * Note that reading the ISR clear pending interrupts.
  42  */
  43 HAL_BOOL
  44 ar5210GetPendingInterrupts(struct ath_hal *ah, HAL_INT *masked)
  45 {
  46 #define AR_FATAL_INT \
  47     (AR_ISR_MCABT_INT | AR_ISR_SSERR_INT | AR_ISR_DPERR_INT | AR_ISR_RXORN_INT)
  48         struct ath_hal_5210 *ahp = AH5210(ah);
  49         uint32_t isr;
  50
  51         isr = OS_REG_READ(ah, AR_ISR);
  52         if (isr == 0xffffffff) {
  53                 *masked = 0;
  54                 return AH_FALSE;
  55         }
  56
  57         /*
  58          * Mask interrupts that have no device-independent
  59          * representation; these are added back below.  We
  60          * also masked with the abstracted IMR to insure no
  61          * status bits leak through that weren't requested
  62          * (e.g. RXNOFRM) and that might confuse the caller.
  63          */
  64         *masked = (isr & HAL_INT_COMMON) & ahp->ah_maskReg;
  65
  66         if (isr & AR_FATAL_INT)
  67                 *masked |= HAL_INT_FATAL;
  68         if (isr & (AR_ISR_RXOK_INT | AR_ISR_RXERR_INT))
  69                 *masked |= HAL_INT_RX;
  70         if (isr & (AR_ISR_TXOK_INT | AR_ISR_TXDESC_INT | AR_ISR_TXERR_INT | AR_ISR_TXEOL_INT))
  71                 *masked |= HAL_INT_TX;
  72
  73         /*
  74          * On fatal errors collect ISR state for debugging.
  75          */
  76         if (*masked & HAL_INT_FATAL) {
  77                 AH_PRIVATE(ah)->ah_fatalState[0] = isr;
  78         }
  79
  80         return AH_TRUE;
  81 #undef AR_FATAL_INT
  82 }
  83
  84 HAL_INT
  85 ar5210GetInterrupts(struct ath_hal *ah)
  86 {
  87         return AH5210(ah)->ah_maskReg;
  88 }
  89
  90 HAL_INT
  91 ar5210SetInterrupts(struct ath_hal *ah, HAL_INT ints)
  92 {
  93         struct ath_hal_5210 *ahp = AH5210(ah);
  94         uint32_t omask = ahp->ah_maskReg;
  95         uint32_t mask;
  96
  97         HALDEBUG(ah, HAL_DEBUG_INTERRUPT, "%s: 0x%x => 0x%x\n",
  98             __func__, omask, ints);
  99
 100         /*
 101          * Disable interrupts here before reading & modifying
 102          * the mask so that the ISR does not modify the mask
 103          * out from under us.
 104          */
 105         if (omask & HAL_INT_GLOBAL) {
 106                 HALDEBUG(ah, HAL_DEBUG_INTERRUPT, "%s: disable IER\n", __func__);
 107                 OS_REG_WRITE(ah, AR_IER, AR_IER_DISABLE);
 108         }
 109
 110         mask = ints & HAL_INT_COMMON;
 111         if (ints & HAL_INT_RX)
 112                 mask |= AR_IMR_RXOK_INT | AR_IMR_RXERR_INT;
 113         if (ints & HAL_INT_TX) {
 114                 if (ahp->ah_txOkInterruptMask)
 115                         mask |= AR_IMR_TXOK_INT;
 116                 if (ahp->ah_txErrInterruptMask)
 117                         mask |= AR_IMR_TXERR_INT;
 118                 if (ahp->ah_txDescInterruptMask)
 119                         mask |= AR_IMR_TXDESC_INT;
 120                 if (ahp->ah_txEolInterruptMask)
 121                         mask |= AR_IMR_TXEOL_INT;
 122         }
 123
 124         /* Write the new IMR and store off our SW copy. */
 125         HALDEBUG(ah, HAL_DEBUG_INTERRUPT, "%s: new IMR 0x%x\n", __func__, mask);
 126         OS_REG_WRITE(ah, AR_IMR, mask);
 127         ahp->ah_maskReg = ints;
 128
 129         /* Re-enable interrupts as appropriate. */
 130         if (ints & HAL_INT_GLOBAL) {
 131                 HALDEBUG(ah, HAL_DEBUG_INTERRUPT, "%s: enable IER\n", __func__);
 132                 OS_REG_WRITE(ah, AR_IER, AR_IER_ENABLE);
 133         }
 134
 135         return omask;
 136 }
 137 #endif /* AH_SUPPORT_AR5210 */