workbench/devs/networks/atheros5000/hal/ar5210/ar5210desc.h

   1 /*
   2  * Copyright (c) 2002-2008 Sam Leffler, Errno Consulting
   3  * Copyright (c) 2002-2004 Atheros Communications, Inc.
   4  *
   5  * Permission to use, copy, modify, and/or distribute this software for any
   6  * purpose with or without fee is hereby granted, provided that the above
   7  * copyright notice and this permission notice appear in all copies.
   8  *
   9  * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
  10  * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
  11  * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
  12  * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
  13  * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
  14  * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF
  15  * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
  16  *
  17  * $Id$
  18  */
  19 #ifndef _DEV_ATH_AR5210DESC_H
  20 #define _DEV_ATH_AR5210DESC_H
  21
  22 #include "ah_desc.h"
  23
  24 /*
  25  * Defintions for the DMA descriptors used by the Atheros
  26  * AR5210/AR5211 and AR5110 Wireless Lan controller parts.
  27  */
  28
  29 /* DMA descriptors */
  30 struct ar5210_desc {
  31         uint32_t        ds_link;        /* link pointer */
  32         uint32_t        ds_data;        /* data buffer pointer */
  33         uint32_t        ds_ctl0;        /* DMA control 0 */
  34         uint32_t        ds_ctl1;        /* DMA control 1 */
  35         uint32_t        ds_status0;     /* DMA status 0 */
  36         uint32_t        ds_status1;     /* DMA status 1 */
  37 } __packed;
  38 #define AR5210DESC(_ds) ((struct ar5210_desc *)(_ds))
  39 #define AR5210DESC_CONST(_ds)   ((const struct ar5210_desc *)(_ds))
  40
  41 /* TX ds_ctl0 */
  42 #define AR_FrameLen             0x00000fff      /* frame length */
  43 #define AR_HdrLen               0x0003f000      /* header length */
  44 #define AR_HdrLen_S             12
  45 #define AR_XmitRate             0x003c0000      /* txrate */
  46 #define AR_XmitRate_S           18
  47 #define AR_Rate_6M              0xb
  48 #define AR_Rate_9M              0xf
  49 #define AR_Rate_12M             0xa
  50 #define AR_Rate_18M             0xe
  51 #define AR_Rate_24M             0x9
  52 #define AR_Rate_36M             0xd
  53 #define AR_Rate_48M             0x8
  54 #define AR_Rate_54M             0xc
  55 #define AR_RTSCTSEnable         0x00400000      /* RTS/CTS enable */
  56 #define AR_LongPkt              0x00800000      /* long packet indication */
  57 #define AR_ClearDestMask        0x01000000      /* Clear destination mask bit */
  58 #define AR_AntModeXmit          0x02000000      /* TX antenna seslection */
  59 #define AR_FrmType              0x1c000000      /* frame type indication */
  60 #define AR_Frm_Normal           0x00000000      /* normal frame */
  61 #define AR_Frm_ATIM             0x04000000      /* ATIM frame */
  62 #define AR_Frm_PSPOLL           0x08000000      /* PS poll frame */
  63 #define AR_Frm_NoDelay          0x0c000000      /* no delay data */
  64 #define AR_Frm_PIFS             0x10000000      /* PIFS data */
  65 #define AR_TxInterReq           0x20000000      /* TX interrupt request */
  66 #define AR_EncryptKeyValid      0x40000000      /* EncryptKeyIdx is valid */
  67
  68 /* TX ds_ctl1 */
  69 #define AR_BufLen               0x00000fff      /* data buffer length */
  70 #define AR_More                 0x00001000      /* more desc in this frame */
  71 #define AR_EncryptKeyIdx        0x0007e000      /* encrypt key table index */
  72 #define AR_EncryptKeyIdx_S      13
  73 #define AR_RTSDuration          0xfff80000      /* lower 13bit of duration */
  74
  75 /* RX ds_ctl1 */
  76 /*      AR_BufLen               0x00000fff         data buffer length */
  77 #define AR_RxInterReq           0x00002000      /* RX interrupt request */
  78
  79 /* TX ds_status0 */
  80 #define AR_FrmXmitOK            0x00000001      /* TX success */
  81 #define AR_ExcessiveRetries     0x00000002      /* excessive retries */
  82 #define AR_FIFOUnderrun         0x00000004      /* TX FIFO underrun */
  83 #define AR_Filtered             0x00000008      /* TX filter indication */
  84 /* NB: the spec has the Short+Long retry counts reversed */
  85 #define AR_LongRetryCnt         0x000000f0      /* long retry count */
  86 #define AR_LongRetryCnt_S       4
  87 #define AR_ShortRetryCnt        0x00000f00      /* short retry count */
  88 #define AR_ShortRetryCnt_S      8
  89 #define AR_SendTimestamp        0xffff0000      /* TX timestamp */
  90 #define AR_SendTimestamp_S      16
  91
  92 /* RX ds_status0 */
  93 #define AR_DataLen              0x00000fff      /* RX data length */
  94 /*      AR_More                 0x00001000         more desc in this frame */
  95 #define AR_RcvAntenna           0x00004000      /* received on ant 1 */
  96 #define AR_RcvRate              0x00078000      /* reception rate */
  97 #define AR_RcvRate_S            15
  98 #define AR_RcvSigStrength       0x07f80000      /* receive signal strength */
  99 #define AR_RcvSigStrength_S     19
 100
 101 /* TX ds_status1 */
 102 #define AR_Done                 0x00000001      /* descripter complete */
 103 #define AR_SeqNum               0x00001ffe      /* TX sequence number */
 104 #define AR_AckSigStrength       0x001fe000      /* strength of ACK */
 105 #define AR_AckSigStrength_S     13
 106
 107 /* RX ds_status1 */
 108 /*      AR_Done                 0x00000001         descripter complete */
 109 #define AR_FrmRcvOK             0x00000002      /* frame reception success */
 110 #define AR_CRCErr               0x00000004      /* CRC error */
 111 #define AR_FIFOOverrun          0x00000008      /* RX FIFO overrun */
 112 #define AR_DecryptCRCErr        0x00000010      /* Decryption CRC fiailure */
 113 #define AR_PHYErr               0x000000e0      /* PHY error */
 114 #define AR_PHYErr_S             5
 115 #define AR_PHYErr_NoErr         0x00000000      /* No error */
 116 #define AR_PHYErr_Tim           0x00000020      /* Timing error */
 117 #define AR_PHYErr_Par           0x00000040      /* Parity error */
 118 #define AR_PHYErr_Rate          0x00000060      /* Illegal rate */
 119 #define AR_PHYErr_Len           0x00000080      /* Illegal length */
 120 #define AR_PHYErr_QAM           0x000000a0      /* 64 QAM rate */
 121 #define AR_PHYErr_Srv           0x000000c0      /* Service bit error */
 122 #define AR_PHYErr_TOR           0x000000e0      /* Transmit override receive */
 123 #define AR_KeyIdxValid          0x00000100      /* decryption key index valid */
 124 #define AR_KeyIdx               0x00007e00      /* Decryption key index */
 125 #define AR_KeyIdx_S             9
 126 #define AR_RcvTimestamp         0x0fff8000      /* timestamp */
 127 #define AR_RcvTimestamp_S       15
 128 #define AR_KeyCacheMiss         0x10000000      /* key cache miss indication */
 129
 130 #endif /* _DEV_ATH_AR5210DESC_H_ */