workbench/devs/networks/atheros5000/hal/ar5211/ar5211_keycache.c

   1 /*
   2  * Copyright (c) 2002-2008 Sam Leffler, Errno Consulting
   3  * Copyright (c) 2002-2006 Atheros Communications, Inc.
   4  *
   5  * Permission to use, copy, modify, and/or distribute this software for any
   6  * purpose with or without fee is hereby granted, provided that the above
   7  * copyright notice and this permission notice appear in all copies.
   8  *
   9  * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
  10  * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
  11  * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
  12  * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
  13  * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
  14  * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF
  15  * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
  16  *
  17  * $Id$
  18  */
  19 #include "opt_ah.h"
  20
  21 #ifdef AH_SUPPORT_AR5211
  22
  23 #include "ah.h"
  24 #include "ah_internal.h"
  25
  26 #include "ar5211/ar5211.h"
  27 #include "ar5211/ar5211reg.h"
  28
  29 /*
  30  *  Chips-specific key cache routines.
  31  */
  32
  33 #define AR_KEYTABLE_SIZE        128
  34 #define KEY_XOR                 0xaa
  35
  36 /*
  37  * Return the size of the hardware key cache.
  38  */
  39 uint32_t
  40 ar5211GetKeyCacheSize(struct ath_hal *ah)
  41 {
  42         return AR_KEYTABLE_SIZE;
  43 }
  44
  45 /*
  46  * Return true if the specific key cache entry is valid.
  47  */
  48 HAL_BOOL
  49 ar5211IsKeyCacheEntryValid(struct ath_hal *ah, uint16_t entry)
  50 {
  51         if (entry < AR_KEYTABLE_SIZE) {
  52                 uint32_t val = OS_REG_READ(ah, AR_KEYTABLE_MAC1(entry));
  53                 if (val & AR_KEYTABLE_VALID)
  54                         return AH_TRUE;
  55         }
  56         return AH_FALSE;
  57 }
  58
  59 /*
  60  * Clear the specified key cache entry
  61  */
  62 HAL_BOOL
  63 ar5211ResetKeyCacheEntry(struct ath_hal *ah, uint16_t entry)
  64 {
  65         if (entry < AR_KEYTABLE_SIZE) {
  66                 OS_REG_WRITE(ah, AR_KEYTABLE_KEY0(entry), 0);
  67                 OS_REG_WRITE(ah, AR_KEYTABLE_KEY1(entry), 0);
  68                 OS_REG_WRITE(ah, AR_KEYTABLE_KEY2(entry), 0);
  69                 OS_REG_WRITE(ah, AR_KEYTABLE_KEY3(entry), 0);
  70                 OS_REG_WRITE(ah, AR_KEYTABLE_KEY4(entry), 0);
  71                 OS_REG_WRITE(ah, AR_KEYTABLE_TYPE(entry), 0);
  72                 OS_REG_WRITE(ah, AR_KEYTABLE_MAC0(entry), 0);
  73                 OS_REG_WRITE(ah, AR_KEYTABLE_MAC1(entry), 0);
  74                 return AH_TRUE;
  75         }
  76         return AH_FALSE;
  77 }
  78
  79 /*
  80  * Sets the mac part of the specified key cache entry and mark it valid.
  81  */
  82 HAL_BOOL
  83 ar5211SetKeyCacheEntryMac(struct ath_hal *ah, uint16_t entry, const uint8_t *mac)
  84 {
  85         uint32_t macHi, macLo;
  86
  87         if (entry >= AR_KEYTABLE_SIZE) {
  88                 HALDEBUG(ah, HAL_DEBUG_ANY, "%s: entry %u out of range\n",
  89                     __func__, entry);
  90                 return AH_FALSE;
  91         }
  92
  93         /*
  94          * Set MAC address -- shifted right by 1.  MacLo is
  95          * the 4 MSBs, and MacHi is the 2 LSBs.
  96          */
  97         if (mac != AH_NULL) {
  98                 macHi = (mac[5] << 8) | mac[4];
  99                 macLo = (mac[3] << 24)| (mac[2] << 16)
 100                       | (mac[1] << 8) | mac[0];
 101                 macLo >>= 1;
 102                 macLo |= (macHi & 1) << 31;     /* carry */
 103                 macHi >>= 1;
 104         } else {
 105                 macLo = macHi = 0;
 106         }
 107
 108         OS_REG_WRITE(ah, AR_KEYTABLE_MAC0(entry), macLo);
 109         OS_REG_WRITE(ah, AR_KEYTABLE_MAC1(entry), macHi | AR_KEYTABLE_VALID);
 110         return AH_TRUE;
 111 }
 112
 113 /*
 114  * Sets the contents of the specified key cache entry.
 115  */
 116 HAL_BOOL
 117 ar5211SetKeyCacheEntry(struct ath_hal *ah, uint16_t entry,
 118                        const HAL_KEYVAL *k, const uint8_t *mac,
 119                        int xorKey)
 120 {
 121         uint32_t key0, key1, key2, key3, key4;
 122         uint32_t keyType;
 123         uint32_t xorMask= xorKey ?
 124                 (KEY_XOR << 24 | KEY_XOR << 16 | KEY_XOR << 8 | KEY_XOR) : 0;
 125
 126         if (entry >= AR_KEYTABLE_SIZE) {
 127                 HALDEBUG(ah, HAL_DEBUG_ANY, "%s: entry %u out of range\n",
 128                     __func__, entry);
 129                 return AH_FALSE;
 130         }
 131         switch (k->kv_type) {
 132         case HAL_CIPHER_AES_OCB:
 133                 keyType = AR_KEYTABLE_TYPE_AES;
 134                 break;
 135         case HAL_CIPHER_WEP:
 136                 if (k->kv_len < 40 / NBBY) {
 137                         HALDEBUG(ah, HAL_DEBUG_ANY,
 138                             "%s: WEP key length %u too small\n",
 139                             __func__, k->kv_len);
 140                         return AH_FALSE;
 141                 }
 142                 if (k->kv_len <= 40 / NBBY)
 143                         keyType = AR_KEYTABLE_TYPE_40;
 144                 else if (k->kv_len <= 104 / NBBY)
 145                         keyType = AR_KEYTABLE_TYPE_104;
 146                 else
 147                         keyType = AR_KEYTABLE_TYPE_128;
 148                 break;
 149         case HAL_CIPHER_CLR:
 150                 keyType = AR_KEYTABLE_TYPE_CLR;
 151                 break;
 152         default:
 153                 HALDEBUG(ah, HAL_DEBUG_ANY, "%s: cipher %u not supported\n",
 154                         __func__, k->kv_type);
 155                 return AH_FALSE;
 156         }
 157
 158         key0 = LE_READ_4(k->kv_val+0) ^ xorMask;
 159         key1 = (LE_READ_2(k->kv_val+4) ^ xorMask) & 0xffff;
 160         key2 = LE_READ_4(k->kv_val+6) ^ xorMask;
 161         key3 = (LE_READ_2(k->kv_val+10) ^ xorMask) & 0xffff;
 162         key4 = LE_READ_4(k->kv_val+12) ^ xorMask;
 163         if (k->kv_len <= 104 / NBBY)
 164                 key4 &= 0xff;
 165
 166
 167         /*
 168          * Note: WEP key cache hardware requires that each double-word
 169          * pair be written in even/odd order (since the destination is
 170          * a 64-bit register).  Don't reorder these writes w/o
 171          * understanding this!
 172          */
 173         OS_REG_WRITE(ah, AR_KEYTABLE_KEY0(entry), key0);
 174         OS_REG_WRITE(ah, AR_KEYTABLE_KEY1(entry), key1);
 175         OS_REG_WRITE(ah, AR_KEYTABLE_KEY2(entry), key2);
 176         OS_REG_WRITE(ah, AR_KEYTABLE_KEY3(entry), key3);
 177         OS_REG_WRITE(ah, AR_KEYTABLE_KEY4(entry), key4);
 178         OS_REG_WRITE(ah, AR_KEYTABLE_TYPE(entry), keyType);
 179         return ar5211SetKeyCacheEntryMac(ah, entry, mac);
 180 }
 181 #endif /* AH_SUPPORT_AR5211 */