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revert between 56095 -> 55830 in arch
[AROS.git] / workbench / devs / networks / e1000 / e1000_82540.c
blob0561e125db4d7f968935d3030758026dd5b35008
1 /*******************************************************************************
2
3 Intel PRO/1000 Linux driver
4 Copyright(c) 1999 - 2010 Intel Corporation.
5
6 This program is free software; you can redistribute it and/or modify it
7 under the terms and conditions of the GNU General Public License,
8 version 2, as published by the Free Software Foundation.
9
10 This program is distributed in the hope it will be useful, but WITHOUT
11 ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
12 FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
13 more details.
14
15 You should have received a copy of the GNU General Public License along with
16 this program; if not, write to the Free Software Foundation, Inc.,
17 51 Franklin St - Fifth Floor, Boston, MA 02110-1301 USA.
18
19 The full GNU General Public License is included in this distribution in
20 the file called "COPYING".
21
22 Contact Information:
23 Linux NICS <linux.nics@intel.com>
24 e1000-devel Mailing List <e1000-devel@lists.sourceforge.net>
25 Intel Corporation, 5200 N.E. Elam Young Parkway, Hillsboro, OR 97124-6497
26
27 *******************************************************************************/
28
29 /*
30 * 82540EM Gigabit Ethernet Controller
31 * 82540EP Gigabit Ethernet Controller
32 * 82545EM Gigabit Ethernet Controller (Copper)
33 * 82545EM Gigabit Ethernet Controller (Fiber)
34 * 82545GM Gigabit Ethernet Controller
35 * 82546EB Gigabit Ethernet Controller (Copper)
36 * 82546EB Gigabit Ethernet Controller (Fiber)
37 * 82546GB Gigabit Ethernet Controller
38 */
39
40 #include "e1000_api.h"
41
42 static s32 e1000_init_phy_params_82540(struct e1000_hw *hw);
43 static s32 e1000_init_nvm_params_82540(struct e1000_hw *hw);
44 static s32 e1000_init_mac_params_82540(struct e1000_hw *hw);
45 static s32 e1000_adjust_serdes_amplitude_82540(struct e1000_hw *hw);
46 static void e1000_clear_hw_cntrs_82540(struct e1000_hw *hw);
47 static s32 e1000_init_hw_82540(struct e1000_hw *hw);
48 static s32 e1000_reset_hw_82540(struct e1000_hw *hw);
49 static s32 e1000_set_phy_mode_82540(struct e1000_hw *hw);
50 static s32 e1000_set_vco_speed_82540(struct e1000_hw *hw);
51 static s32 e1000_setup_copper_link_82540(struct e1000_hw *hw);
52 static s32 e1000_setup_fiber_serdes_link_82540(struct e1000_hw *hw);
53 static void e1000_power_down_phy_copper_82540(struct e1000_hw *hw);
54 static s32 e1000_read_mac_addr_82540(struct e1000_hw *hw);
55
56 /**
57 * e1000_init_phy_params_82540 - Init PHY func ptrs.
58 * @hw: pointer to the HW structure
59 **/
60 static s32 e1000_init_phy_params_82540(struct e1000_hw *hw)
61 {
62 struct e1000_phy_info *phy = &hw->phy;
63 s32 ret_val = E1000_SUCCESS;
64
65 phy->addr = 1;
66 phy->autoneg_mask = AUTONEG_ADVERTISE_SPEED_DEFAULT;
67 phy->reset_delay_us = 10000;
68 phy->type = e1000_phy_m88;
69
70 /* Function Pointers */
71 phy->ops.check_polarity = e1000_check_polarity_m88;
72 phy->ops.commit = e1000_phy_sw_reset_generic;
73 phy->ops.force_speed_duplex = e1000_phy_force_speed_duplex_m88;
74 phy->ops.get_cable_length = e1000_get_cable_length_m88;
75 phy->ops.get_cfg_done = e1000_get_cfg_done_generic;
76 phy->ops.read_reg = e1000_read_phy_reg_m88;
77 phy->ops.reset = e1000_phy_hw_reset_generic;
78 phy->ops.write_reg = e1000_write_phy_reg_m88;
79 phy->ops.get_info = e1000_get_phy_info_m88;
80 phy->ops.power_up = e1000_power_up_phy_copper;
81 phy->ops.power_down = e1000_power_down_phy_copper_82540;
82
83 ret_val = e1000_get_phy_id(hw);
84 if (ret_val)
85 goto out;
86
87 /* Verify phy id */
88 switch (hw->mac.type) {
89 case e1000_82540:
90 case e1000_82545:
91 case e1000_82545_rev_3:
92 case e1000_82546:
93 case e1000_82546_rev_3:
94 if (phy->id == M88E1011_I_PHY_ID)
95 break;
96 /* Fall Through */
97 default:
98 ret_val = -E1000_ERR_PHY;
99 goto out;
100 break;
101 }
102
103 out:
104 return ret_val;
105 }
106
107 /**
108 * e1000_init_nvm_params_82540 - Init NVM func ptrs.
109 * @hw: pointer to the HW structure
110 **/
111 static s32 e1000_init_nvm_params_82540(struct e1000_hw *hw)
112 {
113 struct e1000_nvm_info *nvm = &hw->nvm;
114 u32 eecd = E1000_READ_REG(hw, E1000_EECD);
115
116 DEBUGFUNC("e1000_init_nvm_params_82540");
117
118 nvm->type = e1000_nvm_eeprom_microwire;
119 nvm->delay_usec = 50;
120 nvm->opcode_bits = 3;
121 switch (nvm->override) {
122 case e1000_nvm_override_microwire_large:
123 nvm->address_bits = 8;
124 nvm->word_size = 256;
125 break;
126 case e1000_nvm_override_microwire_small:
127 nvm->address_bits = 6;
128 nvm->word_size = 64;
129 break;
130 default:
131 nvm->address_bits = eecd & E1000_EECD_SIZE ? 8 : 6;
132 nvm->word_size = eecd & E1000_EECD_SIZE ? 256 : 64;
133 break;
134 }
135
136 /* Function Pointers */
137 nvm->ops.acquire = e1000_acquire_nvm_generic;
138 nvm->ops.read = e1000_read_nvm_microwire;
139 nvm->ops.release = e1000_release_nvm_generic;
140 nvm->ops.update = e1000_update_nvm_checksum_generic;
141 nvm->ops.valid_led_default = e1000_valid_led_default_generic;
142 nvm->ops.validate = e1000_validate_nvm_checksum_generic;
143 nvm->ops.write = e1000_write_nvm_microwire;
144
145 return E1000_SUCCESS;
146 }
147
148 /**
149 * e1000_init_mac_params_82540 - Init MAC func ptrs.
150 * @hw: pointer to the HW structure
151 **/
152 static s32 e1000_init_mac_params_82540(struct e1000_hw *hw)
153 {
154 struct e1000_mac_info *mac = &hw->mac;
155 s32 ret_val = E1000_SUCCESS;
156
157 DEBUGFUNC("e1000_init_mac_params_82540");
158
159 /* Set media type */
160 switch (hw->device_id) {
161 case E1000_DEV_ID_82545EM_FIBER:
162 case E1000_DEV_ID_82545GM_FIBER:
163 case E1000_DEV_ID_82546EB_FIBER:
164 case E1000_DEV_ID_82546GB_FIBER:
165 hw->phy.media_type = e1000_media_type_fiber;
166 break;
167 case E1000_DEV_ID_82545GM_SERDES:
168 case E1000_DEV_ID_82546GB_SERDES:
169 hw->phy.media_type = e1000_media_type_internal_serdes;
170 break;
171 default:
172 hw->phy.media_type = e1000_media_type_copper;
173 break;
174 }
175
176 /* Set mta register count */
177 mac->mta_reg_count = 128;
178 /* Set rar entry count */
179 mac->rar_entry_count = E1000_RAR_ENTRIES;
180
181 /* Function pointers */
182
183 /* bus type/speed/width */
184 mac->ops.get_bus_info = e1000_get_bus_info_pci_generic;
185 /* function id */
186 mac->ops.set_lan_id = e1000_set_lan_id_multi_port_pci;
187 /* reset */
188 mac->ops.reset_hw = e1000_reset_hw_82540;
189 /* hw initialization */
190 mac->ops.init_hw = e1000_init_hw_82540;
191 /* link setup */
192 mac->ops.setup_link = e1000_setup_link_generic;
193 /* physical interface setup */
194 mac->ops.setup_physical_interface =
195 (hw->phy.media_type == e1000_media_type_copper)
196 ? e1000_setup_copper_link_82540
197 : e1000_setup_fiber_serdes_link_82540;
198 /* check for link */
199 switch (hw->phy.media_type) {
200 case e1000_media_type_copper:
201 mac->ops.check_for_link = e1000_check_for_copper_link_generic;
202 break;
203 case e1000_media_type_fiber:
204 mac->ops.check_for_link = e1000_check_for_fiber_link_generic;
205 break;
206 case e1000_media_type_internal_serdes:
207 mac->ops.check_for_link = e1000_check_for_serdes_link_generic;
208 break;
209 default:
210 ret_val = -E1000_ERR_CONFIG;
211 goto out;
212 break;
213 }
214 /* link info */
215 mac->ops.get_link_up_info =
216 (hw->phy.media_type == e1000_media_type_copper)
217 ? e1000_get_speed_and_duplex_copper_generic
218 : e1000_get_speed_and_duplex_fiber_serdes_generic;
219 /* multicast address update */
220 mac->ops.update_mc_addr_list = e1000_update_mc_addr_list_generic;
221 /* writing VFTA */
222 mac->ops.write_vfta = e1000_write_vfta_generic;
223 /* clearing VFTA */
224 mac->ops.clear_vfta = e1000_clear_vfta_generic;
225 /* read mac address */
226 mac->ops.read_mac_addr = e1000_read_mac_addr_82540;
227 /* ID LED init */
228 mac->ops.id_led_init = e1000_id_led_init_generic;
229 /* setup LED */
230 mac->ops.setup_led = e1000_setup_led_generic;
231 /* cleanup LED */
232 mac->ops.cleanup_led = e1000_cleanup_led_generic;
233 /* turn on/off LED */
234 mac->ops.led_on = e1000_led_on_generic;
235 mac->ops.led_off = e1000_led_off_generic;
236 /* clear hardware counters */
237 mac->ops.clear_hw_cntrs = e1000_clear_hw_cntrs_82540;
238
239 out:
240 return ret_val;
241 }
242
243 /**
244 * e1000_init_function_pointers_82540 - Init func ptrs.
245 * @hw: pointer to the HW structure
246 *
247 * Called to initialize all function pointers and parameters.
248 **/
249 void e1000_init_function_pointers_82540(struct e1000_hw *hw)
250 {
251 DEBUGFUNC("e1000_init_function_pointers_82540");
252
253 hw->mac.ops.init_params = e1000_init_mac_params_82540;
254 hw->nvm.ops.init_params = e1000_init_nvm_params_82540;
255 hw->phy.ops.init_params = e1000_init_phy_params_82540;
256 }
257
258 /**
259 * e1000_reset_hw_82540 - Reset hardware
260 * @hw: pointer to the HW structure
261 *
262 * This resets the hardware into a known state.
263 **/
264 static s32 e1000_reset_hw_82540(struct e1000_hw *hw)
265 {
266 u32 ctrl, manc;
267 s32 ret_val = E1000_SUCCESS;
268
269 DEBUGFUNC("e1000_reset_hw_82540");
270
271 DEBUGOUT("Masking off all interrupts\n");
272 E1000_WRITE_REG(hw, E1000_IMC, 0xFFFFFFFF);
273
274 E1000_WRITE_REG(hw, E1000_RCTL, 0);
275 E1000_WRITE_REG(hw, E1000_TCTL, E1000_TCTL_PSP);
276 E1000_WRITE_FLUSH(hw);
277
278 /*
279 * Delay to allow any outstanding PCI transactions to complete
280 * before resetting the device.
281 */
282 msec_delay(10);
283
284 ctrl = E1000_READ_REG(hw, E1000_CTRL);
285
286 DEBUGOUT("Issuing a global reset to 82540/82545/82546 MAC\n");
287 switch (hw->mac.type) {
288 case e1000_82545_rev_3:
289 case e1000_82546_rev_3:
290 E1000_WRITE_REG(hw, E1000_CTRL_DUP, ctrl | E1000_CTRL_RST);
291 break;
292 default:
293 /*
294 * These controllers can't ack the 64-bit write when
295 * issuing the reset, so we use IO-mapping as a
296 * workaround to issue the reset.
297 */
298 E1000_WRITE_REG_IO(hw, E1000_CTRL, ctrl | E1000_CTRL_RST);
299 break;
300 }
301
302 /* Wait for EEPROM reload */
303 msec_delay(5);
304
305 /* Disable HW ARPs on ASF enabled adapters */
306 manc = E1000_READ_REG(hw, E1000_MANC);
307 manc &= ~E1000_MANC_ARP_EN;
308 E1000_WRITE_REG(hw, E1000_MANC, manc);
309
310 E1000_WRITE_REG(hw, E1000_IMC, 0xffffffff);
311 E1000_READ_REG(hw, E1000_ICR);
312
313 return ret_val;
314 }
315
316 /**
317 * e1000_init_hw_82540 - Initialize hardware
318 * @hw: pointer to the HW structure
319 *
320 * This inits the hardware readying it for operation.
321 **/
322 static s32 e1000_init_hw_82540(struct e1000_hw *hw)
323 {
324 struct e1000_mac_info *mac = &hw->mac;
325 u32 txdctl, ctrl_ext;
326 s32 ret_val = E1000_SUCCESS;
327 u16 i;
328
329 DEBUGFUNC("e1000_init_hw_82540");
330
331 /* Initialize identification LED */
332 ret_val = mac->ops.id_led_init(hw);
333 if (ret_val) {
334 DEBUGOUT("Error initializing identification LED\n");
335 /* This is not fatal and we should not stop init due to this */
336 }
337
338 /* Disabling VLAN filtering */
339 DEBUGOUT("Initializing the IEEE VLAN\n");
340 if (mac->type < e1000_82545_rev_3)
341 E1000_WRITE_REG(hw, E1000_VET, 0);
342
343 mac->ops.clear_vfta(hw);
344
345 /* Setup the receive address. */
346 e1000_init_rx_addrs_generic(hw, mac->rar_entry_count);
347
348 /* Zero out the Multicast HASH table */
349 DEBUGOUT("Zeroing the MTA\n");
350 for (i = 0; i < mac->mta_reg_count; i++) {
351 E1000_WRITE_REG_ARRAY(hw, E1000_MTA, i, 0);
352 /*
353 * Avoid back to back register writes by adding the register
354 * read (flush). This is to protect against some strange
355 * bridge configurations that may issue Memory Write Block
356 * (MWB) to our register space. The *_rev_3 hardware at
357 * least doesn't respond correctly to every other dword in an
358 * MWB to our register space.
359 */
360 E1000_WRITE_FLUSH(hw);
361 }
362
363 if (mac->type < e1000_82545_rev_3)
364 e1000_pcix_mmrbc_workaround_generic(hw);
365
366 /* Setup link and flow control */
367 ret_val = mac->ops.setup_link(hw);
368
369 txdctl = E1000_READ_REG(hw, E1000_TXDCTL(0));
370 txdctl = (txdctl & ~E1000_TXDCTL_WTHRESH) |
371 E1000_TXDCTL_FULL_TX_DESC_WB;
372 E1000_WRITE_REG(hw, E1000_TXDCTL(0), txdctl);
373
374 /*
375 * Clear all of the statistics registers (clear on read). It is
376 * important that we do this after we have tried to establish link
377 * because the symbol error count will increment wildly if there
378 * is no link.
379 */
380 e1000_clear_hw_cntrs_82540(hw);
381
382 if ((hw->device_id == E1000_DEV_ID_82546GB_QUAD_COPPER) ||
383 (hw->device_id == E1000_DEV_ID_82546GB_QUAD_COPPER_KSP3)) {
384 ctrl_ext = E1000_READ_REG(hw, E1000_CTRL_EXT);
385 /*
386 * Relaxed ordering must be disabled to avoid a parity
387 * error crash in a PCI slot.
388 */
389 ctrl_ext |= E1000_CTRL_EXT_RO_DIS;
390 E1000_WRITE_REG(hw, E1000_CTRL_EXT, ctrl_ext);
391 }
392
393 return ret_val;
394 }
395
396 /**
397 * e1000_setup_copper_link_82540 - Configure copper link settings
398 * @hw: pointer to the HW structure
399 *
400 * Calls the appropriate function to configure the link for auto-neg or forced
401 * speed and duplex. Then we check for link, once link is established calls
402 * to configure collision distance and flow control are called. If link is
403 * not established, we return -E1000_ERR_PHY (-2).
404 **/
405 static s32 e1000_setup_copper_link_82540(struct e1000_hw *hw)
406 {
407 u32 ctrl;
408 s32 ret_val = E1000_SUCCESS;
409 u16 data;
410
411 DEBUGFUNC("e1000_setup_copper_link_82540");
412
413 ctrl = E1000_READ_REG(hw, E1000_CTRL);
414 ctrl |= E1000_CTRL_SLU;
415 ctrl &= ~(E1000_CTRL_FRCSPD | E1000_CTRL_FRCDPX);
416 E1000_WRITE_REG(hw, E1000_CTRL, ctrl);
417
418 ret_val = e1000_set_phy_mode_82540(hw);
419 if (ret_val)
420 goto out;
421
422 if (hw->mac.type == e1000_82545_rev_3 ||
423 hw->mac.type == e1000_82546_rev_3) {
424 ret_val = hw->phy.ops.read_reg(hw, M88E1000_PHY_SPEC_CTRL, &data);
425 if (ret_val)
426 goto out;
427 data |= 0x00000008;
428 ret_val = hw->phy.ops.write_reg(hw, M88E1000_PHY_SPEC_CTRL, data);
429 if (ret_val)
430 goto out;
431 }
432
433 ret_val = e1000_copper_link_setup_m88(hw);
434 if (ret_val)
435 goto out;
436
437 ret_val = e1000_setup_copper_link_generic(hw);
438
439 out:
440 return ret_val;
441 }
442
443 /**
444 * e1000_setup_fiber_serdes_link_82540 - Setup link for fiber/serdes
445 * @hw: pointer to the HW structure
446 *
447 * Set the output amplitude to the value in the EEPROM and adjust the VCO
448 * speed to improve Bit Error Rate (BER) performance. Configures collision
449 * distance and flow control for fiber and serdes links. Upon successful
450 * setup, poll for link.
451 **/
452 static s32 e1000_setup_fiber_serdes_link_82540(struct e1000_hw *hw)
453 {
454 struct e1000_mac_info *mac = &hw->mac;
455 s32 ret_val = E1000_SUCCESS;
456
457 DEBUGFUNC("e1000_setup_fiber_serdes_link_82540");
458
459 switch (mac->type) {
460 case e1000_82545_rev_3:
461 case e1000_82546_rev_3:
462 if (hw->phy.media_type == e1000_media_type_internal_serdes) {
463 /*
464 * If we're on serdes media, adjust the output
465 * amplitude to value set in the EEPROM.
466 */
467 ret_val = e1000_adjust_serdes_amplitude_82540(hw);
468 if (ret_val)
469 goto out;
470 }
471 /* Adjust VCO speed to improve BER performance */
472 ret_val = e1000_set_vco_speed_82540(hw);
473 if (ret_val)
474 goto out;
475 default:
476 break;
477 }
478
479 ret_val = e1000_setup_fiber_serdes_link_generic(hw);
480
481 out:
482 return ret_val;
483 }
484
485 /**
486 * e1000_adjust_serdes_amplitude_82540 - Adjust amplitude based on EEPROM
487 * @hw: pointer to the HW structure
488 *
489 * Adjust the SERDES output amplitude based on the EEPROM settings.
490 **/
491 static s32 e1000_adjust_serdes_amplitude_82540(struct e1000_hw *hw)
492 {
493 s32 ret_val = E1000_SUCCESS;
494 u16 nvm_data;
495
496 DEBUGFUNC("e1000_adjust_serdes_amplitude_82540");
497
498 ret_val = hw->nvm.ops.read(hw, NVM_SERDES_AMPLITUDE, 1, &nvm_data);
499 if (ret_val)
500 goto out;
501
502 if (nvm_data != NVM_RESERVED_WORD) {
503 /* Adjust serdes output amplitude only. */
504 nvm_data &= NVM_SERDES_AMPLITUDE_MASK;
505 ret_val = hw->phy.ops.write_reg(hw,
506 M88E1000_PHY_EXT_CTRL,
507 nvm_data);
508 if (ret_val)
509 goto out;
510 }
511
512 out:
513 return ret_val;
514 }
515
516 /**
517 * e1000_set_vco_speed_82540 - Set VCO speed for better performance
518 * @hw: pointer to the HW structure
519 *
520 * Set the VCO speed to improve Bit Error Rate (BER) performance.
521 **/
522 static s32 e1000_set_vco_speed_82540(struct e1000_hw *hw)
523 {
524 s32 ret_val = E1000_SUCCESS;
525 u16 default_page = 0;
526 u16 phy_data;
527
528 DEBUGFUNC("e1000_set_vco_speed_82540");
529
530 /* Set PHY register 30, page 5, bit 8 to 0 */
531
532 ret_val = hw->phy.ops.read_reg(hw,
533 M88E1000_PHY_PAGE_SELECT,
534 &default_page);
535 if (ret_val)
536 goto out;
537
538 ret_val = hw->phy.ops.write_reg(hw, M88E1000_PHY_PAGE_SELECT, 0x0005);
539 if (ret_val)
540 goto out;
541
542 ret_val = hw->phy.ops.read_reg(hw, M88E1000_PHY_GEN_CONTROL, &phy_data);
543 if (ret_val)
544 goto out;
545
546 phy_data &= ~M88E1000_PHY_VCO_REG_BIT8;
547 ret_val = hw->phy.ops.write_reg(hw, M88E1000_PHY_GEN_CONTROL, phy_data);
548 if (ret_val)
549 goto out;
550
551 /* Set PHY register 30, page 4, bit 11 to 1 */
552
553 ret_val = hw->phy.ops.write_reg(hw, M88E1000_PHY_PAGE_SELECT, 0x0004);
554 if (ret_val)
555 goto out;
556
557 ret_val = hw->phy.ops.read_reg(hw, M88E1000_PHY_GEN_CONTROL, &phy_data);
558 if (ret_val)
559 goto out;
560
561 phy_data |= M88E1000_PHY_VCO_REG_BIT11;
562 ret_val = hw->phy.ops.write_reg(hw, M88E1000_PHY_GEN_CONTROL, phy_data);
563 if (ret_val)
564 goto out;
565
566 ret_val = hw->phy.ops.write_reg(hw, M88E1000_PHY_PAGE_SELECT,
567 default_page);
568
569 out:
570 return ret_val;
571 }
572
573 /**
574 * e1000_set_phy_mode_82540 - Set PHY to class A mode
575 * @hw: pointer to the HW structure
576 *
577 * Sets the PHY to class A mode and assumes the following operations will
578 * follow to enable the new class mode:
579 * 1. Do a PHY soft reset.
580 * 2. Restart auto-negotiation or force link.
581 **/
582 static s32 e1000_set_phy_mode_82540(struct e1000_hw *hw)
583 {
584 struct e1000_phy_info *phy = &hw->phy;
585 s32 ret_val = E1000_SUCCESS;
586 u16 nvm_data;
587
588 DEBUGFUNC("e1000_set_phy_mode_82540");
589
590 if (hw->mac.type != e1000_82545_rev_3)
591 goto out;
592
593 ret_val = hw->nvm.ops.read(hw, NVM_PHY_CLASS_WORD, 1, &nvm_data);
594 if (ret_val) {
595 ret_val = -E1000_ERR_PHY;
596 goto out;
597 }
598
599 if ((nvm_data != NVM_RESERVED_WORD) && (nvm_data & NVM_PHY_CLASS_A)) {
600 ret_val = hw->phy.ops.write_reg(hw, M88E1000_PHY_PAGE_SELECT,
601 0x000B);
602 if (ret_val) {
603 ret_val = -E1000_ERR_PHY;
604 goto out;
605 }
606 ret_val = hw->phy.ops.write_reg(hw,
607 M88E1000_PHY_GEN_CONTROL,
608 0x8104);
609 if (ret_val) {
610 ret_val = -E1000_ERR_PHY;
611 goto out;
612 }
613
614 phy->reset_disable = false;
615 }
616
617 out:
618 return ret_val;
619 }
620
621 /**
622 * e1000_power_down_phy_copper_82540 - Remove link in case of PHY power down
623 * @hw: pointer to the HW structure
624 *
625 * In the case of a PHY power down to save power, or to turn off link during a
626 * driver unload, or wake on lan is not enabled, remove the link.
627 **/
628 static void e1000_power_down_phy_copper_82540(struct e1000_hw *hw)
629 {
630 /* If the management interface is not enabled, then power down */
631 if (!(E1000_READ_REG(hw, E1000_MANC) & E1000_MANC_SMBUS_EN))
632 e1000_power_down_phy_copper(hw);
633
634 return;
635 }
636
637 /**
638 * e1000_clear_hw_cntrs_82540 - Clear device specific hardware counters
639 * @hw: pointer to the HW structure
640 *
641 * Clears the hardware counters by reading the counter registers.
642 **/
643 static void e1000_clear_hw_cntrs_82540(struct e1000_hw *hw)
644 {
645 DEBUGFUNC("e1000_clear_hw_cntrs_82540");
646
647 e1000_clear_hw_cntrs_base_generic(hw);
648
649 E1000_READ_REG(hw, E1000_PRC64);
650 E1000_READ_REG(hw, E1000_PRC127);
651 E1000_READ_REG(hw, E1000_PRC255);
652 E1000_READ_REG(hw, E1000_PRC511);
653 E1000_READ_REG(hw, E1000_PRC1023);
654 E1000_READ_REG(hw, E1000_PRC1522);
655 E1000_READ_REG(hw, E1000_PTC64);
656 E1000_READ_REG(hw, E1000_PTC127);
657 E1000_READ_REG(hw, E1000_PTC255);
658 E1000_READ_REG(hw, E1000_PTC511);
659 E1000_READ_REG(hw, E1000_PTC1023);
660 E1000_READ_REG(hw, E1000_PTC1522);
661
662 E1000_READ_REG(hw, E1000_ALGNERRC);
663 E1000_READ_REG(hw, E1000_RXERRC);
664 E1000_READ_REG(hw, E1000_TNCRS);
665 E1000_READ_REG(hw, E1000_CEXTERR);
666 E1000_READ_REG(hw, E1000_TSCTC);
667 E1000_READ_REG(hw, E1000_TSCTFC);
668
669 E1000_READ_REG(hw, E1000_MGTPRC);
670 E1000_READ_REG(hw, E1000_MGTPDC);
671 E1000_READ_REG(hw, E1000_MGTPTC);
672 }
673
674 /**
675 * e1000_read_mac_addr_82540 - Read device MAC address
676 * @hw: pointer to the HW structure
677 *
678 * Reads the device MAC address from the EEPROM and stores the value.
679 * Since devices with two ports use the same EEPROM, we increment the
680 * last bit in the MAC address for the second port.
681 *
682 * This version is being used over generic because of customer issues
683 * with VmWare and Virtual Box when using generic. It seems in
684 * the emulated 82545, RAR[0] does NOT have a valid address after a
685 * reset, this older method works and using this breaks nothing for
686 * these legacy adapters.
687 **/
688 s32 e1000_read_mac_addr_82540(struct e1000_hw *hw)
689 {
690 s32 ret_val = E1000_SUCCESS;
691 u16 offset, nvm_data, i;
692
693 DEBUGFUNC("e1000_read_mac_addr");
694
695 for (i = 0; i < ETH_ADDR_LEN; i += 2) {
696 offset = i >> 1;
697 ret_val = hw->nvm.ops.read(hw, offset, 1, &nvm_data);
698 if (ret_val) {
699 DEBUGOUT("NVM Read Error\n");
700 goto out;
701 }
702 hw->mac.perm_addr[i] = (u8)(nvm_data & 0xFF);
703 hw->mac.perm_addr[i+1] = (u8)(nvm_data >> 8);
704 }
705
706 /* Flip last bit of mac address if we're on second port */
707 if (hw->bus.func == E1000_FUNC_1)
708 hw->mac.perm_addr[5] ^= 1;
709
710 for (i = 0; i < ETH_ADDR_LEN; i++)
711 hw->mac.addr[i] = hw->mac.perm_addr[i];
712
713 out:
714 return ret_val;
715 }
Mirror of AROS' svn.