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revert between 56095 -> 55830 in arch
[AROS.git] / workbench / devs / networks / e1000 / e1000_82541.c
blob027e0ab61321776cdfc8e30251c8918621431387
1 /*******************************************************************************
2
3 Intel PRO/1000 Linux driver
4 Copyright(c) 1999 - 2010 Intel Corporation.
5
6 This program is free software; you can redistribute it and/or modify it
7 under the terms and conditions of the GNU General Public License,
8 version 2, as published by the Free Software Foundation.
9
10 This program is distributed in the hope it will be useful, but WITHOUT
11 ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
12 FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
13 more details.
14
15 You should have received a copy of the GNU General Public License along with
16 this program; if not, write to the Free Software Foundation, Inc.,
17 51 Franklin St - Fifth Floor, Boston, MA 02110-1301 USA.
18
19 The full GNU General Public License is included in this distribution in
20 the file called "COPYING".
21
22 Contact Information:
23 Linux NICS <linux.nics@intel.com>
24 e1000-devel Mailing List <e1000-devel@lists.sourceforge.net>
25 Intel Corporation, 5200 N.E. Elam Young Parkway, Hillsboro, OR 97124-6497
26
27 *******************************************************************************/
28
29 /*
30 * 82541EI Gigabit Ethernet Controller
31 * 82541ER Gigabit Ethernet Controller
32 * 82541GI Gigabit Ethernet Controller
33 * 82541PI Gigabit Ethernet Controller
34 * 82547EI Gigabit Ethernet Controller
35 * 82547GI Gigabit Ethernet Controller
36 */
37
38 #include "e1000_api.h"
39
40 static s32 e1000_init_phy_params_82541(struct e1000_hw *hw);
41 static s32 e1000_init_nvm_params_82541(struct e1000_hw *hw);
42 static s32 e1000_init_mac_params_82541(struct e1000_hw *hw);
43 static s32 e1000_reset_hw_82541(struct e1000_hw *hw);
44 static s32 e1000_init_hw_82541(struct e1000_hw *hw);
45 static s32 e1000_get_link_up_info_82541(struct e1000_hw *hw, u16 *speed,
46 u16 *duplex);
47 static s32 e1000_phy_hw_reset_82541(struct e1000_hw *hw);
48 static s32 e1000_setup_copper_link_82541(struct e1000_hw *hw);
49 static s32 e1000_check_for_link_82541(struct e1000_hw *hw);
50 static s32 e1000_get_cable_length_igp_82541(struct e1000_hw *hw);
51 static s32 e1000_set_d3_lplu_state_82541(struct e1000_hw *hw,
52 bool active);
53 static s32 e1000_setup_led_82541(struct e1000_hw *hw);
54 static s32 e1000_cleanup_led_82541(struct e1000_hw *hw);
55 static void e1000_clear_hw_cntrs_82541(struct e1000_hw *hw);
56 static s32 e1000_config_dsp_after_link_change_82541(struct e1000_hw *hw,
57 bool link_up);
58 static s32 e1000_phy_init_script_82541(struct e1000_hw *hw);
59 static void e1000_power_down_phy_copper_82541(struct e1000_hw *hw);
60
61 static const u16 e1000_igp_cable_length_table[] =
62 { 5, 5, 5, 5, 5, 5, 5, 5, 5, 5, 5, 5, 5, 5, 5, 5,
63 5, 10, 10, 10, 10, 10, 10, 10, 20, 20, 20, 20, 20, 25, 25, 25,
64 25, 25, 25, 25, 30, 30, 30, 30, 40, 40, 40, 40, 40, 40, 40, 40,
65 40, 50, 50, 50, 50, 50, 50, 50, 60, 60, 60, 60, 60, 60, 60, 60,
66 60, 70, 70, 70, 70, 70, 70, 80, 80, 80, 80, 80, 80, 90, 90, 90,
67 90, 90, 90, 90, 90, 90, 100, 100, 100, 100, 100, 100, 100, 100, 100, 100,
68 100, 100, 100, 100, 110, 110, 110, 110, 110, 110, 110, 110, 110, 110, 110, 110,
69 110, 110, 110, 110, 110, 110, 120, 120, 120, 120, 120, 120, 120, 120, 120, 120};
70 #define IGP01E1000_AGC_LENGTH_TABLE_SIZE \
71 (sizeof(e1000_igp_cable_length_table) / \
72 sizeof(e1000_igp_cable_length_table[0]))
73
74 /**
75 * e1000_init_phy_params_82541 - Init PHY func ptrs.
76 * @hw: pointer to the HW structure
77 **/
78 static s32 e1000_init_phy_params_82541(struct e1000_hw *hw)
79 {
80 struct e1000_phy_info *phy = &hw->phy;
81 s32 ret_val = E1000_SUCCESS;
82
83 DEBUGFUNC("e1000_init_phy_params_82541");
84
85 phy->addr = 1;
86 phy->autoneg_mask = AUTONEG_ADVERTISE_SPEED_DEFAULT;
87 phy->reset_delay_us = 10000;
88 phy->type = e1000_phy_igp;
89
90 /* Function Pointers */
91 phy->ops.check_polarity = e1000_check_polarity_igp;
92 phy->ops.force_speed_duplex = e1000_phy_force_speed_duplex_igp;
93 phy->ops.get_cable_length = e1000_get_cable_length_igp_82541;
94 phy->ops.get_cfg_done = e1000_get_cfg_done_generic;
95 phy->ops.get_info = e1000_get_phy_info_igp;
96 phy->ops.read_reg = e1000_read_phy_reg_igp;
97 phy->ops.reset = e1000_phy_hw_reset_82541;
98 phy->ops.set_d3_lplu_state = e1000_set_d3_lplu_state_82541;
99 phy->ops.write_reg = e1000_write_phy_reg_igp;
100 phy->ops.power_up = e1000_power_up_phy_copper;
101 phy->ops.power_down = e1000_power_down_phy_copper_82541;
102
103 ret_val = e1000_get_phy_id(hw);
104 if (ret_val)
105 goto out;
106
107 /* Verify phy id */
108 if (phy->id != IGP01E1000_I_PHY_ID) {
109 ret_val = -E1000_ERR_PHY;
110 goto out;
111 }
112
113 out:
114 return ret_val;
115 }
116
117 /**
118 * e1000_init_nvm_params_82541 - Init NVM func ptrs.
119 * @hw: pointer to the HW structure
120 **/
121 static s32 e1000_init_nvm_params_82541(struct e1000_hw *hw)
122 {
123 struct e1000_nvm_info *nvm = &hw->nvm;
124 s32 ret_val = E1000_SUCCESS;
125 u32 eecd = E1000_READ_REG(hw, E1000_EECD);
126 u16 size;
127
128 DEBUGFUNC("e1000_init_nvm_params_82541");
129
130 switch (nvm->override) {
131 case e1000_nvm_override_spi_large:
132 nvm->type = e1000_nvm_eeprom_spi;
133 eecd |= E1000_EECD_ADDR_BITS;
134 break;
135 case e1000_nvm_override_spi_small:
136 nvm->type = e1000_nvm_eeprom_spi;
137 eecd &= ~E1000_EECD_ADDR_BITS;
138 break;
139 case e1000_nvm_override_microwire_large:
140 nvm->type = e1000_nvm_eeprom_microwire;
141 eecd |= E1000_EECD_SIZE;
142 break;
143 case e1000_nvm_override_microwire_small:
144 nvm->type = e1000_nvm_eeprom_microwire;
145 eecd &= ~E1000_EECD_SIZE;
146 break;
147 default:
148 nvm->type = eecd & E1000_EECD_TYPE
149 ? e1000_nvm_eeprom_spi
150 : e1000_nvm_eeprom_microwire;
151 break;
152 }
153
154 if (nvm->type == e1000_nvm_eeprom_spi) {
155 nvm->address_bits = (eecd & E1000_EECD_ADDR_BITS)
156 ? 16 : 8;
157 nvm->delay_usec = 1;
158 nvm->opcode_bits = 8;
159 nvm->page_size = (eecd & E1000_EECD_ADDR_BITS)
160 ? 32 : 8;
161
162 /* Function Pointers */
163 nvm->ops.acquire = e1000_acquire_nvm_generic;
164 nvm->ops.read = e1000_read_nvm_spi;
165 nvm->ops.release = e1000_release_nvm_generic;
166 nvm->ops.update = e1000_update_nvm_checksum_generic;
167 nvm->ops.valid_led_default = e1000_valid_led_default_generic;
168 nvm->ops.validate = e1000_validate_nvm_checksum_generic;
169 nvm->ops.write = e1000_write_nvm_spi;
170
171 /*
172 * nvm->word_size must be discovered after the pointers
173 * are set so we can verify the size from the nvm image
174 * itself. Temporarily set it to a dummy value so the
175 * read will work.
176 */
177 nvm->word_size = 64;
178 ret_val = nvm->ops.read(hw, NVM_CFG, 1, &size);
179 if (ret_val)
180 goto out;
181 size = (size & NVM_SIZE_MASK) >> NVM_SIZE_SHIFT;
182 /*
183 * if size != 0, it can be added to a constant and become
184 * the left-shift value to set the word_size. Otherwise,
185 * word_size stays at 64.
186 */
187 if (size) {
188 size += NVM_WORD_SIZE_BASE_SHIFT_82541;
189 nvm->word_size = 1 << size;
190 }
191 } else {
192 nvm->address_bits = (eecd & E1000_EECD_ADDR_BITS)
193 ? 8 : 6;
194 nvm->delay_usec = 50;
195 nvm->opcode_bits = 3;
196 nvm->word_size = (eecd & E1000_EECD_ADDR_BITS)
197 ? 256 : 64;
198
199 /* Function Pointers */
200 nvm->ops.acquire = e1000_acquire_nvm_generic;
201 nvm->ops.read = e1000_read_nvm_microwire;
202 nvm->ops.release = e1000_release_nvm_generic;
203 nvm->ops.update = e1000_update_nvm_checksum_generic;
204 nvm->ops.valid_led_default = e1000_valid_led_default_generic;
205 nvm->ops.validate = e1000_validate_nvm_checksum_generic;
206 nvm->ops.write = e1000_write_nvm_microwire;
207 }
208
209 out:
210 return ret_val;
211 }
212
213 /**
214 * e1000_init_mac_params_82541 - Init MAC func ptrs.
215 * @hw: pointer to the HW structure
216 **/
217 static s32 e1000_init_mac_params_82541(struct e1000_hw *hw)
218 {
219 struct e1000_mac_info *mac = &hw->mac;
220
221 DEBUGFUNC("e1000_init_mac_params_82541");
222
223 /* Set media type */
224 hw->phy.media_type = e1000_media_type_copper;
225 /* Set mta register count */
226 mac->mta_reg_count = 128;
227 /* Set rar entry count */
228 mac->rar_entry_count = E1000_RAR_ENTRIES;
229 /* Set if part includes ASF firmware */
230 mac->asf_firmware_present = true;
231
232 /* Function Pointers */
233
234 /* bus type/speed/width */
235 mac->ops.get_bus_info = e1000_get_bus_info_pci_generic;
236 /* function id */
237 mac->ops.set_lan_id = e1000_set_lan_id_single_port;
238 /* reset */
239 mac->ops.reset_hw = e1000_reset_hw_82541;
240 /* hw initialization */
241 mac->ops.init_hw = e1000_init_hw_82541;
242 /* link setup */
243 mac->ops.setup_link = e1000_setup_link_generic;
244 /* physical interface link setup */
245 mac->ops.setup_physical_interface = e1000_setup_copper_link_82541;
246 /* check for link */
247 mac->ops.check_for_link = e1000_check_for_link_82541;
248 /* link info */
249 mac->ops.get_link_up_info = e1000_get_link_up_info_82541;
250 /* multicast address update */
251 mac->ops.update_mc_addr_list = e1000_update_mc_addr_list_generic;
252 /* writing VFTA */
253 mac->ops.write_vfta = e1000_write_vfta_generic;
254 /* clearing VFTA */
255 mac->ops.clear_vfta = e1000_clear_vfta_generic;
256 /* ID LED init */
257 mac->ops.id_led_init = e1000_id_led_init_generic;
258 /* setup LED */
259 mac->ops.setup_led = e1000_setup_led_82541;
260 /* cleanup LED */
261 mac->ops.cleanup_led = e1000_cleanup_led_82541;
262 /* turn on/off LED */
263 mac->ops.led_on = e1000_led_on_generic;
264 mac->ops.led_off = e1000_led_off_generic;
265 /* clear hardware counters */
266 mac->ops.clear_hw_cntrs = e1000_clear_hw_cntrs_82541;
267
268 return E1000_SUCCESS;
269 }
270
271 /**
272 * e1000_init_function_pointers_82541 - Init func ptrs.
273 * @hw: pointer to the HW structure
274 *
275 * Called to initialize all function pointers and parameters.
276 **/
277 void e1000_init_function_pointers_82541(struct e1000_hw *hw)
278 {
279 DEBUGFUNC("e1000_init_function_pointers_82541");
280
281 hw->mac.ops.init_params = e1000_init_mac_params_82541;
282 hw->nvm.ops.init_params = e1000_init_nvm_params_82541;
283 hw->phy.ops.init_params = e1000_init_phy_params_82541;
284 }
285
286 /**
287 * e1000_reset_hw_82541 - Reset hardware
288 * @hw: pointer to the HW structure
289 *
290 * This resets the hardware into a known state.
291 **/
292 static s32 e1000_reset_hw_82541(struct e1000_hw *hw)
293 {
294 u32 ledctl, ctrl, manc;
295
296 DEBUGFUNC("e1000_reset_hw_82541");
297
298 DEBUGOUT("Masking off all interrupts\n");
299 E1000_WRITE_REG(hw, E1000_IMC, 0xFFFFFFFF);
300
301 E1000_WRITE_REG(hw, E1000_RCTL, 0);
302 E1000_WRITE_REG(hw, E1000_TCTL, E1000_TCTL_PSP);
303 E1000_WRITE_FLUSH(hw);
304
305 /*
306 * Delay to allow any outstanding PCI transactions to complete
307 * before resetting the device.
308 */
309 msec_delay(10);
310
311 ctrl = E1000_READ_REG(hw, E1000_CTRL);
312
313 /* Must reset the Phy before resetting the MAC */
314 if ((hw->mac.type == e1000_82541) || (hw->mac.type == e1000_82547)) {
315 E1000_WRITE_REG(hw, E1000_CTRL, (ctrl | E1000_CTRL_PHY_RST));
316 E1000_WRITE_FLUSH(hw);
317 msec_delay(5);
318 }
319
320 DEBUGOUT("Issuing a global reset to 82541/82547 MAC\n");
321 switch (hw->mac.type) {
322 case e1000_82541:
323 case e1000_82541_rev_2:
324 /*
325 * These controllers can't ack the 64-bit write when
326 * issuing the reset, so we use IO-mapping as a
327 * workaround to issue the reset.
328 */
329 E1000_WRITE_REG_IO(hw, E1000_CTRL, ctrl | E1000_CTRL_RST);
330 break;
331 default:
332 E1000_WRITE_REG(hw, E1000_CTRL, ctrl | E1000_CTRL_RST);
333 break;
334 }
335
336 /* Wait for NVM reload */
337 msec_delay(20);
338
339 /* Disable HW ARPs on ASF enabled adapters */
340 manc = E1000_READ_REG(hw, E1000_MANC);
341 manc &= ~E1000_MANC_ARP_EN;
342 E1000_WRITE_REG(hw, E1000_MANC, manc);
343
344 if ((hw->mac.type == e1000_82541) || (hw->mac.type == e1000_82547)) {
345 e1000_phy_init_script_82541(hw);
346
347 /* Configure activity LED after Phy reset */
348 ledctl = E1000_READ_REG(hw, E1000_LEDCTL);
349 ledctl &= IGP_ACTIVITY_LED_MASK;
350 ledctl |= (IGP_ACTIVITY_LED_ENABLE | IGP_LED3_MODE);
351 E1000_WRITE_REG(hw, E1000_LEDCTL, ledctl);
352 }
353
354 /* Once again, mask the interrupts */
355 DEBUGOUT("Masking off all interrupts\n");
356 E1000_WRITE_REG(hw, E1000_IMC, 0xFFFFFFFF);
357
358 /* Clear any pending interrupt events. */
359 E1000_READ_REG(hw, E1000_ICR);
360
361 return E1000_SUCCESS;
362 }
363
364 /**
365 * e1000_init_hw_82541 - Initialize hardware
366 * @hw: pointer to the HW structure
367 *
368 * This inits the hardware readying it for operation.
369 **/
370 static s32 e1000_init_hw_82541(struct e1000_hw *hw)
371 {
372 struct e1000_mac_info *mac = &hw->mac;
373 struct e1000_dev_spec_82541 *dev_spec = &hw->dev_spec._82541;
374 u32 i, txdctl;
375 s32 ret_val;
376
377 DEBUGFUNC("e1000_init_hw_82541");
378
379 /* Initialize identification LED */
380 ret_val = mac->ops.id_led_init(hw);
381 if (ret_val) {
382 DEBUGOUT("Error initializing identification LED\n");
383 /* This is not fatal and we should not stop init due to this */
384 }
385
386 /* Storing the Speed Power Down value for later use */
387 ret_val = hw->phy.ops.read_reg(hw,
388 IGP01E1000_GMII_FIFO,
389 &dev_spec->spd_default);
390 if (ret_val)
391 goto out;
392
393 /* Disabling VLAN filtering */
394 DEBUGOUT("Initializing the IEEE VLAN\n");
395 mac->ops.clear_vfta(hw);
396
397 /* Setup the receive address. */
398 e1000_init_rx_addrs_generic(hw, mac->rar_entry_count);
399
400 /* Zero out the Multicast HASH table */
401 DEBUGOUT("Zeroing the MTA\n");
402 for (i = 0; i < mac->mta_reg_count; i++) {
403 E1000_WRITE_REG_ARRAY(hw, E1000_MTA, i, 0);
404 /*
405 * Avoid back to back register writes by adding the register
406 * read (flush). This is to protect against some strange
407 * bridge configurations that may issue Memory Write Block
408 * (MWB) to our register space.
409 */
410 E1000_WRITE_FLUSH(hw);
411 }
412
413 /* Setup link and flow control */
414 ret_val = mac->ops.setup_link(hw);
415
416 txdctl = E1000_READ_REG(hw, E1000_TXDCTL(0));
417 txdctl = (txdctl & ~E1000_TXDCTL_WTHRESH) |
418 E1000_TXDCTL_FULL_TX_DESC_WB;
419 E1000_WRITE_REG(hw, E1000_TXDCTL(0), txdctl);
420
421 /*
422 * Clear all of the statistics registers (clear on read). It is
423 * important that we do this after we have tried to establish link
424 * because the symbol error count will increment wildly if there
425 * is no link.
426 */
427 e1000_clear_hw_cntrs_82541(hw);
428
429 out:
430 return ret_val;
431 }
432
433 /**
434 * e1000_get_link_up_info_82541 - Report speed and duplex
435 * @hw: pointer to the HW structure
436 * @speed: pointer to speed buffer
437 * @duplex: pointer to duplex buffer
438 *
439 * Retrieve the current speed and duplex configuration.
440 **/
441 static s32 e1000_get_link_up_info_82541(struct e1000_hw *hw, u16 *speed,
442 u16 *duplex)
443 {
444 struct e1000_phy_info *phy = &hw->phy;
445 s32 ret_val;
446 u16 data;
447
448 DEBUGFUNC("e1000_get_link_up_info_82541");
449
450 ret_val = e1000_get_speed_and_duplex_copper_generic(hw, speed, duplex);
451 if (ret_val)
452 goto out;
453
454 if (!phy->speed_downgraded)
455 goto out;
456
457 /*
458 * IGP01 PHY may advertise full duplex operation after speed
459 * downgrade even if it is operating at half duplex.
460 * Here we set the duplex settings to match the duplex in the
461 * link partner's capabilities.
462 */
463 ret_val = phy->ops.read_reg(hw, PHY_AUTONEG_EXP, &data);
464 if (ret_val)
465 goto out;
466
467 if (!(data & NWAY_ER_LP_NWAY_CAPS)) {
468 *duplex = HALF_DUPLEX;
469 } else {
470 ret_val = phy->ops.read_reg(hw, PHY_LP_ABILITY, &data);
471 if (ret_val)
472 goto out;
473
474 if (*speed == SPEED_100) {
475 if (!(data & NWAY_LPAR_100TX_FD_CAPS))
476 *duplex = HALF_DUPLEX;
477 } else if (*speed == SPEED_10) {
478 if (!(data & NWAY_LPAR_10T_FD_CAPS))
479 *duplex = HALF_DUPLEX;
480 }
481 }
482
483 out:
484 return ret_val;
485 }
486
487 /**
488 * e1000_phy_hw_reset_82541 - PHY hardware reset
489 * @hw: pointer to the HW structure
490 *
491 * Verify the reset block is not blocking us from resetting. Acquire
492 * semaphore (if necessary) and read/set/write the device control reset
493 * bit in the PHY. Wait the appropriate delay time for the device to
494 * reset and release the semaphore (if necessary).
495 **/
496 static s32 e1000_phy_hw_reset_82541(struct e1000_hw *hw)
497 {
498 s32 ret_val;
499 u32 ledctl;
500
501 DEBUGFUNC("e1000_phy_hw_reset_82541");
502
503 ret_val = e1000_phy_hw_reset_generic(hw);
504 if (ret_val)
505 goto out;
506
507 e1000_phy_init_script_82541(hw);
508
509 if ((hw->mac.type == e1000_82541) || (hw->mac.type == e1000_82547)) {
510 /* Configure activity LED after PHY reset */
511 ledctl = E1000_READ_REG(hw, E1000_LEDCTL);
512 ledctl &= IGP_ACTIVITY_LED_MASK;
513 ledctl |= (IGP_ACTIVITY_LED_ENABLE | IGP_LED3_MODE);
514 E1000_WRITE_REG(hw, E1000_LEDCTL, ledctl);
515 }
516
517 out:
518 return ret_val;
519 }
520
521 /**
522 * e1000_setup_copper_link_82541 - Configure copper link settings
523 * @hw: pointer to the HW structure
524 *
525 * Calls the appropriate function to configure the link for auto-neg or forced
526 * speed and duplex. Then we check for link, once link is established calls
527 * to configure collision distance and flow control are called. If link is
528 * not established, we return -E1000_ERR_PHY (-2).
529 **/
530 static s32 e1000_setup_copper_link_82541(struct e1000_hw *hw)
531 {
532 struct e1000_phy_info *phy = &hw->phy;
533 struct e1000_dev_spec_82541 *dev_spec = &hw->dev_spec._82541;
534 s32 ret_val;
535 u32 ctrl, ledctl;
536
537 DEBUGFUNC("e1000_setup_copper_link_82541");
538
539 ctrl = E1000_READ_REG(hw, E1000_CTRL);
540 ctrl |= E1000_CTRL_SLU;
541 ctrl &= ~(E1000_CTRL_FRCSPD | E1000_CTRL_FRCDPX);
542 E1000_WRITE_REG(hw, E1000_CTRL, ctrl);
543
544 hw->phy.reset_disable = false;
545
546 /* Earlier revs of the IGP phy require us to force MDI. */
547 if (hw->mac.type == e1000_82541 || hw->mac.type == e1000_82547) {
548 dev_spec->dsp_config = e1000_dsp_config_disabled;
549 phy->mdix = 1;
550 } else {
551 dev_spec->dsp_config = e1000_dsp_config_enabled;
552 }
553
554 ret_val = e1000_copper_link_setup_igp(hw);
555 if (ret_val)
556 goto out;
557
558 if (hw->mac.autoneg) {
559 if (dev_spec->ffe_config == e1000_ffe_config_active)
560 dev_spec->ffe_config = e1000_ffe_config_enabled;
561 }
562
563 /* Configure activity LED after Phy reset */
564 ledctl = E1000_READ_REG(hw, E1000_LEDCTL);
565 ledctl &= IGP_ACTIVITY_LED_MASK;
566 ledctl |= (IGP_ACTIVITY_LED_ENABLE | IGP_LED3_MODE);
567 E1000_WRITE_REG(hw, E1000_LEDCTL, ledctl);
568
569 ret_val = e1000_setup_copper_link_generic(hw);
570
571 out:
572 return ret_val;
573 }
574
575 /**
576 * e1000_check_for_link_82541 - Check/Store link connection
577 * @hw: pointer to the HW structure
578 *
579 * This checks the link condition of the adapter and stores the
580 * results in the hw->mac structure.
581 **/
582 static s32 e1000_check_for_link_82541(struct e1000_hw *hw)
583 {
584 struct e1000_mac_info *mac = &hw->mac;
585 s32 ret_val;
586 bool link;
587
588 DEBUGFUNC("e1000_check_for_link_82541");
589
590 /*
591 * We only want to go out to the PHY registers to see if Auto-Neg
592 * has completed and/or if our link status has changed. The
593 * get_link_status flag is set upon receiving a Link Status
594 * Change or Rx Sequence Error interrupt.
595 */
596 if (!mac->get_link_status) {
597 ret_val = E1000_SUCCESS;
598 goto out;
599 }
600
601 /*
602 * First we want to see if the MII Status Register reports
603 * link. If so, then we want to get the current speed/duplex
604 * of the PHY.
605 */
606 ret_val = e1000_phy_has_link_generic(hw, 1, 0, &link);
607 if (ret_val)
608 goto out;
609
610 if (!link) {
611 ret_val = e1000_config_dsp_after_link_change_82541(hw, false);
612 goto out; /* No link detected */
613 }
614
615 mac->get_link_status = false;
616
617 /*
618 * Check if there was DownShift, must be checked
619 * immediately after link-up
620 */
621 e1000_check_downshift_generic(hw);
622
623 /*
624 * If we are forcing speed/duplex, then we simply return since
625 * we have already determined whether we have link or not.
626 */
627 if (!mac->autoneg) {
628 ret_val = -E1000_ERR_CONFIG;
629 goto out;
630 }
631
632 ret_val = e1000_config_dsp_after_link_change_82541(hw, true);
633
634 /*
635 * Auto-Neg is enabled. Auto Speed Detection takes care
636 * of MAC speed/duplex configuration. So we only need to
637 * configure Collision Distance in the MAC.
638 */
639 e1000_config_collision_dist_generic(hw);
640
641 /*
642 * Configure Flow Control now that Auto-Neg has completed.
643 * First, we need to restore the desired flow control
644 * settings because we may have had to re-autoneg with a
645 * different link partner.
646 */
647 ret_val = e1000_config_fc_after_link_up_generic(hw);
648 if (ret_val) {
649 DEBUGOUT("Error configuring flow control\n");
650 }
651
652 out:
653 return ret_val;
654 }
655
656 /**
657 * e1000_config_dsp_after_link_change_82541 - Config DSP after link
658 * @hw: pointer to the HW structure
659 * @link_up: boolean flag for link up status
660 *
661 * Return E1000_ERR_PHY when failing to read/write the PHY, else E1000_SUCCESS
662 * at any other case.
663 *
664 * 82541_rev_2 & 82547_rev_2 have the capability to configure the DSP when a
665 * gigabit link is achieved to improve link quality.
666 **/
667 static s32 e1000_config_dsp_after_link_change_82541(struct e1000_hw *hw,
668 bool link_up)
669 {
670 struct e1000_phy_info *phy = &hw->phy;
671 struct e1000_dev_spec_82541 *dev_spec = &hw->dev_spec._82541;
672 s32 ret_val;
673 u32 idle_errs = 0;
674 u16 phy_data, phy_saved_data, speed, duplex, i;
675 u16 ffe_idle_err_timeout = FFE_IDLE_ERR_COUNT_TIMEOUT_20;
676 u16 dsp_reg_array[IGP01E1000_PHY_CHANNEL_NUM] =
677 {IGP01E1000_PHY_AGC_PARAM_A,
678 IGP01E1000_PHY_AGC_PARAM_B,
679 IGP01E1000_PHY_AGC_PARAM_C,
680 IGP01E1000_PHY_AGC_PARAM_D};
681
682 DEBUGFUNC("e1000_config_dsp_after_link_change_82541");
683
684 if (link_up) {
685 ret_val = hw->mac.ops.get_link_up_info(hw, &speed, &duplex);
686 if (ret_val) {
687 DEBUGOUT("Error getting link speed and duplex\n");
688 goto out;
689 }
690
691 if (speed != SPEED_1000) {
692 ret_val = E1000_SUCCESS;
693 goto out;
694 }
695
696 ret_val = phy->ops.get_cable_length(hw);
697 if (ret_val)
698 goto out;
699
700 if ((dev_spec->dsp_config == e1000_dsp_config_enabled) &&
701 phy->min_cable_length >= 50) {
702
703 for (i = 0; i < IGP01E1000_PHY_CHANNEL_NUM; i++) {
704 ret_val = phy->ops.read_reg(hw,
705 dsp_reg_array[i],
706 &phy_data);
707 if (ret_val)
708 goto out;
709
710 phy_data &= ~IGP01E1000_PHY_EDAC_MU_INDEX;
711
712 ret_val = phy->ops.write_reg(hw,
713 dsp_reg_array[i],
714 phy_data);
715 if (ret_val)
716 goto out;
717 }
718 dev_spec->dsp_config = e1000_dsp_config_activated;
719 }
720
721 if ((dev_spec->ffe_config != e1000_ffe_config_enabled) ||
722 (phy->min_cable_length >= 50)) {
723 ret_val = E1000_SUCCESS;
724 goto out;
725 }
726
727 /* clear previous idle error counts */
728 ret_val = phy->ops.read_reg(hw, PHY_1000T_STATUS, &phy_data);
729 if (ret_val)
730 goto out;
731
732 for (i = 0; i < ffe_idle_err_timeout; i++) {
733 usec_delay(1000);
734 ret_val = phy->ops.read_reg(hw,
735 PHY_1000T_STATUS,
736 &phy_data);
737 if (ret_val)
738 goto out;
739
740 idle_errs += (phy_data & SR_1000T_IDLE_ERROR_CNT);
741 if (idle_errs > SR_1000T_PHY_EXCESSIVE_IDLE_ERR_COUNT) {
742 dev_spec->ffe_config = e1000_ffe_config_active;
743
744 ret_val = phy->ops.write_reg(hw,
745 IGP01E1000_PHY_DSP_FFE,
746 IGP01E1000_PHY_DSP_FFE_CM_CP);
747 if (ret_val)
748 goto out;
749 break;
750 }
751
752 if (idle_errs)
753 ffe_idle_err_timeout =
754 FFE_IDLE_ERR_COUNT_TIMEOUT_100;
755 }
756 } else {
757 if (dev_spec->dsp_config == e1000_dsp_config_activated) {
758 /*
759 * Save off the current value of register 0x2F5B
760 * to be restored at the end of the routines.
761 */
762 ret_val = phy->ops.read_reg(hw,
763 0x2F5B,
764 &phy_saved_data);
765 if (ret_val)
766 goto out;
767
768 /* Disable the PHY transmitter */
769 ret_val = phy->ops.write_reg(hw, 0x2F5B, 0x0003);
770 if (ret_val)
771 goto out;
772
773 msec_delay_irq(20);
774
775 ret_val = phy->ops.write_reg(hw,
776 0x0000,
777 IGP01E1000_IEEE_FORCE_GIG);
778 if (ret_val)
779 goto out;
780 for (i = 0; i < IGP01E1000_PHY_CHANNEL_NUM; i++) {
781 ret_val = phy->ops.read_reg(hw,
782 dsp_reg_array[i],
783 &phy_data);
784 if (ret_val)
785 goto out;
786
787 phy_data &= ~IGP01E1000_PHY_EDAC_MU_INDEX;
788 phy_data |= IGP01E1000_PHY_EDAC_SIGN_EXT_9_BITS;
789
790 ret_val = phy->ops.write_reg(hw,
791 dsp_reg_array[i],
792 phy_data);
793 if (ret_val)
794 goto out;
795 }
796
797 ret_val = phy->ops.write_reg(hw,
798 0x0000,
799 IGP01E1000_IEEE_RESTART_AUTONEG);
800 if (ret_val)
801 goto out;
802
803 msec_delay_irq(20);
804
805 /* Now enable the transmitter */
806 ret_val = phy->ops.write_reg(hw,
807 0x2F5B,
808 phy_saved_data);
809 if (ret_val)
810 goto out;
811
812 dev_spec->dsp_config = e1000_dsp_config_enabled;
813 }
814
815 if (dev_spec->ffe_config != e1000_ffe_config_active) {
816 ret_val = E1000_SUCCESS;
817 goto out;
818 }
819
820 /*
821 * Save off the current value of register 0x2F5B
822 * to be restored at the end of the routines.
823 */
824 ret_val = phy->ops.read_reg(hw, 0x2F5B, &phy_saved_data);
825 if (ret_val)
826 goto out;
827
828 /* Disable the PHY transmitter */
829 ret_val = phy->ops.write_reg(hw, 0x2F5B, 0x0003);
830 if (ret_val)
831 goto out;
832
833 msec_delay_irq(20);
834
835 ret_val = phy->ops.write_reg(hw,
836 0x0000,
837 IGP01E1000_IEEE_FORCE_GIG);
838 if (ret_val)
839 goto out;
840
841 ret_val = phy->ops.write_reg(hw,
842 IGP01E1000_PHY_DSP_FFE,
843 IGP01E1000_PHY_DSP_FFE_DEFAULT);
844 if (ret_val)
845 goto out;
846
847 ret_val = phy->ops.write_reg(hw,
848 0x0000,
849 IGP01E1000_IEEE_RESTART_AUTONEG);
850 if (ret_val)
851 goto out;
852
853 msec_delay_irq(20);
854
855 /* Now enable the transmitter */
856 ret_val = phy->ops.write_reg(hw, 0x2F5B, phy_saved_data);
857
858 if (ret_val)
859 goto out;
860
861 dev_spec->ffe_config = e1000_ffe_config_enabled;
862 }
863
864 out:
865 return ret_val;
866 }
867
868 /**
869 * e1000_get_cable_length_igp_82541 - Determine cable length for igp PHY
870 * @hw: pointer to the HW structure
871 *
872 * The automatic gain control (agc) normalizes the amplitude of the
873 * received signal, adjusting for the attenuation produced by the
874 * cable. By reading the AGC registers, which represent the
875 * combination of coarse and fine gain value, the value can be put
876 * into a lookup table to obtain the approximate cable length
877 * for each channel.
878 **/
879 static s32 e1000_get_cable_length_igp_82541(struct e1000_hw *hw)
880 {
881 struct e1000_phy_info *phy = &hw->phy;
882 s32 ret_val = E1000_SUCCESS;
883 u16 i, data;
884 u16 cur_agc_value, agc_value = 0;
885 u16 min_agc_value = IGP01E1000_AGC_LENGTH_TABLE_SIZE;
886 u16 agc_reg_array[IGP01E1000_PHY_CHANNEL_NUM] =
887 {IGP01E1000_PHY_AGC_A,
888 IGP01E1000_PHY_AGC_B,
889 IGP01E1000_PHY_AGC_C,
890 IGP01E1000_PHY_AGC_D};
891
892 DEBUGFUNC("e1000_get_cable_length_igp_82541");
893
894 /* Read the AGC registers for all channels */
895 for (i = 0; i < IGP01E1000_PHY_CHANNEL_NUM; i++) {
896 ret_val = phy->ops.read_reg(hw, agc_reg_array[i], &data);
897 if (ret_val)
898 goto out;
899
900 cur_agc_value = data >> IGP01E1000_AGC_LENGTH_SHIFT;
901
902 /* Bounds checking */
903 if ((cur_agc_value >= IGP01E1000_AGC_LENGTH_TABLE_SIZE - 1) ||
904 (cur_agc_value == 0)) {
905 ret_val = -E1000_ERR_PHY;
906 goto out;
907 }
908
909 agc_value += cur_agc_value;
910
911 if (min_agc_value > cur_agc_value)
912 min_agc_value = cur_agc_value;
913 }
914
915 /* Remove the minimal AGC result for length < 50m */
916 if (agc_value < IGP01E1000_PHY_CHANNEL_NUM * 50) {
917 agc_value -= min_agc_value;
918 /* Average the three remaining channels for the length. */
919 agc_value /= (IGP01E1000_PHY_CHANNEL_NUM - 1);
920 } else {
921 /* Average the channels for the length. */
922 agc_value /= IGP01E1000_PHY_CHANNEL_NUM;
923 }
924
925 phy->min_cable_length = (e1000_igp_cable_length_table[agc_value] >
926 IGP01E1000_AGC_RANGE)
927 ? (e1000_igp_cable_length_table[agc_value] -
928 IGP01E1000_AGC_RANGE)
929 : 0;
930 phy->max_cable_length = e1000_igp_cable_length_table[agc_value] +
931 IGP01E1000_AGC_RANGE;
932
933 phy->cable_length = (phy->min_cable_length + phy->max_cable_length) / 2;
934
935 out:
936 return ret_val;
937 }
938
939 /**
940 * e1000_set_d3_lplu_state_82541 - Sets low power link up state for D3
941 * @hw: pointer to the HW structure
942 * @active: boolean used to enable/disable lplu
943 *
944 * Success returns 0, Failure returns 1
945 *
946 * The low power link up (lplu) state is set to the power management level D3
947 * and SmartSpeed is disabled when active is true, else clear lplu for D3
948 * and enable Smartspeed. LPLU and Smartspeed are mutually exclusive. LPLU
949 * is used during Dx states where the power conservation is most important.
950 * During driver activity, SmartSpeed should be enabled so performance is
951 * maintained.
952 **/
953 static s32 e1000_set_d3_lplu_state_82541(struct e1000_hw *hw, bool active)
954 {
955 struct e1000_phy_info *phy = &hw->phy;
956 s32 ret_val;
957 u16 data;
958
959 DEBUGFUNC("e1000_set_d3_lplu_state_82541");
960
961 switch (hw->mac.type) {
962 case e1000_82541_rev_2:
963 case e1000_82547_rev_2:
964 break;
965 default:
966 ret_val = e1000_set_d3_lplu_state_generic(hw, active);
967 goto out;
968 break;
969 }
970
971 ret_val = phy->ops.read_reg(hw, IGP01E1000_GMII_FIFO, &data);
972 if (ret_val)
973 goto out;
974
975 if (!active) {
976 data &= ~IGP01E1000_GMII_FLEX_SPD;
977 ret_val = phy->ops.write_reg(hw, IGP01E1000_GMII_FIFO, data);
978 if (ret_val)
979 goto out;
980
981 /*
982 * LPLU and SmartSpeed are mutually exclusive. LPLU is used
983 * during Dx states where the power conservation is most
984 * important. During driver activity we should enable
985 * SmartSpeed, so performance is maintained.
986 */
987 if (phy->smart_speed == e1000_smart_speed_on) {
988 ret_val = phy->ops.read_reg(hw,
989 IGP01E1000_PHY_PORT_CONFIG,
990 &data);
991 if (ret_val)
992 goto out;
993
994 data |= IGP01E1000_PSCFR_SMART_SPEED;
995 ret_val = phy->ops.write_reg(hw,
996 IGP01E1000_PHY_PORT_CONFIG,
997 data);
998 if (ret_val)
999 goto out;
1000 } else if (phy->smart_speed == e1000_smart_speed_off) {
1001 ret_val = phy->ops.read_reg(hw,
1002 IGP01E1000_PHY_PORT_CONFIG,
1003 &data);
1004 if (ret_val)
1005 goto out;
1006
1007 data &= ~IGP01E1000_PSCFR_SMART_SPEED;
1008 ret_val = phy->ops.write_reg(hw,
1009 IGP01E1000_PHY_PORT_CONFIG,
1010 data);
1011 if (ret_val)
1012 goto out;
1013 }
1014 } else if ((phy->autoneg_advertised == E1000_ALL_SPEED_DUPLEX) ||
1015 (phy->autoneg_advertised == E1000_ALL_NOT_GIG) ||
1016 (phy->autoneg_advertised == E1000_ALL_10_SPEED)) {
1017 data |= IGP01E1000_GMII_FLEX_SPD;
1018 ret_val = phy->ops.write_reg(hw, IGP01E1000_GMII_FIFO, data);
1019 if (ret_val)
1020 goto out;
1021
1022 /* When LPLU is enabled, we should disable SmartSpeed */
1023 ret_val = phy->ops.read_reg(hw,
1024 IGP01E1000_PHY_PORT_CONFIG,
1025 &data);
1026 if (ret_val)
1027 goto out;
1028
1029 data &= ~IGP01E1000_PSCFR_SMART_SPEED;
1030 ret_val = phy->ops.write_reg(hw,
1031 IGP01E1000_PHY_PORT_CONFIG,
1032 data);
1033 }
1034
1035 out:
1036 return ret_val;
1037 }
1038
1039 /**
1040 * e1000_setup_led_82541 - Configures SW controllable LED
1041 * @hw: pointer to the HW structure
1042 *
1043 * This prepares the SW controllable LED for use and saves the current state
1044 * of the LED so it can be later restored.
1045 **/
1046 static s32 e1000_setup_led_82541(struct e1000_hw *hw)
1047 {
1048 struct e1000_dev_spec_82541 *dev_spec = &hw->dev_spec._82541;
1049 s32 ret_val;
1050
1051 DEBUGFUNC("e1000_setup_led_82541");
1052
1053 ret_val = hw->phy.ops.read_reg(hw,
1054 IGP01E1000_GMII_FIFO,
1055 &dev_spec->spd_default);
1056 if (ret_val)
1057 goto out;
1058
1059 ret_val = hw->phy.ops.write_reg(hw,
1060 IGP01E1000_GMII_FIFO,
1061 (u16)(dev_spec->spd_default &
1062 ~IGP01E1000_GMII_SPD));
1063 if (ret_val)
1064 goto out;
1065
1066 E1000_WRITE_REG(hw, E1000_LEDCTL, hw->mac.ledctl_mode1);
1067
1068 out:
1069 return ret_val;
1070 }
1071
1072 /**
1073 * e1000_cleanup_led_82541 - Set LED config to default operation
1074 * @hw: pointer to the HW structure
1075 *
1076 * Remove the current LED configuration and set the LED configuration
1077 * to the default value, saved from the EEPROM.
1078 **/
1079 static s32 e1000_cleanup_led_82541(struct e1000_hw *hw)
1080 {
1081 struct e1000_dev_spec_82541 *dev_spec = &hw->dev_spec._82541;
1082 s32 ret_val;
1083
1084 DEBUGFUNC("e1000_cleanup_led_82541");
1085
1086 ret_val = hw->phy.ops.write_reg(hw,
1087 IGP01E1000_GMII_FIFO,
1088 dev_spec->spd_default);
1089 if (ret_val)
1090 goto out;
1091
1092 E1000_WRITE_REG(hw, E1000_LEDCTL, hw->mac.ledctl_default);
1093
1094 out:
1095 return ret_val;
1096 }
1097
1098 /**
1099 * e1000_phy_init_script_82541 - Initialize GbE PHY
1100 * @hw: pointer to the HW structure
1101 *
1102 * Initializes the IGP PHY.
1103 **/
1104 static s32 e1000_phy_init_script_82541(struct e1000_hw *hw)
1105 {
1106 struct e1000_dev_spec_82541 *dev_spec = &hw->dev_spec._82541;
1107 u32 ret_val;
1108 u16 phy_saved_data;
1109
1110 DEBUGFUNC("e1000_phy_init_script_82541");
1111
1112 if (!dev_spec->phy_init_script) {
1113 ret_val = E1000_SUCCESS;
1114 goto out;
1115 }
1116
1117 /* Delay after phy reset to enable NVM configuration to load */
1118 msec_delay(20);
1119
1120 /*
1121 * Save off the current value of register 0x2F5B to be restored at
1122 * the end of this routine.
1123 */
1124 ret_val = hw->phy.ops.read_reg(hw, 0x2F5B, &phy_saved_data);
1125
1126 /* Disabled the PHY transmitter */
1127 hw->phy.ops.write_reg(hw, 0x2F5B, 0x0003);
1128
1129 msec_delay(20);
1130
1131 hw->phy.ops.write_reg(hw, 0x0000, 0x0140);
1132
1133 msec_delay(5);
1134
1135 switch (hw->mac.type) {
1136 case e1000_82541:
1137 case e1000_82547:
1138 hw->phy.ops.write_reg(hw, 0x1F95, 0x0001);
1139
1140 hw->phy.ops.write_reg(hw, 0x1F71, 0xBD21);
1141
1142 hw->phy.ops.write_reg(hw, 0x1F79, 0x0018);
1143
1144 hw->phy.ops.write_reg(hw, 0x1F30, 0x1600);
1145
1146 hw->phy.ops.write_reg(hw, 0x1F31, 0x0014);
1147
1148 hw->phy.ops.write_reg(hw, 0x1F32, 0x161C);
1149
1150 hw->phy.ops.write_reg(hw, 0x1F94, 0x0003);
1151
1152 hw->phy.ops.write_reg(hw, 0x1F96, 0x003F);
1153
1154 hw->phy.ops.write_reg(hw, 0x2010, 0x0008);
1155 break;
1156 case e1000_82541_rev_2:
1157 case e1000_82547_rev_2:
1158 hw->phy.ops.write_reg(hw, 0x1F73, 0x0099);
1159 break;
1160 default:
1161 break;
1162 }
1163
1164 hw->phy.ops.write_reg(hw, 0x0000, 0x3300);
1165
1166 msec_delay(20);
1167
1168 /* Now enable the transmitter */
1169 hw->phy.ops.write_reg(hw, 0x2F5B, phy_saved_data);
1170
1171 if (hw->mac.type == e1000_82547) {
1172 u16 fused, fine, coarse;
1173
1174 /* Move to analog registers page */
1175 hw->phy.ops.read_reg(hw,
1176 IGP01E1000_ANALOG_SPARE_FUSE_STATUS,
1177 &fused);
1178
1179 if (!(fused & IGP01E1000_ANALOG_SPARE_FUSE_ENABLED)) {
1180 hw->phy.ops.read_reg(hw,
1181 IGP01E1000_ANALOG_FUSE_STATUS,
1182 &fused);
1183
1184 fine = fused & IGP01E1000_ANALOG_FUSE_FINE_MASK;
1185 coarse = fused & IGP01E1000_ANALOG_FUSE_COARSE_MASK;
1186
1187 if (coarse > IGP01E1000_ANALOG_FUSE_COARSE_THRESH) {
1188 coarse -= IGP01E1000_ANALOG_FUSE_COARSE_10;
1189 fine -= IGP01E1000_ANALOG_FUSE_FINE_1;
1190 } else if (coarse ==
1191 IGP01E1000_ANALOG_FUSE_COARSE_THRESH)
1192 fine -= IGP01E1000_ANALOG_FUSE_FINE_10;
1193
1194 fused = (fused & IGP01E1000_ANALOG_FUSE_POLY_MASK) |
1195 (fine & IGP01E1000_ANALOG_FUSE_FINE_MASK) |
1196 (coarse & IGP01E1000_ANALOG_FUSE_COARSE_MASK);
1197
1198 hw->phy.ops.write_reg(hw,
1199 IGP01E1000_ANALOG_FUSE_CONTROL,
1200 fused);
1201 hw->phy.ops.write_reg(hw,
1202 IGP01E1000_ANALOG_FUSE_BYPASS,
1203 IGP01E1000_ANALOG_FUSE_ENABLE_SW_CONTROL);
1204 }
1205 }
1206
1207 out:
1208 return ret_val;
1209 }
1210
1211 /**
1212 * e1000_init_script_state_82541 - Enable/Disable PHY init script
1213 * @hw: pointer to the HW structure
1214 * @state: boolean value used to enable/disable PHY init script
1215 *
1216 * Allows the driver to enable/disable the PHY init script, if the PHY is an
1217 * IGP PHY.
1218 **/
1219 void e1000_init_script_state_82541(struct e1000_hw *hw, bool state)
1220 {
1221 struct e1000_dev_spec_82541 *dev_spec = &hw->dev_spec._82541;
1222
1223 DEBUGFUNC("e1000_init_script_state_82541");
1224
1225 if (hw->phy.type != e1000_phy_igp) {
1226 DEBUGOUT("Initialization script not necessary.\n");
1227 goto out;
1228 }
1229
1230 dev_spec->phy_init_script = state;
1231
1232 out:
1233 return;
1234 }
1235
1236 /**
1237 * e1000_power_down_phy_copper_82541 - Remove link in case of PHY power down
1238 * @hw: pointer to the HW structure
1239 *
1240 * In the case of a PHY power down to save power, or to turn off link during a
1241 * driver unload, or wake on lan is not enabled, remove the link.
1242 **/
1243 static void e1000_power_down_phy_copper_82541(struct e1000_hw *hw)
1244 {
1245 /* If the management interface is not enabled, then power down */
1246 if (!(E1000_READ_REG(hw, E1000_MANC) & E1000_MANC_SMBUS_EN))
1247 e1000_power_down_phy_copper(hw);
1248
1249 return;
1250 }
1251
1252 /**
1253 * e1000_clear_hw_cntrs_82541 - Clear device specific hardware counters
1254 * @hw: pointer to the HW structure
1255 *
1256 * Clears the hardware counters by reading the counter registers.
1257 **/
1258 static void e1000_clear_hw_cntrs_82541(struct e1000_hw *hw)
1259 {
1260 DEBUGFUNC("e1000_clear_hw_cntrs_82541");
1261
1262 e1000_clear_hw_cntrs_base_generic(hw);
1263
1264 E1000_READ_REG(hw, E1000_PRC64);
1265 E1000_READ_REG(hw, E1000_PRC127);
1266 E1000_READ_REG(hw, E1000_PRC255);
1267 E1000_READ_REG(hw, E1000_PRC511);
1268 E1000_READ_REG(hw, E1000_PRC1023);
1269 E1000_READ_REG(hw, E1000_PRC1522);
1270 E1000_READ_REG(hw, E1000_PTC64);
1271 E1000_READ_REG(hw, E1000_PTC127);
1272 E1000_READ_REG(hw, E1000_PTC255);
1273 E1000_READ_REG(hw, E1000_PTC511);
1274 E1000_READ_REG(hw, E1000_PTC1023);
1275 E1000_READ_REG(hw, E1000_PTC1522);
1276
1277 E1000_READ_REG(hw, E1000_ALGNERRC);
1278 E1000_READ_REG(hw, E1000_RXERRC);
1279 E1000_READ_REG(hw, E1000_TNCRS);
1280 E1000_READ_REG(hw, E1000_CEXTERR);
1281 E1000_READ_REG(hw, E1000_TSCTC);
1282 E1000_READ_REG(hw, E1000_TSCTFC);
1283
1284 E1000_READ_REG(hw, E1000_MGTPRC);
1285 E1000_READ_REG(hw, E1000_MGTPDC);
1286 E1000_READ_REG(hw, E1000_MGTPTC);
1287 }
Mirror of AROS' svn.