workbench/devs/networks/e1000/e1000_hw.h

   1 /*******************************************************************************
   2
   3   Intel PRO/1000 Linux driver
   4   Copyright(c) 1999 - 2010 Intel Corporation.
   5
   6   This program is free software; you can redistribute it and/or modify it
   7   under the terms and conditions of the GNU General Public License,
   8   version 2, as published by the Free Software Foundation.
   9
  10   This program is distributed in the hope it will be useful, but WITHOUT
  11   ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
  12   FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License for
  13   more details.
  14
  15   You should have received a copy of the GNU General Public License along with
  16   this program; if not, write to the Free Software Foundation, Inc.,
  17   51 Franklin St - Fifth Floor, Boston, MA 02110-1301 USA.
  18
  19   The full GNU General Public License is included in this distribution in
  20   the file called "COPYING".
  21
  22   Contact Information:
  23   Linux NICS <linux.nics@intel.com>
  24   e1000-devel Mailing List <e1000-devel@lists.sourceforge.net>
  25   Intel Corporation, 5200 N.E. Elam Young Parkway, Hillsboro, OR 97124-6497
  26
  27 *******************************************************************************/
  28
  29 #ifndef _E1000_HW_H_
  30 #define _E1000_HW_H_
  31
  32 #include "e1000_osdep.h"
  33 #include "e1000_regs.h"
  34 #include "e1000_defines.h"
  35
  36 struct e1000_hw;
  37
  38 #define E1000_DEV_ID_82542                    0x1000
  39 #define E1000_DEV_ID_82543GC_FIBER            0x1001
  40 #define E1000_DEV_ID_82543GC_COPPER           0x1004
  41 #define E1000_DEV_ID_82544EI_COPPER           0x1008
  42 #define E1000_DEV_ID_82544EI_FIBER            0x1009
  43 #define E1000_DEV_ID_82544GC_COPPER           0x100C
  44 #define E1000_DEV_ID_82544GC_LOM              0x100D
  45 #define E1000_DEV_ID_82540EM                  0x100E
  46 #define E1000_DEV_ID_82540EM_LOM              0x1015
  47 #define E1000_DEV_ID_82540EP_LOM              0x1016
  48 #define E1000_DEV_ID_82540EP                  0x1017
  49 #define E1000_DEV_ID_82540EP_LP               0x101E
  50 #define E1000_DEV_ID_82545EM_COPPER           0x100F
  51 #define E1000_DEV_ID_82545EM_FIBER            0x1011
  52 #define E1000_DEV_ID_82545GM_COPPER           0x1026
  53 #define E1000_DEV_ID_82545GM_FIBER            0x1027
  54 #define E1000_DEV_ID_82545GM_SERDES           0x1028
  55 #define E1000_DEV_ID_82546EB_COPPER           0x1010
  56 #define E1000_DEV_ID_82546EB_FIBER            0x1012
  57 #define E1000_DEV_ID_82546EB_QUAD_COPPER      0x101D
  58 #define E1000_DEV_ID_82546GB_COPPER           0x1079
  59 #define E1000_DEV_ID_82546GB_FIBER            0x107A
  60 #define E1000_DEV_ID_82546GB_SERDES           0x107B
  61 #define E1000_DEV_ID_82546GB_PCIE             0x108A
  62 #define E1000_DEV_ID_82546GB_QUAD_COPPER      0x1099
  63 #define E1000_DEV_ID_82546GB_QUAD_COPPER_KSP3 0x10B5
  64 #define E1000_DEV_ID_82541EI                  0x1013
  65 #define E1000_DEV_ID_82541EI_MOBILE           0x1018
  66 #define E1000_DEV_ID_82541ER_LOM              0x1014
  67 #define E1000_DEV_ID_82541ER                  0x1078
  68 #define E1000_DEV_ID_82541GI                  0x1076
  69 #define E1000_DEV_ID_82541GI_LF               0x107C
  70 #define E1000_DEV_ID_82541GI_MOBILE           0x1077
  71 #define E1000_DEV_ID_82547EI                  0x1019
  72 #define E1000_DEV_ID_82547EI_MOBILE           0x101A
  73 #define E1000_DEV_ID_82547GI                  0x1075
  74 #define E1000_REVISION_0 0
  75 #define E1000_REVISION_1 1
  76 #define E1000_REVISION_2 2
  77 #define E1000_REVISION_3 3
  78 #define E1000_REVISION_4 4
  79
  80 #define E1000_FUNC_0     0
  81 #define E1000_FUNC_1     1
  82
  83 #define E1000_ALT_MAC_ADDRESS_OFFSET_LAN0   0
  84 #define E1000_ALT_MAC_ADDRESS_OFFSET_LAN1   3
  85
  86 enum e1000_mac_type {
  87         e1000_undefined = 0,
  88         e1000_82542,
  89         e1000_82543,
  90         e1000_82544,
  91         e1000_82540,
  92         e1000_82545,
  93         e1000_82545_rev_3,
  94         e1000_82546,
  95         e1000_82546_rev_3,
  96         e1000_82541,
  97         e1000_82541_rev_2,
  98         e1000_82547,
  99         e1000_82547_rev_2,
 100         e1000_num_macs  /* List is 1-based, so subtract 1 for true count. */
 101 };
 102
 103 enum e1000_media_type {
 104         e1000_media_type_unknown = 0,
 105         e1000_media_type_copper = 1,
 106         e1000_media_type_fiber = 2,
 107         e1000_media_type_internal_serdes = 3,
 108         e1000_num_media_types
 109 };
 110
 111 enum e1000_nvm_type {
 112         e1000_nvm_unknown = 0,
 113         e1000_nvm_none,
 114         e1000_nvm_eeprom_spi,
 115         e1000_nvm_eeprom_microwire,
 116         e1000_nvm_flash_hw,
 117         e1000_nvm_flash_sw
 118 };
 119
 120 enum e1000_nvm_override {
 121         e1000_nvm_override_none = 0,
 122         e1000_nvm_override_spi_small,
 123         e1000_nvm_override_spi_large,
 124         e1000_nvm_override_microwire_small,
 125         e1000_nvm_override_microwire_large
 126 };
 127
 128 enum e1000_phy_type {
 129         e1000_phy_unknown = 0,
 130         e1000_phy_none,
 131         e1000_phy_m88,
 132         e1000_phy_igp,
 133         e1000_phy_igp_2,
 134         e1000_phy_gg82563,
 135         e1000_phy_igp_3,
 136         e1000_phy_ife,
 137 };
 138
 139 enum e1000_bus_type {
 140         e1000_bus_type_unknown = 0,
 141         e1000_bus_type_pci,
 142         e1000_bus_type_pcix,
 143         e1000_bus_type_pci_express,
 144         e1000_bus_type_reserved
 145 };
 146
 147 enum e1000_bus_speed {
 148         e1000_bus_speed_unknown = 0,
 149         e1000_bus_speed_33,
 150         e1000_bus_speed_66,
 151         e1000_bus_speed_100,
 152         e1000_bus_speed_120,
 153         e1000_bus_speed_133,
 154         e1000_bus_speed_2500,
 155         e1000_bus_speed_5000,
 156         e1000_bus_speed_reserved
 157 };
 158
 159 enum e1000_bus_width {
 160         e1000_bus_width_unknown = 0,
 161         e1000_bus_width_pcie_x1,
 162         e1000_bus_width_pcie_x2,
 163         e1000_bus_width_pcie_x4 = 4,
 164         e1000_bus_width_pcie_x8 = 8,
 165         e1000_bus_width_32,
 166         e1000_bus_width_64,
 167         e1000_bus_width_reserved
 168 };
 169
 170 enum e1000_1000t_rx_status {
 171         e1000_1000t_rx_status_not_ok = 0,
 172         e1000_1000t_rx_status_ok,
 173         e1000_1000t_rx_status_undefined = 0xFF
 174 };
 175
 176 enum e1000_rev_polarity {
 177         e1000_rev_polarity_normal = 0,
 178         e1000_rev_polarity_reversed,
 179         e1000_rev_polarity_undefined = 0xFF
 180 };
 181
 182 enum e1000_fc_mode {
 183         e1000_fc_none = 0,
 184         e1000_fc_rx_pause,
 185         e1000_fc_tx_pause,
 186         e1000_fc_full,
 187         e1000_fc_default = 0xFF
 188 };
 189
 190 enum e1000_ffe_config {
 191         e1000_ffe_config_enabled = 0,
 192         e1000_ffe_config_active,
 193         e1000_ffe_config_blocked
 194 };
 195
 196 enum e1000_dsp_config {
 197         e1000_dsp_config_disabled = 0,
 198         e1000_dsp_config_enabled,
 199         e1000_dsp_config_activated,
 200         e1000_dsp_config_undefined = 0xFF
 201 };
 202
 203 enum e1000_ms_type {
 204         e1000_ms_hw_default = 0,
 205         e1000_ms_force_master,
 206         e1000_ms_force_slave,
 207         e1000_ms_auto
 208 };
 209
 210 enum e1000_smart_speed {
 211         e1000_smart_speed_default = 0,
 212         e1000_smart_speed_on,
 213         e1000_smart_speed_off
 214 };
 215
 216 enum e1000_serdes_link_state {
 217         e1000_serdes_link_down = 0,
 218         e1000_serdes_link_autoneg_progress,
 219         e1000_serdes_link_autoneg_complete,
 220         e1000_serdes_link_forced_up
 221 };
 222
 223 #ifndef __le16
 224 #define __le16 u16
 225 #endif
 226 #ifndef __le32
 227 #define __le32 u32
 228 #endif
 229 #ifndef __le64
 230 #define __le64 u64
 231 #endif
 232 /* Receive Descriptor */
 233 struct e1000_rx_desc {
 234         __le64 buffer_addr; /* Address of the descriptor's data buffer */
 235         __le16 length;      /* Length of data DMAed into data buffer */
 236         __le16 csum;        /* Packet checksum */
 237         u8  status;         /* Descriptor status */
 238         u8  errors;         /* Descriptor Errors */
 239         __le16 special;
 240 };
 241
 242 /* Receive Descriptor - Extended */
 243 union e1000_rx_desc_extended {
 244         struct {
 245                 __le64 buffer_addr;
 246                 __le64 reserved;
 247         } read;
 248         struct {
 249                 struct {
 250                         __le32 mrq;           /* Multiple Rx Queues */
 251                         union {
 252                                 __le32 rss;         /* RSS Hash */
 253                                 struct {
 254                                         __le16 ip_id;  /* IP id */
 255                                         __le16 csum;   /* Packet Checksum */
 256                                 } csum_ip;
 257                         } hi_dword;
 258                 } lower;
 259                 struct {
 260                         __le32 status_error;  /* ext status/error */
 261                         __le16 length;
 262                         __le16 vlan;          /* VLAN tag */
 263                 } upper;
 264         } wb;  /* writeback */
 265 };
 266
 267 #define MAX_PS_BUFFERS 4
 268 /* Receive Descriptor - Packet Split */
 269 union e1000_rx_desc_packet_split {
 270         struct {
 271                 /* one buffer for protocol header(s), three data buffers */
 272                 __le64 buffer_addr[MAX_PS_BUFFERS];
 273         } read;
 274         struct {
 275                 struct {
 276                         __le32 mrq;           /* Multiple Rx Queues */
 277                         union {
 278                                 __le32 rss;           /* RSS Hash */
 279                                 struct {
 280                                         __le16 ip_id;    /* IP id */
 281                                         __le16 csum;     /* Packet Checksum */
 282                                 } csum_ip;
 283                         } hi_dword;
 284                 } lower;
 285                 struct {
 286                         __le32 status_error;  /* ext status/error */
 287                         __le16 length0;       /* length of buffer 0 */
 288                         __le16 vlan;          /* VLAN tag */
 289                 } middle;
 290                 struct {
 291                         __le16 header_status;
 292                         __le16 length[3];     /* length of buffers 1-3 */
 293                 } upper;
 294                 __le64 reserved;
 295         } wb; /* writeback */
 296 };
 297
 298 /* Transmit Descriptor */
 299 struct e1000_tx_desc {
 300         __le64 buffer_addr;   /* Address of the descriptor's data buffer */
 301         union {
 302                 __le32 data;
 303                 struct {
 304                         __le16 length;    /* Data buffer length */
 305                         u8 cso;           /* Checksum offset */
 306                         u8 cmd;           /* Descriptor control */
 307                 } flags;
 308         } lower;
 309         union {
 310                 __le32 data;
 311                 struct {
 312                         u8 status;        /* Descriptor status */
 313                         u8 css;           /* Checksum start */
 314                         __le16 special;
 315                 } fields;
 316         } upper;
 317 };
 318
 319 /* Offload Context Descriptor */
 320 struct e1000_context_desc {
 321         union {
 322                 __le32 ip_config;
 323                 struct {
 324                         u8 ipcss;         /* IP checksum start */
 325                         u8 ipcso;         /* IP checksum offset */
 326                         __le16 ipcse;     /* IP checksum end */
 327                 } ip_fields;
 328         } lower_setup;
 329         union {
 330                 __le32 tcp_config;
 331                 struct {
 332                         u8 tucss;         /* TCP checksum start */
 333                         u8 tucso;         /* TCP checksum offset */
 334                         __le16 tucse;     /* TCP checksum end */
 335                 } tcp_fields;
 336         } upper_setup;
 337         __le32 cmd_and_length;
 338         union {
 339                 __le32 data;
 340                 struct {
 341                         u8 status;        /* Descriptor status */
 342                         u8 hdr_len;       /* Header length */
 343                         __le16 mss;       /* Maximum segment size */
 344                 } fields;
 345         } tcp_seg_setup;
 346 };
 347
 348 /* Offload data descriptor */
 349 struct e1000_data_desc {
 350         __le64 buffer_addr;   /* Address of the descriptor's buffer address */
 351         union {
 352                 __le32 data;
 353                 struct {
 354                         __le16 length;    /* Data buffer length */
 355                         u8 typ_len_ext;
 356                         u8 cmd;
 357                 } flags;
 358         } lower;
 359         union {
 360                 __le32 data;
 361                 struct {
 362                         u8 status;        /* Descriptor status */
 363                         u8 popts;         /* Packet Options */
 364                         __le16 special;
 365                 } fields;
 366         } upper;
 367 };
 368
 369 /* Statistics counters collected by the MAC */
 370 struct e1000_hw_stats {
 371         u64 crcerrs;
 372         u64 algnerrc;
 373         u64 symerrs;
 374         u64 rxerrc;
 375         u64 mpc;
 376         u64 scc;
 377         u64 ecol;
 378         u64 mcc;
 379         u64 latecol;
 380         u64 colc;
 381         u64 dc;
 382         u64 tncrs;
 383         u64 sec;
 384         u64 cexterr;
 385         u64 rlec;
 386         u64 xonrxc;
 387         u64 xontxc;
 388         u64 xoffrxc;
 389         u64 xofftxc;
 390         u64 fcruc;
 391         u64 prc64;
 392         u64 prc127;
 393         u64 prc255;
 394         u64 prc511;
 395         u64 prc1023;
 396         u64 prc1522;
 397         u64 gprc;
 398         u64 bprc;
 399         u64 mprc;
 400         u64 gptc;
 401         u64 gorc;
 402         u64 gotc;
 403         u64 rnbc;
 404         u64 ruc;
 405         u64 rfc;
 406         u64 roc;
 407         u64 rjc;
 408         u64 mgprc;
 409         u64 mgpdc;
 410         u64 mgptc;
 411         u64 tor;
 412         u64 tot;
 413         u64 tpr;
 414         u64 tpt;
 415         u64 ptc64;
 416         u64 ptc127;
 417         u64 ptc255;
 418         u64 ptc511;
 419         u64 ptc1023;
 420         u64 ptc1522;
 421         u64 mptc;
 422         u64 bptc;
 423         u64 tsctc;
 424         u64 tsctfc;
 425         u64 iac;
 426         u64 icrxptc;
 427         u64 icrxatc;
 428         u64 ictxptc;
 429         u64 ictxatc;
 430         u64 ictxqec;
 431         u64 ictxqmtc;
 432         u64 icrxdmtc;
 433         u64 icrxoc;
 434         u64 cbtmpc;
 435         u64 htdpmc;
 436         u64 cbrdpc;
 437         u64 cbrmpc;
 438         u64 rpthc;
 439         u64 hgptc;
 440         u64 htcbdpc;
 441         u64 hgorc;
 442         u64 hgotc;
 443         u64 lenerrs;
 444         u64 scvpc;
 445         u64 hrmpc;
 446         u64 doosync;
 447 };
 448
 449
 450 struct e1000_phy_stats {
 451         u32 idle_errors;
 452         u32 receive_errors;
 453 };
 454
 455 struct e1000_host_mng_dhcp_cookie {
 456         u32 signature;
 457         u8  status;
 458         u8  reserved0;
 459         u16 vlan_id;
 460         u32 reserved1;
 461         u16 reserved2;
 462         u8  reserved3;
 463         u8  checksum;
 464 };
 465
 466 /* Host Interface "Rev 1" */
 467 struct e1000_host_command_header {
 468         u8 command_id;
 469         u8 command_length;
 470         u8 command_options;
 471         u8 checksum;
 472 };
 473
 474 #define E1000_HI_MAX_DATA_LENGTH     252
 475 struct e1000_host_command_info {
 476         struct e1000_host_command_header command_header;
 477         u8 command_data[E1000_HI_MAX_DATA_LENGTH];
 478 };
 479
 480 /* Host Interface "Rev 2" */
 481 struct e1000_host_mng_command_header {
 482         u8  command_id;
 483         u8  checksum;
 484         u16 reserved1;
 485         u16 reserved2;
 486         u16 command_length;
 487 };
 488
 489 #define E1000_HI_MAX_MNG_DATA_LENGTH 0x6F8
 490 struct e1000_host_mng_command_info {
 491         struct e1000_host_mng_command_header command_header;
 492         u8 command_data[E1000_HI_MAX_MNG_DATA_LENGTH];
 493 };
 494
 495 #include "e1000_mac.h"
 496 #include "e1000_phy.h"
 497 #include "e1000_nvm.h"
 498 #include "e1000_manage.h"
 499
 500 struct e1000_mac_operations {
 501         /* Function pointers for the MAC. */
 502         s32  (*init_params)(struct e1000_hw *);
 503         s32  (*id_led_init)(struct e1000_hw *);
 504         s32  (*blink_led)(struct e1000_hw *);
 505         s32  (*check_for_link)(struct e1000_hw *);
 506         bool (*check_mng_mode)(struct e1000_hw *hw);
 507         s32  (*cleanup_led)(struct e1000_hw *);
 508         void (*clear_hw_cntrs)(struct e1000_hw *);
 509         void (*clear_vfta)(struct e1000_hw *);
 510         s32  (*get_bus_info)(struct e1000_hw *);
 511         void (*set_lan_id)(struct e1000_hw *);
 512         s32  (*get_link_up_info)(struct e1000_hw *, u16 *, u16 *);
 513         s32  (*led_on)(struct e1000_hw *);
 514         s32  (*led_off)(struct e1000_hw *);
 515         void (*update_mc_addr_list)(struct e1000_hw *, u8 *, u32);
 516         s32  (*reset_hw)(struct e1000_hw *);
 517         s32  (*init_hw)(struct e1000_hw *);
 518         s32  (*setup_link)(struct e1000_hw *);
 519         s32  (*setup_physical_interface)(struct e1000_hw *);
 520         s32  (*setup_led)(struct e1000_hw *);
 521         void (*write_vfta)(struct e1000_hw *, u32, u32);
 522         void (*config_collision_dist)(struct e1000_hw *);
 523         void (*rar_set)(struct e1000_hw *, u8*, u32);
 524         s32  (*read_mac_addr)(struct e1000_hw *);
 525         s32  (*validate_mdi_setting)(struct e1000_hw *);
 526         s32  (*mng_host_if_write)(struct e1000_hw *, u8*, u16, u16, u8*);
 527         s32  (*mng_write_cmd_header)(struct e1000_hw *hw,
 528                       struct e1000_host_mng_command_header*);
 529         s32  (*mng_enable_host_if)(struct e1000_hw *);
 530         s32  (*wait_autoneg)(struct e1000_hw *);
 531 };
 532
 533 /*
 534  * When to use various PHY register access functions:
 535  *
 536  *                 Func   Caller
 537  *   Function      Does   Does    When to use
 538  *   ~~~~~~~~~~~~  ~~~~~  ~~~~~~  ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
 539  *   X_reg         L,P,A  n/a     for simple PHY reg accesses
 540  *   X_reg_locked  P,A    L       for multiple accesses of different regs
 541  *                                on different pages
 542  *   X_reg_page    A      L,P     for multiple accesses of different regs
 543  *                                on the same page
 544  *
 545  * Where X=[read|write], L=locking, P=sets page, A=register access
 546  *
 547  */
 548 struct e1000_phy_operations {
 549         s32  (*init_params)(struct e1000_hw *);
 550         s32  (*acquire)(struct e1000_hw *);
 551         s32  (*check_polarity)(struct e1000_hw *);
 552         s32  (*check_reset_block)(struct e1000_hw *);
 553         s32  (*commit)(struct e1000_hw *);
 554         s32  (*force_speed_duplex)(struct e1000_hw *);
 555         s32  (*get_cfg_done)(struct e1000_hw *hw);
 556         s32  (*get_cable_length)(struct e1000_hw *);
 557         s32  (*get_info)(struct e1000_hw *);
 558         s32  (*set_page)(struct e1000_hw *, u16);
 559         s32  (*read_reg)(struct e1000_hw *, u32, u16 *);
 560         s32  (*read_reg_locked)(struct e1000_hw *, u32, u16 *);
 561         s32  (*read_reg_page)(struct e1000_hw *, u32, u16 *);
 562         void (*release)(struct e1000_hw *);
 563         s32  (*reset)(struct e1000_hw *);
 564         s32  (*set_d0_lplu_state)(struct e1000_hw *, bool);
 565         s32  (*set_d3_lplu_state)(struct e1000_hw *, bool);
 566         s32  (*write_reg)(struct e1000_hw *, u32, u16);
 567         s32  (*write_reg_locked)(struct e1000_hw *, u32, u16);
 568         s32  (*write_reg_page)(struct e1000_hw *, u32, u16);
 569         void (*power_up)(struct e1000_hw *);
 570         void (*power_down)(struct e1000_hw *);
 571 };
 572
 573 struct e1000_nvm_operations {
 574         s32  (*init_params)(struct e1000_hw *);
 575         s32  (*acquire)(struct e1000_hw *);
 576         s32  (*read)(struct e1000_hw *, u16, u16, u16 *);
 577         void (*release)(struct e1000_hw *);
 578         void (*reload)(struct e1000_hw *);
 579         s32  (*update)(struct e1000_hw *);
 580         s32  (*valid_led_default)(struct e1000_hw *, u16 *);
 581         s32  (*validate)(struct e1000_hw *);
 582         s32  (*write)(struct e1000_hw *, u16, u16, u16 *);
 583 };
 584
 585 struct e1000_mac_info {
 586         struct e1000_mac_operations ops;
 587         u8 addr[ETH_ADDR_LEN];
 588         u8 perm_addr[ETH_ADDR_LEN];
 589
 590         enum e1000_mac_type type;
 591
 592         u32 collision_delta;
 593         u32 ledctl_default;
 594         u32 ledctl_mode1;
 595         u32 ledctl_mode2;
 596         u32 mc_filter_type;
 597         u32 tx_packet_delta;
 598         u32 txcw;
 599
 600         u16 current_ifs_val;
 601         u16 ifs_max_val;
 602         u16 ifs_min_val;
 603         u16 ifs_ratio;
 604         u16 ifs_step_size;
 605         u16 mta_reg_count;
 606
 607         /* Maximum size of the MTA register table in all supported adapters */
 608         #define MAX_MTA_REG 128
 609         u32 mta_shadow[MAX_MTA_REG];
 610         u16 rar_entry_count;
 611
 612         u8  forced_speed_duplex;
 613
 614         bool adaptive_ifs;
 615         bool has_fwsm;
 616         bool arc_subsystem_valid;
 617         bool asf_firmware_present;
 618         bool autoneg;
 619         bool autoneg_failed;
 620         bool get_link_status;
 621         bool in_ifs_mode;
 622         bool report_tx_early;
 623         enum e1000_serdes_link_state serdes_link_state;
 624         bool serdes_has_link;
 625         bool tx_pkt_filtering;
 626 };
 627
 628 struct e1000_phy_info {
 629         struct e1000_phy_operations ops;
 630         enum e1000_phy_type type;
 631
 632         enum e1000_1000t_rx_status local_rx;
 633         enum e1000_1000t_rx_status remote_rx;
 634         enum e1000_ms_type ms_type;
 635         enum e1000_ms_type original_ms_type;
 636         enum e1000_rev_polarity cable_polarity;
 637         enum e1000_smart_speed smart_speed;
 638
 639         u32 addr;
 640         u32 id;
 641         u32 reset_delay_us; /* in usec */
 642         u32 revision;
 643
 644         enum e1000_media_type media_type;
 645
 646         u16 autoneg_advertised;
 647         u16 autoneg_mask;
 648         u16 cable_length;
 649         u16 max_cable_length;
 650         u16 min_cable_length;
 651
 652         u8 mdix;
 653
 654         bool disable_polarity_correction;
 655         bool is_mdix;
 656         bool polarity_correction;
 657         bool reset_disable;
 658         bool speed_downgraded;
 659         bool autoneg_wait_to_complete;
 660 };
 661
 662 struct e1000_nvm_info {
 663         struct e1000_nvm_operations ops;
 664         enum e1000_nvm_type type;
 665         enum e1000_nvm_override override;
 666
 667         u32 flash_bank_size;
 668         u32 flash_base_addr;
 669
 670         u16 word_size;
 671         u16 delay_usec;
 672         u16 address_bits;
 673         u16 opcode_bits;
 674         u16 page_size;
 675 };
 676
 677 struct e1000_bus_info {
 678         enum e1000_bus_type type;
 679         enum e1000_bus_speed speed;
 680         enum e1000_bus_width width;
 681
 682         u16 func;
 683         u16 pci_cmd_word;
 684 };
 685
 686 struct e1000_fc_info {
 687         u32 high_water;          /* Flow control high-water mark */
 688         u32 low_water;           /* Flow control low-water mark */
 689         u16 pause_time;          /* Flow control pause timer */
 690         u16 refresh_time;        /* Flow control refresh timer */
 691         bool send_xon;           /* Flow control send XON */
 692         bool strict_ieee;        /* Strict IEEE mode */
 693         enum e1000_fc_mode current_mode; /* FC mode in effect */
 694         enum e1000_fc_mode requested_mode; /* FC mode requested by caller */
 695 };
 696
 697 struct e1000_dev_spec_82541 {
 698         enum e1000_dsp_config dsp_config;
 699         enum e1000_ffe_config ffe_config;
 700         u16 spd_default;
 701         bool phy_init_script;
 702 };
 703
 704 struct e1000_dev_spec_82542 {
 705         bool dma_fairness;
 706 };
 707
 708 struct e1000_dev_spec_82543 {
 709         u32  tbi_compatibility;
 710         bool dma_fairness;
 711         bool init_phy_disabled;
 712 };
 713
 714 struct e1000_hw {
 715         void *back;
 716
 717         u8 __iomem *hw_addr;
 718         u8 __iomem *flash_address;
 719         unsigned long io_base;
 720
 721         struct e1000_mac_info  mac;
 722         struct e1000_fc_info   fc;
 723         struct e1000_phy_info  phy;
 724         struct e1000_nvm_info  nvm;
 725         struct e1000_bus_info  bus;
 726         struct e1000_host_mng_dhcp_cookie mng_cookie;
 727
 728         union {
 729                 struct e1000_dev_spec_82541 _82541;
 730                 struct e1000_dev_spec_82542 _82542;
 731                 struct e1000_dev_spec_82543 _82543;
 732         } dev_spec;
 733
 734         u16 device_id;
 735         u16 subsystem_vendor_id;
 736         u16 subsystem_device_id;
 737         u16 vendor_id;
 738
 739         u8  revision_id;
 740 };
 741
 742 #include "e1000_82541.h"
 743 #include "e1000_82543.h"
 744
 745 /* These functions must be implemented by drivers */
 746 void e1000_pci_clear_mwi(struct e1000_hw *hw);
 747 void e1000_pci_set_mwi(struct e1000_hw *hw);
 748 s32  e1000_read_pcie_cap_reg(struct e1000_hw *hw, u32 reg, u16 *value);
 749 void e1000_read_pci_cfg(struct e1000_hw *hw, u32 reg, u16 *value);
 750 void e1000_write_pci_cfg(struct e1000_hw *hw, u32 reg, u16 *value);
 751
 752 #endif