revert between 56095 -> 55830 in arch
[AROS.git] / workbench / devs / networks / e1000 / e1000_nvm.c
blobd7faf433abef8b05ff18e67b535528070c12fd81
1 /*******************************************************************************
3 Intel PRO/1000 Linux driver
4 Copyright(c) 1999 - 2010 Intel Corporation.
6 This program is free software; you can redistribute it and/or modify it
7 under the terms and conditions of the GNU General Public License,
8 version 2, as published by the Free Software Foundation.
10 This program is distributed in the hope it will be useful, but WITHOUT
11 ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
12 FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
13 more details.
15 You should have received a copy of the GNU General Public License along with
16 this program; if not, write to the Free Software Foundation, Inc.,
17 51 Franklin St - Fifth Floor, Boston, MA 02110-1301 USA.
19 The full GNU General Public License is included in this distribution in
20 the file called "COPYING".
22 Contact Information:
23 Linux NICS <linux.nics@intel.com>
24 e1000-devel Mailing List <e1000-devel@lists.sourceforge.net>
25 Intel Corporation, 5200 N.E. Elam Young Parkway, Hillsboro, OR 97124-6497
27 *******************************************************************************/
29 #include "e1000_api.h"
31 static void e1000_reload_nvm_generic(struct e1000_hw *hw);
33 /**
34 * e1000_init_nvm_ops_generic - Initialize NVM function pointers
35 * @hw: pointer to the HW structure
37 * Setups up the function pointers to no-op functions
38 **/
39 void e1000_init_nvm_ops_generic(struct e1000_hw *hw)
41 struct e1000_nvm_info *nvm = &hw->nvm;
42 DEBUGFUNC("e1000_init_nvm_ops_generic");
44 /* Initialize function pointers */
45 nvm->ops.init_params = e1000_null_ops_generic;
46 nvm->ops.acquire = e1000_null_ops_generic;
47 nvm->ops.read = e1000_null_read_nvm;
48 nvm->ops.release = e1000_null_nvm_generic;
49 nvm->ops.reload = e1000_reload_nvm_generic;
50 nvm->ops.update = e1000_null_ops_generic;
51 nvm->ops.valid_led_default = e1000_null_led_default;
52 nvm->ops.validate = e1000_null_ops_generic;
53 nvm->ops.write = e1000_null_write_nvm;
56 /**
57 * e1000_null_nvm_read - No-op function, return 0
58 * @hw: pointer to the HW structure
59 **/
60 s32 e1000_null_read_nvm(struct e1000_hw *hw, u16 a, u16 b, u16 *c)
62 DEBUGFUNC("e1000_null_read_nvm");
63 return E1000_SUCCESS;
66 /**
67 * e1000_null_nvm_generic - No-op function, return void
68 * @hw: pointer to the HW structure
69 **/
70 void e1000_null_nvm_generic(struct e1000_hw *hw)
72 DEBUGFUNC("e1000_null_nvm_generic");
73 return;
76 /**
77 * e1000_null_led_default - No-op function, return 0
78 * @hw: pointer to the HW structure
79 **/
80 s32 e1000_null_led_default(struct e1000_hw *hw, u16 *data)
82 DEBUGFUNC("e1000_null_led_default");
83 return E1000_SUCCESS;
86 /**
87 * e1000_null_write_nvm - No-op function, return 0
88 * @hw: pointer to the HW structure
89 **/
90 s32 e1000_null_write_nvm(struct e1000_hw *hw, u16 a, u16 b, u16 *c)
92 DEBUGFUNC("e1000_null_write_nvm");
93 return E1000_SUCCESS;
96 /**
97 * e1000_raise_eec_clk - Raise EEPROM clock
98 * @hw: pointer to the HW structure
99 * @eecd: pointer to the EEPROM
101 * Enable/Raise the EEPROM clock bit.
103 static void e1000_raise_eec_clk(struct e1000_hw *hw, u32 *eecd)
105 *eecd = *eecd | E1000_EECD_SK;
106 E1000_WRITE_REG(hw, E1000_EECD, *eecd);
107 E1000_WRITE_FLUSH(hw);
108 usec_delay(hw->nvm.delay_usec);
112 * e1000_lower_eec_clk - Lower EEPROM clock
113 * @hw: pointer to the HW structure
114 * @eecd: pointer to the EEPROM
116 * Clear/Lower the EEPROM clock bit.
118 static void e1000_lower_eec_clk(struct e1000_hw *hw, u32 *eecd)
120 *eecd = *eecd & ~E1000_EECD_SK;
121 E1000_WRITE_REG(hw, E1000_EECD, *eecd);
122 E1000_WRITE_FLUSH(hw);
123 usec_delay(hw->nvm.delay_usec);
127 * e1000_shift_out_eec_bits - Shift data bits our to the EEPROM
128 * @hw: pointer to the HW structure
129 * @data: data to send to the EEPROM
130 * @count: number of bits to shift out
132 * We need to shift 'count' bits out to the EEPROM. So, the value in the
133 * "data" parameter will be shifted out to the EEPROM one bit at a time.
134 * In order to do this, "data" must be broken down into bits.
136 static void e1000_shift_out_eec_bits(struct e1000_hw *hw, u16 data, u16 count)
138 struct e1000_nvm_info *nvm = &hw->nvm;
139 u32 eecd = E1000_READ_REG(hw, E1000_EECD);
140 u32 mask;
142 DEBUGFUNC("e1000_shift_out_eec_bits");
144 mask = 0x01 << (count - 1);
145 if (nvm->type == e1000_nvm_eeprom_microwire)
146 eecd &= ~E1000_EECD_DO;
147 else
148 if (nvm->type == e1000_nvm_eeprom_spi)
149 eecd |= E1000_EECD_DO;
151 do {
152 eecd &= ~E1000_EECD_DI;
154 if (data & mask)
155 eecd |= E1000_EECD_DI;
157 E1000_WRITE_REG(hw, E1000_EECD, eecd);
158 E1000_WRITE_FLUSH(hw);
160 usec_delay(nvm->delay_usec);
162 e1000_raise_eec_clk(hw, &eecd);
163 e1000_lower_eec_clk(hw, &eecd);
165 mask >>= 1;
166 } while (mask);
168 eecd &= ~E1000_EECD_DI;
169 E1000_WRITE_REG(hw, E1000_EECD, eecd);
173 * e1000_shift_in_eec_bits - Shift data bits in from the EEPROM
174 * @hw: pointer to the HW structure
175 * @count: number of bits to shift in
177 * In order to read a register from the EEPROM, we need to shift 'count' bits
178 * in from the EEPROM. Bits are "shifted in" by raising the clock input to
179 * the EEPROM (setting the SK bit), and then reading the value of the data out
180 * "DO" bit. During this "shifting in" process the data in "DI" bit should
181 * always be clear.
183 static u16 e1000_shift_in_eec_bits(struct e1000_hw *hw, u16 count)
185 u32 eecd;
186 u32 i;
187 u16 data;
189 DEBUGFUNC("e1000_shift_in_eec_bits");
191 eecd = E1000_READ_REG(hw, E1000_EECD);
193 eecd &= ~(E1000_EECD_DO | E1000_EECD_DI);
194 data = 0;
196 for (i = 0; i < count; i++) {
197 data <<= 1;
198 e1000_raise_eec_clk(hw, &eecd);
200 eecd = E1000_READ_REG(hw, E1000_EECD);
202 eecd &= ~E1000_EECD_DI;
203 if (eecd & E1000_EECD_DO)
204 data |= 1;
206 e1000_lower_eec_clk(hw, &eecd);
209 return data;
213 * e1000_poll_eerd_eewr_done - Poll for EEPROM read/write completion
214 * @hw: pointer to the HW structure
215 * @ee_reg: EEPROM flag for polling
217 * Polls the EEPROM status bit for either read or write completion based
218 * upon the value of 'ee_reg'.
220 s32 e1000_poll_eerd_eewr_done(struct e1000_hw *hw, int ee_reg)
222 u32 attempts = 100000;
223 u32 i, reg = 0;
224 s32 ret_val = -E1000_ERR_NVM;
226 DEBUGFUNC("e1000_poll_eerd_eewr_done");
228 for (i = 0; i < attempts; i++) {
229 if (ee_reg == E1000_NVM_POLL_READ)
230 reg = E1000_READ_REG(hw, E1000_EERD);
231 else
232 reg = E1000_READ_REG(hw, E1000_EEWR);
234 if (reg & E1000_NVM_RW_REG_DONE) {
235 ret_val = E1000_SUCCESS;
236 break;
239 usec_delay(5);
242 return ret_val;
246 * e1000_acquire_nvm_generic - Generic request for access to EEPROM
247 * @hw: pointer to the HW structure
249 * Set the EEPROM access request bit and wait for EEPROM access grant bit.
250 * Return successful if access grant bit set, else clear the request for
251 * EEPROM access and return -E1000_ERR_NVM (-1).
253 s32 e1000_acquire_nvm_generic(struct e1000_hw *hw)
255 u32 eecd = E1000_READ_REG(hw, E1000_EECD);
256 s32 timeout = E1000_NVM_GRANT_ATTEMPTS;
257 s32 ret_val = E1000_SUCCESS;
259 DEBUGFUNC("e1000_acquire_nvm_generic");
261 E1000_WRITE_REG(hw, E1000_EECD, eecd | E1000_EECD_REQ);
262 eecd = E1000_READ_REG(hw, E1000_EECD);
264 while (timeout) {
265 if (eecd & E1000_EECD_GNT)
266 break;
267 usec_delay(5);
268 eecd = E1000_READ_REG(hw, E1000_EECD);
269 timeout--;
272 if (!timeout) {
273 eecd &= ~E1000_EECD_REQ;
274 E1000_WRITE_REG(hw, E1000_EECD, eecd);
275 DEBUGOUT("Could not acquire NVM grant\n");
276 ret_val = -E1000_ERR_NVM;
279 return ret_val;
283 * e1000_standby_nvm - Return EEPROM to standby state
284 * @hw: pointer to the HW structure
286 * Return the EEPROM to a standby state.
288 static void e1000_standby_nvm(struct e1000_hw *hw)
290 struct e1000_nvm_info *nvm = &hw->nvm;
291 u32 eecd = E1000_READ_REG(hw, E1000_EECD);
293 DEBUGFUNC("e1000_standby_nvm");
295 if (nvm->type == e1000_nvm_eeprom_microwire) {
296 eecd &= ~(E1000_EECD_CS | E1000_EECD_SK);
297 E1000_WRITE_REG(hw, E1000_EECD, eecd);
298 E1000_WRITE_FLUSH(hw);
299 usec_delay(nvm->delay_usec);
301 e1000_raise_eec_clk(hw, &eecd);
303 /* Select EEPROM */
304 eecd |= E1000_EECD_CS;
305 E1000_WRITE_REG(hw, E1000_EECD, eecd);
306 E1000_WRITE_FLUSH(hw);
307 usec_delay(nvm->delay_usec);
309 e1000_lower_eec_clk(hw, &eecd);
310 } else
311 if (nvm->type == e1000_nvm_eeprom_spi) {
312 /* Toggle CS to flush commands */
313 eecd |= E1000_EECD_CS;
314 E1000_WRITE_REG(hw, E1000_EECD, eecd);
315 E1000_WRITE_FLUSH(hw);
316 usec_delay(nvm->delay_usec);
317 eecd &= ~E1000_EECD_CS;
318 E1000_WRITE_REG(hw, E1000_EECD, eecd);
319 E1000_WRITE_FLUSH(hw);
320 usec_delay(nvm->delay_usec);
325 * e1000_stop_nvm - Terminate EEPROM command
326 * @hw: pointer to the HW structure
328 * Terminates the current command by inverting the EEPROM's chip select pin.
330 void e1000_stop_nvm(struct e1000_hw *hw)
332 u32 eecd;
334 DEBUGFUNC("e1000_stop_nvm");
336 eecd = E1000_READ_REG(hw, E1000_EECD);
337 if (hw->nvm.type == e1000_nvm_eeprom_spi) {
338 /* Pull CS high */
339 eecd |= E1000_EECD_CS;
340 e1000_lower_eec_clk(hw, &eecd);
341 } else if (hw->nvm.type == e1000_nvm_eeprom_microwire) {
342 /* CS on Microwire is active-high */
343 eecd &= ~(E1000_EECD_CS | E1000_EECD_DI);
344 E1000_WRITE_REG(hw, E1000_EECD, eecd);
345 e1000_raise_eec_clk(hw, &eecd);
346 e1000_lower_eec_clk(hw, &eecd);
351 * e1000_release_nvm_generic - Release exclusive access to EEPROM
352 * @hw: pointer to the HW structure
354 * Stop any current commands to the EEPROM and clear the EEPROM request bit.
356 void e1000_release_nvm_generic(struct e1000_hw *hw)
358 u32 eecd;
360 DEBUGFUNC("e1000_release_nvm_generic");
362 e1000_stop_nvm(hw);
364 eecd = E1000_READ_REG(hw, E1000_EECD);
365 eecd &= ~E1000_EECD_REQ;
366 E1000_WRITE_REG(hw, E1000_EECD, eecd);
370 * e1000_ready_nvm_eeprom - Prepares EEPROM for read/write
371 * @hw: pointer to the HW structure
373 * Setups the EEPROM for reading and writing.
375 static s32 e1000_ready_nvm_eeprom(struct e1000_hw *hw)
377 struct e1000_nvm_info *nvm = &hw->nvm;
378 u32 eecd = E1000_READ_REG(hw, E1000_EECD);
379 s32 ret_val = E1000_SUCCESS;
380 u8 spi_stat_reg;
382 DEBUGFUNC("e1000_ready_nvm_eeprom");
384 if (nvm->type == e1000_nvm_eeprom_microwire) {
385 /* Clear SK and DI */
386 eecd &= ~(E1000_EECD_DI | E1000_EECD_SK);
387 E1000_WRITE_REG(hw, E1000_EECD, eecd);
388 /* Set CS */
389 eecd |= E1000_EECD_CS;
390 E1000_WRITE_REG(hw, E1000_EECD, eecd);
391 } else
392 if (nvm->type == e1000_nvm_eeprom_spi) {
393 u16 timeout = NVM_MAX_RETRY_SPI;
395 /* Clear SK and CS */
396 eecd &= ~(E1000_EECD_CS | E1000_EECD_SK);
397 E1000_WRITE_REG(hw, E1000_EECD, eecd);
398 E1000_WRITE_FLUSH(hw);
399 usec_delay(1);
402 * Read "Status Register" repeatedly until the LSB is cleared.
403 * The EEPROM will signal that the command has been completed
404 * by clearing bit 0 of the internal status register. If it's
405 * not cleared within 'timeout', then error out.
407 while (timeout) {
408 e1000_shift_out_eec_bits(hw, NVM_RDSR_OPCODE_SPI,
409 hw->nvm.opcode_bits);
410 spi_stat_reg = (u8)e1000_shift_in_eec_bits(hw, 8);
411 if (!(spi_stat_reg & NVM_STATUS_RDY_SPI))
412 break;
414 usec_delay(5);
415 e1000_standby_nvm(hw);
416 timeout--;
419 if (!timeout) {
420 DEBUGOUT("SPI NVM Status error\n");
421 ret_val = -E1000_ERR_NVM;
422 goto out;
426 out:
427 return ret_val;
431 * e1000_read_nvm_spi - Read EEPROM's using SPI
432 * @hw: pointer to the HW structure
433 * @offset: offset of word in the EEPROM to read
434 * @words: number of words to read
435 * @data: word read from the EEPROM
437 * Reads a 16 bit word from the EEPROM.
439 s32 e1000_read_nvm_spi(struct e1000_hw *hw, u16 offset, u16 words, u16 *data)
441 struct e1000_nvm_info *nvm = &hw->nvm;
442 u32 i = 0;
443 s32 ret_val;
444 u16 word_in;
445 u8 read_opcode = NVM_READ_OPCODE_SPI;
447 DEBUGFUNC("e1000_read_nvm_spi");
450 * A check for invalid values: offset too large, too many words,
451 * and not enough words.
453 if ((offset >= nvm->word_size) || (words > (nvm->word_size - offset)) ||
454 (words == 0)) {
455 DEBUGOUT("nvm parameter(s) out of bounds\n");
456 ret_val = -E1000_ERR_NVM;
457 goto out;
460 ret_val = nvm->ops.acquire(hw);
461 if (ret_val)
462 goto out;
464 ret_val = e1000_ready_nvm_eeprom(hw);
465 if (ret_val)
466 goto release;
468 e1000_standby_nvm(hw);
470 if ((nvm->address_bits == 8) && (offset >= 128))
471 read_opcode |= NVM_A8_OPCODE_SPI;
473 /* Send the READ command (opcode + addr) */
474 e1000_shift_out_eec_bits(hw, read_opcode, nvm->opcode_bits);
475 e1000_shift_out_eec_bits(hw, (u16)(offset*2), nvm->address_bits);
478 * Read the data. SPI NVMs increment the address with each byte
479 * read and will roll over if reading beyond the end. This allows
480 * us to read the whole NVM from any offset
482 for (i = 0; i < words; i++) {
483 word_in = e1000_shift_in_eec_bits(hw, 16);
484 data[i] = (word_in >> 8) | (word_in << 8);
487 release:
488 nvm->ops.release(hw);
490 out:
491 return ret_val;
495 * e1000_read_nvm_microwire - Reads EEPROM's using microwire
496 * @hw: pointer to the HW structure
497 * @offset: offset of word in the EEPROM to read
498 * @words: number of words to read
499 * @data: word read from the EEPROM
501 * Reads a 16 bit word from the EEPROM.
503 s32 e1000_read_nvm_microwire(struct e1000_hw *hw, u16 offset, u16 words,
504 u16 *data)
506 struct e1000_nvm_info *nvm = &hw->nvm;
507 u32 i = 0;
508 s32 ret_val;
509 u8 read_opcode = NVM_READ_OPCODE_MICROWIRE;
511 DEBUGFUNC("e1000_read_nvm_microwire");
514 * A check for invalid values: offset too large, too many words,
515 * and not enough words.
517 if ((offset >= nvm->word_size) || (words > (nvm->word_size - offset)) ||
518 (words == 0)) {
519 DEBUGOUT("nvm parameter(s) out of bounds\n");
520 ret_val = -E1000_ERR_NVM;
521 goto out;
524 ret_val = nvm->ops.acquire(hw);
525 if (ret_val)
526 goto out;
528 ret_val = e1000_ready_nvm_eeprom(hw);
529 if (ret_val)
530 goto release;
532 for (i = 0; i < words; i++) {
533 /* Send the READ command (opcode + addr) */
534 e1000_shift_out_eec_bits(hw, read_opcode, nvm->opcode_bits);
535 e1000_shift_out_eec_bits(hw, (u16)(offset + i),
536 nvm->address_bits);
539 * Read the data. For microwire, each word requires the
540 * overhead of setup and tear-down.
542 data[i] = e1000_shift_in_eec_bits(hw, 16);
543 e1000_standby_nvm(hw);
546 release:
547 nvm->ops.release(hw);
549 out:
550 return ret_val;
554 * e1000_read_nvm_eerd - Reads EEPROM using EERD register
555 * @hw: pointer to the HW structure
556 * @offset: offset of word in the EEPROM to read
557 * @words: number of words to read
558 * @data: word read from the EEPROM
560 * Reads a 16 bit word from the EEPROM using the EERD register.
562 s32 e1000_read_nvm_eerd(struct e1000_hw *hw, u16 offset, u16 words, u16 *data)
564 struct e1000_nvm_info *nvm = &hw->nvm;
565 u32 i, eerd = 0;
566 s32 ret_val = E1000_SUCCESS;
568 DEBUGFUNC("e1000_read_nvm_eerd");
571 * A check for invalid values: offset too large, too many words,
572 * too many words for the offset, and not enough words.
574 if ((offset >= nvm->word_size) || (words > (nvm->word_size - offset)) ||
575 (words == 0)) {
576 DEBUGOUT("nvm parameter(s) out of bounds\n");
577 ret_val = -E1000_ERR_NVM;
578 goto out;
581 for (i = 0; i < words; i++) {
582 eerd = ((offset+i) << E1000_NVM_RW_ADDR_SHIFT) +
583 E1000_NVM_RW_REG_START;
585 E1000_WRITE_REG(hw, E1000_EERD, eerd);
586 ret_val = e1000_poll_eerd_eewr_done(hw, E1000_NVM_POLL_READ);
587 if (ret_val)
588 break;
590 data[i] = (E1000_READ_REG(hw, E1000_EERD) >>
591 E1000_NVM_RW_REG_DATA);
594 out:
595 return ret_val;
599 * e1000_write_nvm_spi - Write to EEPROM using SPI
600 * @hw: pointer to the HW structure
601 * @offset: offset within the EEPROM to be written to
602 * @words: number of words to write
603 * @data: 16 bit word(s) to be written to the EEPROM
605 * Writes data to EEPROM at offset using SPI interface.
607 * If e1000_update_nvm_checksum is not called after this function , the
608 * EEPROM will most likely contain an invalid checksum.
610 s32 e1000_write_nvm_spi(struct e1000_hw *hw, u16 offset, u16 words, u16 *data)
612 struct e1000_nvm_info *nvm = &hw->nvm;
613 s32 ret_val;
614 u16 widx = 0;
616 DEBUGFUNC("e1000_write_nvm_spi");
619 * A check for invalid values: offset too large, too many words,
620 * and not enough words.
622 if ((offset >= nvm->word_size) || (words > (nvm->word_size - offset)) ||
623 (words == 0)) {
624 DEBUGOUT("nvm parameter(s) out of bounds\n");
625 ret_val = -E1000_ERR_NVM;
626 goto out;
629 ret_val = nvm->ops.acquire(hw);
630 if (ret_val)
631 goto out;
633 while (widx < words) {
634 u8 write_opcode = NVM_WRITE_OPCODE_SPI;
636 ret_val = e1000_ready_nvm_eeprom(hw);
637 if (ret_val)
638 goto release;
640 e1000_standby_nvm(hw);
642 /* Send the WRITE ENABLE command (8 bit opcode) */
643 e1000_shift_out_eec_bits(hw, NVM_WREN_OPCODE_SPI,
644 nvm->opcode_bits);
646 e1000_standby_nvm(hw);
649 * Some SPI eeproms use the 8th address bit embedded in the
650 * opcode
652 if ((nvm->address_bits == 8) && (offset >= 128))
653 write_opcode |= NVM_A8_OPCODE_SPI;
655 /* Send the Write command (8-bit opcode + addr) */
656 e1000_shift_out_eec_bits(hw, write_opcode, nvm->opcode_bits);
657 e1000_shift_out_eec_bits(hw, (u16)((offset + widx) * 2),
658 nvm->address_bits);
660 /* Loop to allow for up to whole page write of eeprom */
661 while (widx < words) {
662 u16 word_out = data[widx];
663 word_out = (word_out >> 8) | (word_out << 8);
664 e1000_shift_out_eec_bits(hw, word_out, 16);
665 widx++;
667 if ((((offset + widx) * 2) % nvm->page_size) == 0) {
668 e1000_standby_nvm(hw);
669 break;
674 msec_delay(10);
675 release:
676 nvm->ops.release(hw);
678 out:
679 return ret_val;
683 * e1000_write_nvm_microwire - Writes EEPROM using microwire
684 * @hw: pointer to the HW structure
685 * @offset: offset within the EEPROM to be written to
686 * @words: number of words to write
687 * @data: 16 bit word(s) to be written to the EEPROM
689 * Writes data to EEPROM at offset using microwire interface.
691 * If e1000_update_nvm_checksum is not called after this function , the
692 * EEPROM will most likely contain an invalid checksum.
694 s32 e1000_write_nvm_microwire(struct e1000_hw *hw, u16 offset, u16 words,
695 u16 *data)
697 struct e1000_nvm_info *nvm = &hw->nvm;
698 s32 ret_val;
699 u32 eecd;
700 u16 words_written = 0;
701 u16 widx = 0;
703 DEBUGFUNC("e1000_write_nvm_microwire");
706 * A check for invalid values: offset too large, too many words,
707 * and not enough words.
709 if ((offset >= nvm->word_size) || (words > (nvm->word_size - offset)) ||
710 (words == 0)) {
711 DEBUGOUT("nvm parameter(s) out of bounds\n");
712 ret_val = -E1000_ERR_NVM;
713 goto out;
716 ret_val = nvm->ops.acquire(hw);
717 if (ret_val)
718 goto out;
720 ret_val = e1000_ready_nvm_eeprom(hw);
721 if (ret_val)
722 goto release;
724 e1000_shift_out_eec_bits(hw, NVM_EWEN_OPCODE_MICROWIRE,
725 (u16)(nvm->opcode_bits + 2));
727 e1000_shift_out_eec_bits(hw, 0, (u16)(nvm->address_bits - 2));
729 e1000_standby_nvm(hw);
731 while (words_written < words) {
732 e1000_shift_out_eec_bits(hw, NVM_WRITE_OPCODE_MICROWIRE,
733 nvm->opcode_bits);
735 e1000_shift_out_eec_bits(hw, (u16)(offset + words_written),
736 nvm->address_bits);
738 e1000_shift_out_eec_bits(hw, data[words_written], 16);
740 e1000_standby_nvm(hw);
742 for (widx = 0; widx < 200; widx++) {
743 eecd = E1000_READ_REG(hw, E1000_EECD);
744 if (eecd & E1000_EECD_DO)
745 break;
746 usec_delay(50);
749 if (widx == 200) {
750 DEBUGOUT("NVM Write did not complete\n");
751 ret_val = -E1000_ERR_NVM;
752 goto release;
755 e1000_standby_nvm(hw);
757 words_written++;
760 e1000_shift_out_eec_bits(hw, NVM_EWDS_OPCODE_MICROWIRE,
761 (u16)(nvm->opcode_bits + 2));
763 e1000_shift_out_eec_bits(hw, 0, (u16)(nvm->address_bits - 2));
765 release:
766 nvm->ops.release(hw);
768 out:
769 return ret_val;
773 * e1000_read_pba_string_generic - Read device part number
774 * @hw: pointer to the HW structure
775 * @pba_num: pointer to device part number
776 * @pba_num_size: size of part number buffer
778 * Reads the product board assembly (PBA) number from the EEPROM and stores
779 * the value in pba_num.
781 s32 e1000_read_pba_string_generic(struct e1000_hw *hw, u8 *pba_num,
782 u32 pba_num_size)
784 s32 ret_val;
785 u16 nvm_data;
786 u16 pba_ptr;
787 u16 offset;
788 u16 length;
790 DEBUGFUNC("e1000_read_pba_string_generic");
792 if (pba_num == NULL) {
793 DEBUGOUT("PBA string buffer was null\n");
794 ret_val = E1000_ERR_INVALID_ARGUMENT;
795 goto out;
798 ret_val = hw->nvm.ops.read(hw, NVM_PBA_OFFSET_0, 1, &nvm_data);
799 if (ret_val) {
800 DEBUGOUT("NVM Read Error\n");
801 goto out;
804 ret_val = hw->nvm.ops.read(hw, NVM_PBA_OFFSET_1, 1, &pba_ptr);
805 if (ret_val) {
806 DEBUGOUT("NVM Read Error\n");
807 goto out;
811 * if nvm_data is not ptr guard the PBA must be in legacy format which
812 * means pba_ptr is actually our second data word for the PBA number
813 * and we can decode it into an ascii string
815 if (nvm_data != NVM_PBA_PTR_GUARD) {
816 DEBUGOUT("NVM PBA number is not stored as string\n");
818 /* we will need 11 characters to store the PBA */
819 if (pba_num_size < 11) {
820 DEBUGOUT("PBA string buffer too small\n");
821 return E1000_ERR_NO_SPACE;
824 /* extract hex string from data and pba_ptr */
825 pba_num[0] = (nvm_data >> 12) & 0xF;
826 pba_num[1] = (nvm_data >> 8) & 0xF;
827 pba_num[2] = (nvm_data >> 4) & 0xF;
828 pba_num[3] = nvm_data & 0xF;
829 pba_num[4] = (pba_ptr >> 12) & 0xF;
830 pba_num[5] = (pba_ptr >> 8) & 0xF;
831 pba_num[6] = '-';
832 pba_num[7] = 0;
833 pba_num[8] = (pba_ptr >> 4) & 0xF;
834 pba_num[9] = pba_ptr & 0xF;
836 /* put a null character on the end of our string */
837 pba_num[10] = '\0';
839 /* switch all the data but the '-' to hex char */
840 for (offset = 0; offset < 10; offset++) {
841 if (pba_num[offset] < 0xA)
842 pba_num[offset] += '0';
843 else if (pba_num[offset] < 0x10)
844 pba_num[offset] += 'A' - 0xA;
847 goto out;
850 ret_val = hw->nvm.ops.read(hw, pba_ptr, 1, &length);
851 if (ret_val) {
852 DEBUGOUT("NVM Read Error\n");
853 goto out;
856 if (length == 0xFFFF || length == 0) {
857 DEBUGOUT("NVM PBA number section invalid length\n");
858 ret_val = E1000_ERR_NVM_PBA_SECTION;
859 goto out;
861 /* check if pba_num buffer is big enough */
862 if (pba_num_size < (((u32)length * 2) - 1)) {
863 DEBUGOUT("PBA string buffer too small\n");
864 ret_val = E1000_ERR_NO_SPACE;
865 goto out;
868 /* trim pba length from start of string */
869 pba_ptr++;
870 length--;
872 for (offset = 0; offset < length; offset++) {
873 ret_val = hw->nvm.ops.read(hw, pba_ptr + offset, 1, &nvm_data);
874 if (ret_val) {
875 DEBUGOUT("NVM Read Error\n");
876 goto out;
878 pba_num[offset * 2] = (u8)(nvm_data >> 8);
879 pba_num[(offset * 2) + 1] = (u8)(nvm_data & 0xFF);
881 pba_num[offset * 2] = '\0';
883 out:
884 return ret_val;
888 * e1000_read_mac_addr_generic - Read device MAC address
889 * @hw: pointer to the HW structure
891 * Reads the device MAC address from the EEPROM and stores the value.
892 * Since devices with two ports use the same EEPROM, we increment the
893 * last bit in the MAC address for the second port.
895 s32 e1000_read_mac_addr_generic(struct e1000_hw *hw)
897 u32 rar_high;
898 u32 rar_low;
899 u16 i;
901 rar_high = E1000_READ_REG(hw, E1000_RAH(0));
902 rar_low = E1000_READ_REG(hw, E1000_RAL(0));
904 for (i = 0; i < E1000_RAL_MAC_ADDR_LEN; i++)
905 hw->mac.perm_addr[i] = (u8)(rar_low >> (i*8));
907 for (i = 0; i < E1000_RAH_MAC_ADDR_LEN; i++)
908 hw->mac.perm_addr[i+4] = (u8)(rar_high >> (i*8));
910 for (i = 0; i < ETH_ADDR_LEN; i++)
911 hw->mac.addr[i] = hw->mac.perm_addr[i];
913 return E1000_SUCCESS;
917 * e1000_validate_nvm_checksum_generic - Validate EEPROM checksum
918 * @hw: pointer to the HW structure
920 * Calculates the EEPROM checksum by reading/adding each word of the EEPROM
921 * and then verifies that the sum of the EEPROM is equal to 0xBABA.
923 s32 e1000_validate_nvm_checksum_generic(struct e1000_hw *hw)
925 s32 ret_val = E1000_SUCCESS;
926 u16 checksum = 0;
927 u16 i, nvm_data;
929 DEBUGFUNC("e1000_validate_nvm_checksum_generic");
931 for (i = 0; i < (NVM_CHECKSUM_REG + 1); i++) {
932 ret_val = hw->nvm.ops.read(hw, i, 1, &nvm_data);
933 if (ret_val) {
934 DEBUGOUT("NVM Read Error\n");
935 goto out;
937 checksum += nvm_data;
940 if (checksum != (u16) NVM_SUM) {
941 DEBUGOUT("NVM Checksum Invalid\n");
942 ret_val = -E1000_ERR_NVM;
943 goto out;
946 out:
947 return ret_val;
951 * e1000_update_nvm_checksum_generic - Update EEPROM checksum
952 * @hw: pointer to the HW structure
954 * Updates the EEPROM checksum by reading/adding each word of the EEPROM
955 * up to the checksum. Then calculates the EEPROM checksum and writes the
956 * value to the EEPROM.
958 s32 e1000_update_nvm_checksum_generic(struct e1000_hw *hw)
960 s32 ret_val;
961 u16 checksum = 0;
962 u16 i, nvm_data;
964 DEBUGFUNC("e1000_update_nvm_checksum");
966 for (i = 0; i < NVM_CHECKSUM_REG; i++) {
967 ret_val = hw->nvm.ops.read(hw, i, 1, &nvm_data);
968 if (ret_val) {
969 DEBUGOUT("NVM Read Error while updating checksum.\n");
970 goto out;
972 checksum += nvm_data;
974 checksum = (u16) NVM_SUM - checksum;
975 ret_val = hw->nvm.ops.write(hw, NVM_CHECKSUM_REG, 1, &checksum);
976 if (ret_val)
977 DEBUGOUT("NVM Write Error while updating checksum.\n");
979 out:
980 return ret_val;
984 * e1000_reload_nvm_generic - Reloads EEPROM
985 * @hw: pointer to the HW structure
987 * Reloads the EEPROM by setting the "Reinitialize from EEPROM" bit in the
988 * extended control register.
990 static void e1000_reload_nvm_generic(struct e1000_hw *hw)
992 u32 ctrl_ext;
994 DEBUGFUNC("e1000_reload_nvm_generic");
996 usec_delay(10);
997 ctrl_ext = E1000_READ_REG(hw, E1000_CTRL_EXT);
998 ctrl_ext |= E1000_CTRL_EXT_EE_RST;
999 E1000_WRITE_REG(hw, E1000_CTRL_EXT, ctrl_ext);
1000 E1000_WRITE_FLUSH(hw);