4 /*******************************************************************************
6 Intel PRO/1000 Linux driver
7 Copyright(c) 1999 - 2008 Intel Corporation.
9 This program is free software; you can redistribute it and/or modify it
10 under the terms and conditions of the GNU General Public License,
11 version 2, as published by the Free Software Foundation.
13 This program is distributed in the hope it will be useful, but WITHOUT
14 ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
15 FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
18 You should have received a copy of the GNU General Public License along with
19 this program; if not, write to the Free Software Foundation, Inc.,
20 51 Franklin St - Fifth Floor, Boston, MA 02110-1301 USA.
22 The full GNU General Public License is included in this distribution in
23 the file called "COPYING".
26 Linux NICS <linux.nics@intel.com>
27 e1000-devel Mailing List <e1000-devel@lists.sourceforge.net>
28 Intel Corporation, 5200 N.E. Elam Young Parkway, Hillsboro, OR 97124-6497
30 *******************************************************************************/
33 /* glue for the OS-dependent part of e1000
34 * includes register access macros
37 #ifndef _E1000_OSDEP_H_
38 #define _E1000_OSDEP_H_
42 #define ADVERTISED_1000baseT_Full (1 << 5)
43 #define ADVERTISED_Autoneg (1 << 6)
44 #define ADVERTISED_TP (1 << 7)
45 #define ADVERTISED_FIBRE (1 << 10)
47 #define AUTONEG_DISABLE 0x00
48 #define AUTONEG_ENABLE 0x01
50 #define E1000_FLAG_HAS_SMBUS (1 << 0)
51 #define E1000_FLAG_HAS_INTR_MODERATION (1 << 4)
52 #define E1000_FLAG_BAD_TX_CARRIER_STATS_FD (1 << 6)
53 #define E1000_FLAG_QUAD_PORT_A (1 << 8)
54 #define E1000_FLAG_SMART_POWER_DOWN (1 << 9)
56 #define E1000_TX_FLAGS_CSUM 0x00000001
57 #define E1000_TX_FLAGS_VLAN 0x00000002
58 #define E1000_TX_FLAGS_TSO 0x00000004
59 #define E1000_TX_FLAGS_IPV4 0x00000008
60 #define E1000_TX_FLAGS_VLAN_MASK 0xffff0000
61 #define E1000_TX_FLAGS_VLAN_SHIFT 16
63 #define ALIGN(x,a) (((x)+(a)-1L)&~((a)-1L))
64 #define min(a, b) (((a) < (b)) ? (a) : (b))
65 #define max(a, b) (((a) > (b)) ? (a) : (b))
67 #define E1000_MAX_INTR 10
69 /* TX/RX descriptor defines */
70 #define E1000_DEFAULT_TXD 256
71 #define E1000_MAX_TXD 256
72 #define E1000_MIN_TXD 80
73 #define E1000_MAX_82544_TXD 4096
75 #define E1000_DEFAULT_RXD 256
76 #define E1000_MAX_RXD 256
78 #define E1000_MIN_RXD 80
79 #define E1000_MAX_82544_RXD 4096
81 #define E1000_MIN_ITR_USECS 10 /* 100000 irq/sec */
82 #define E1000_MAX_ITR_USECS 10000 /* 100 irq/sec */
85 /* this is the size past which hardware will drop packets when setting LPE=0 */
86 #define MAXIMUM_ETHERNET_VLAN_SIZE 1522
88 /* Supported Rx Buffer Sizes */
89 #define E1000_RXBUFFER_128 128
90 #define E1000_RXBUFFER_256 256
91 #define E1000_RXBUFFER_512 512
92 #define E1000_RXBUFFER_1024 1024
93 #define E1000_RXBUFFER_2048 2048
94 #define E1000_RXBUFFER_4096 4096
95 #define E1000_RXBUFFER_8192 8192
96 #define E1000_RXBUFFER_16384 16384
98 /* SmartSpeed delimiters */
99 #define E1000_SMARTSPEED_DOWNSHIFT 3
100 #define E1000_SMARTSPEED_MAX 15
102 /* Packet Buffer allocations */
103 #define E1000_PBA_BYTES_SHIFT 0xA
104 #define E1000_TX_HEAD_ADDR_SHIFT 7
105 #define E1000_PBA_TX_MASK 0xFFFF0000
107 /* Early Receive defines */
108 #define E1000_ERT_2048 0x100
110 #define E1000_FC_PAUSE_TIME 0x0680 /* 858 usec */
112 /* How many Tx Descriptors do we need to call netif_wake_queue ? */
113 #define E1000_TX_QUEUE_WAKE 16
114 /* How many Rx Buffers do we bundle into one write to the hardware ? */
115 #define E1000_RX_BUFFER_WRITE 16 /* Must be power of 2 */
117 #define AUTO_ALL_MODES 0
118 #define E1000_EEPROM_82544_APM 0x0004
119 #define E1000_EEPROM_APME 0x0400
121 #ifndef E1000_MASTER_SLAVE
122 /* Switch to override PHY master/slave setting */
123 #define E1000_MASTER_SLAVE e1000_ms_hw_default
126 /* standard definitions .. */
127 #ifndef PCIBAR_TYPE_IO
128 #define PCIBAR_TYPE_IO 0x01
130 #ifndef PCICS_COMMAND
131 #define PCICS_COMMAND 0x04 /* 16 bits */
133 #ifndef PCICMB_INVALIDATE
134 #define PCICMB_INVALIDATE 4 /* Use memory write and invalidate */
137 #define PCI_COMMAND_REGISTER PCICS_COMMAND
138 #define CMD_MEM_WRT_INVALIDATE (1 << PCICMB_INVALIDATE)
141 #define E1000_BIG_ENDIAN __BIG_ENDIAN
145 #if defined(intel_debug)
146 #define E1K_INTELDEBUG
150 #if defined(E1K_INTELDEBUG)
151 #define DEBUGOUT(S) D(bug("[%s] %s:" S, ((struct e1000Unit *)hw->back)->e1ku_name, __PRETTY_FUNCTION__));
152 #define DEBUGOUT1(S, A) D(bug("[%s] %s:" S , ((struct e1000Unit *)hw->back)->e1ku_name, __PRETTY_FUNCTION__, A));
154 #define DEBUGFUNC(F) D(bug("[%s]: " F "()\n", ((struct e1000Unit *)hw->back)->e1ku_name));
155 #define DEBUGOUT2(S, A, B) D(bug("[%s] %s:" S , ((struct e1000Unit *)hw->back)->e1ku_name, __PRETTY_FUNCTION__, A, B));
156 #define DEBUGOUT3(S, A, B, C) D(bug("[%s] %s:" S , ((struct e1000Unit *)hw->back)->e1ku_name, __PRETTY_FUNCTION__, A, B, C));
157 #define DEBUGOUT7(S, A, B, C, D, E, F, G) D(bug("[%s] %s:" S , ((struct e1000Unit *)hw->back)->e1ku_name, __PRETTY_FUNCTION__, A, B, C, D, E, F, G));
160 #define DEBUGOUT1(S, A...)
162 #define DEBUGFUNC(F) DEBUGOUT(F "\n")
163 #define DEBUGOUT2 DEBUGOUT1
164 #define DEBUGOUT3 DEBUGOUT2
165 #define DEBUGOUT7 DEBUGOUT3
168 static inline ULONG
readl(u8 __iomem
*base
)
170 return *((ULONG
volatile *)base
);
172 static inline void writel(ULONG val
, u8 __iomem
*base
)
174 *((ULONG
volatile *)base
) = val
;
177 static inline UBYTE
MMIO_R8(u8 __iomem
*base
)
179 return *((UBYTE
volatile *)base
);
181 static inline UWORD
MMIO_R16(u8 __iomem
*base
)
183 return *((UWORD
volatile *)base
);
185 static inline ULONG
MMIO_R32(u8 __iomem
*base
)
187 return *((ULONG
volatile *)base
);
190 static inline void MMIO_W8(APTR addr
, UBYTE val8
)
192 *((volatile UBYTE
*)(addr
)) = (val8
);
196 static inline void MMIO_W16(APTR addr
, UWORD val16
)
198 *((volatile UWORD
*)(addr
)) = (val16
);
203 static inline void MMIO_W32(APTR addr
, ULONG val32
)
205 *((volatile ULONG
*)(addr
)) = (val32
);
210 #define E1000_REGISTER(a, reg) (((a)->mac.type >= e1000_82543) \
212 : e1000_translate_register_82542(reg))
214 static inline u32
er32(u8 __iomem
*reg
)
219 static inline void ew32(u8 __iomem
*reg
, u32 val
)
224 #define E1000_WRITE_REG(a, reg, value) \
225 ew32(((a)->hw_addr + E1000_REGISTER(a, reg)),value)
227 #define E1000_READ_REG(a, reg) (er32((a)->hw_addr + E1000_REGISTER(a, reg)))
229 #define E1000_WRITE_REG_ARRAY(a, reg, offset, value) ( \
230 writel((value), ((a)->hw_addr + E1000_REGISTER(a, reg) + ((offset) << 2))))
232 #define E1000_READ_REG_ARRAY(a, reg, offset) ( \
233 readl((a)->hw_addr + E1000_REGISTER(a, reg) + ((offset) << 2)))
235 #define E1000_READ_REG_ARRAY_DWORD E1000_READ_REG_ARRAY
236 #define E1000_WRITE_REG_ARRAY_DWORD E1000_WRITE_REG_ARRAY
238 #define E1000_WRITE_REG_ARRAY_WORD(a, reg, offset, value) ( \
239 writew((value), ((a)->hw_addr + E1000_REGISTER(a, reg) + ((offset) << 1))))
241 #define E1000_READ_REG_ARRAY_WORD(a, reg, offset) ( \
242 readw((a)->hw_addr + E1000_REGISTER(a, reg) + ((offset) << 1)))
244 #define E1000_WRITE_REG_ARRAY_BYTE(a, reg, offset, value) ( \
245 writeb((value), ((a)->hw_addr + E1000_REGISTER(a, reg) + (offset))))
247 #define E1000_READ_REG_ARRAY_BYTE(a, reg, offset) ( \
248 readb((a)->hw_addr + E1000_REGISTER(a, reg) + (offset)))
250 #define E1000_WRITE_REG_IO(a, reg, offset) do { \
251 LONGOUT(((a)->io_base), reg); \
252 LONGOUT(((a)->io_base + 4), offset); } while(0)
254 #define E1000_WRITE_FLUSH(a) E1000_READ_REG(a, E1000_STATUS)
256 #define E1000_WRITE_FLASH_REG(a, reg, value) ( \
257 writel((value), ((a)->flash_address + reg)))
259 #define E1000_WRITE_FLASH_REG16(a, reg, value) ( \
260 writew((value), ((a)->flash_address + reg)))
262 #define E1000_READ_FLASH_REG(a, reg) (readl((a)->flash_address + reg))
264 #define E1000_READ_FLASH_REG16(a, reg) (readw((a)->flash_address + reg))
266 #define SANA2_SPECIAL_STAT_COUNT 3
269 struct Node e1ku_Node
;
271 struct e1000Base
*e1ku_device
; /* Pointer to our device base */
276 IPTR e1ku_DriverFlags
;
278 OOP_Object
*e1ku_PCIDevice
;
279 OOP_Object
*e1ku_PCIDriver
;
284 struct SignalSemaphore e1ku_unit_lock
;
286 LONG e1ku_range_count
;
287 struct MinList e1ku_Openers
;
288 struct MinList e1ku_multicast_ranges
;
289 struct MinList e1ku_type_trackers
;
293 struct Sana2DeviceQuery e1ku_Sana2Info
;
294 struct Sana2DeviceStats e1ku_stats
;
295 ULONG e1ku_special_stats
[SANA2_SPECIAL_STAT_COUNT
];
297 struct Process
*e1ku_Process
;
299 struct MsgPort
*e1ku_input_port
;
301 struct MsgPort
*e1ku_request_ports
[REQUEST_QUEUE_COUNT
];
303 struct Interrupt e1ku_irqhandler
;
304 struct Interrupt e1ku_touthandler
;
306 struct MsgPort
*e1ku_TimerSlowPort
;
307 struct timerequest
*e1ku_TimerSlowReq
;
309 struct MsgPort
*e1ku_TimerFastPort
;
310 struct timerequest
*e1ku_TimerFastReq
;
312 struct MsgPort e1ku_DelayPort
;
313 struct timerequest e1ku_DelayReq
;
320 UBYTE e1ku_dev_addr
[6];
321 UBYTE e1ku_org_addr
[6];
323 struct Interrupt e1ku_tx_int
;
325 /* Start : Intel e1000 specific */
327 IPTR e1ku_Private00
; /* Pointer to Intels driver-code hardware struct */
329 ULONG e1ku_FlashSize
;
333 ULONG e1ku_txRing_QueueSize
;
334 ULONG e1ku_rxRing_QueueSize
;
335 struct e1000_tx_ring
*e1ku_txRing
;
336 struct e1000_rx_ring
*e1ku_rxRing
;
344 ULONG e1ku_frame_max
;
345 ULONG e1ku_frame_min
;
347 ULONG e1ku_tx_fifo_head
;
348 ULONG e1ku_tx_head_addr
;
349 ULONG e1ku_tx_fifo_size
;
351 struct e1000_hw_stats
*e1ku_hw_stats
;
355 /* End : Intel e1000 specific */
357 struct timeval e1ku_toutPOLL
;
362 #define net_device e1000Unit
364 #define E1000_DESC_UNUSED(R) \
365 ((((R)->next_to_clean > (R)->next_to_use) ? 0 : (R)->count) + \
366 (R)->next_to_clean - (R)->next_to_use - 1)
368 #define E1000_RX_DESC_EXT(R, i) \
369 (&(((union e1000_rx_desc_extended *)((R).desc))[i]))
370 #define E1000_GET_DESC(R, i, type) ((struct type *)&((R)->desc[i]))
371 #define E1000_RX_DESC(R, i) &(R->desc[i])
372 #define E1000_TX_DESC(R, i) &(R->desc[i])
373 #define E1000_CONTEXT_DESC(R, i) E1000_GET_DESC(R, i, e1000_context_desc)
375 /* e1000.c definitions */
376 /* Timer functions */
377 /* Some workarounds require millisecond delays and are run during interrupt
378 * context. Most notably, when establishing link, the phy may need tweaking
379 * but cannot process phy register reads/writes faster than millisecond
380 * intervals...and we establish link due to a "link status change" interrupt.
382 void e1000_msec_delay(struct net_device
*, ULONG
);
383 void e1000_msec_delay_irq(struct net_device
*, ULONG
);
384 void e1000_usec_delay(struct net_device
*, ULONG
);
385 #define msec_delay(msec) e1000_msec_delay((struct net_device *)hw->back, msec)
386 #define msec_delay_irq(msec) e1000_msec_delay_irq((struct net_device *)hw->back, msec)
387 #define usec_delay(usec) e1000_usec_delay((struct net_device *)hw->back, usec)
389 int request_irq(struct net_device
*);
390 void e1000func_irq_disable(struct net_device
*);
391 void e1000func_irq_enable(struct net_device
*);
392 void e1000func_reset(struct net_device
*);
393 int e1000func_setup_all_tx_resources(struct net_device
*);
394 int e1000func_setup_all_rx_resources(struct net_device
*);
395 void e1000func_configure(struct net_device
*);
396 void e1000func_free_tx_resources(struct net_device
*, struct e1000_tx_ring
*);
397 void e1000func_free_rx_resources(struct net_device
*, struct e1000_rx_ring
*);
398 int e1000func_set_mac(struct net_device
*);
399 void e1000func_set_multi(struct net_device
*);
400 BOOL
e1000func_clean_tx_irq(struct net_device
*, struct e1000_tx_ring
*);
401 BOOL
e1000func_clean_rx_irq(struct net_device
*, struct e1000_rx_ring
*);
403 #endif /* _E1000_OSDEP_H_ */