workbench/devs/networks/e1000/e1000_phy.h

   1 /*******************************************************************************
   2
   3   Intel PRO/1000 Linux driver
   4   Copyright(c) 1999 - 2010 Intel Corporation.
   5
   6   This program is free software; you can redistribute it and/or modify it
   7   under the terms and conditions of the GNU General Public License,
   8   version 2, as published by the Free Software Foundation.
   9
  10   This program is distributed in the hope it will be useful, but WITHOUT
  11   ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
  12   FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License for
  13   more details.
  14
  15   You should have received a copy of the GNU General Public License along with
  16   this program; if not, write to the Free Software Foundation, Inc.,
  17   51 Franklin St - Fifth Floor, Boston, MA 02110-1301 USA.
  18
  19   The full GNU General Public License is included in this distribution in
  20   the file called "COPYING".
  21
  22   Contact Information:
  23   Linux NICS <linux.nics@intel.com>
  24   e1000-devel Mailing List <e1000-devel@lists.sourceforge.net>
  25   Intel Corporation, 5200 N.E. Elam Young Parkway, Hillsboro, OR 97124-6497
  26
  27 *******************************************************************************/
  28
  29 #ifndef _E1000_PHY_H_
  30 #define _E1000_PHY_H_
  31
  32 void e1000_init_phy_ops_generic(struct e1000_hw *hw);
  33 s32  e1000_null_read_reg(struct e1000_hw *hw, u32 offset, u16 *data);
  34 void e1000_null_phy_generic(struct e1000_hw *hw);
  35 s32  e1000_null_lplu_state(struct e1000_hw *hw, bool active);
  36 s32  e1000_null_write_reg(struct e1000_hw *hw, u32 offset, u16 data);
  37 s32  e1000_null_set_page(struct e1000_hw *hw, u16 data);
  38 s32  e1000_check_downshift_generic(struct e1000_hw *hw);
  39 s32  e1000_check_polarity_m88(struct e1000_hw *hw);
  40 s32  e1000_check_polarity_igp(struct e1000_hw *hw);
  41 s32  e1000_check_polarity_ife(struct e1000_hw *hw);
  42 s32  e1000_check_reset_block_generic(struct e1000_hw *hw);
  43 s32  e1000_phy_setup_autoneg(struct e1000_hw *hw);
  44 s32  e1000_copper_link_autoneg(struct e1000_hw *hw);
  45 s32  e1000_copper_link_setup_igp(struct e1000_hw *hw);
  46 s32  e1000_copper_link_setup_m88(struct e1000_hw *hw);
  47 s32  e1000_phy_force_speed_duplex_igp(struct e1000_hw *hw);
  48 s32  e1000_phy_force_speed_duplex_m88(struct e1000_hw *hw);
  49 s32  e1000_phy_force_speed_duplex_ife(struct e1000_hw *hw);
  50 s32  e1000_get_cable_length_m88(struct e1000_hw *hw);
  51 s32  e1000_get_cable_length_igp_2(struct e1000_hw *hw);
  52 s32  e1000_get_cfg_done_generic(struct e1000_hw *hw);
  53 s32  e1000_get_phy_id(struct e1000_hw *hw);
  54 s32  e1000_get_phy_info_igp(struct e1000_hw *hw);
  55 s32  e1000_get_phy_info_m88(struct e1000_hw *hw);
  56 s32  e1000_get_phy_info_ife(struct e1000_hw *hw);
  57 s32  e1000_phy_sw_reset_generic(struct e1000_hw *hw);
  58 void e1000_phy_force_speed_duplex_setup(struct e1000_hw *hw, u16 *phy_ctrl);
  59 s32  e1000_phy_hw_reset_generic(struct e1000_hw *hw);
  60 s32  e1000_phy_reset_dsp_generic(struct e1000_hw *hw);
  61 s32  e1000_read_kmrn_reg_generic(struct e1000_hw *hw, u32 offset, u16 *data);
  62 s32  e1000_read_kmrn_reg_locked(struct e1000_hw *hw, u32 offset, u16 *data);
  63 s32  e1000_set_page_igp(struct e1000_hw *hw, u16 page);
  64 s32  e1000_read_phy_reg_igp(struct e1000_hw *hw, u32 offset, u16 *data);
  65 s32  e1000_read_phy_reg_igp_locked(struct e1000_hw *hw, u32 offset, u16 *data);
  66 s32  e1000_read_phy_reg_m88(struct e1000_hw *hw, u32 offset, u16 *data);
  67 s32  e1000_set_d3_lplu_state_generic(struct e1000_hw *hw, bool active);
  68 s32  e1000_setup_copper_link_generic(struct e1000_hw *hw);
  69 s32  e1000_wait_autoneg_generic(struct e1000_hw *hw);
  70 s32  e1000_write_kmrn_reg_generic(struct e1000_hw *hw, u32 offset, u16 data);
  71 s32  e1000_write_kmrn_reg_locked(struct e1000_hw *hw, u32 offset, u16 data);
  72 s32  e1000_write_phy_reg_igp(struct e1000_hw *hw, u32 offset, u16 data);
  73 s32  e1000_write_phy_reg_igp_locked(struct e1000_hw *hw, u32 offset, u16 data);
  74 s32  e1000_write_phy_reg_m88(struct e1000_hw *hw, u32 offset, u16 data);
  75 s32  e1000_phy_reset_dsp(struct e1000_hw *hw);
  76 s32  e1000_phy_has_link_generic(struct e1000_hw *hw, u32 iterations,
  77                                 u32 usec_interval, bool *success);
  78 s32  e1000_phy_init_script_igp3(struct e1000_hw *hw);
  79 enum e1000_phy_type e1000_get_phy_type_from_id(u32 phy_id);
  80 s32  e1000_determine_phy_address(struct e1000_hw *hw);
  81 s32  e1000_enable_phy_wakeup_reg_access_bm(struct e1000_hw *hw, u16 *phy_reg);
  82 s32  e1000_disable_phy_wakeup_reg_access_bm(struct e1000_hw *hw, u16 *phy_reg);
  83 void e1000_power_up_phy_copper(struct e1000_hw *hw);
  84 void e1000_power_down_phy_copper(struct e1000_hw *hw);
  85 s32  e1000_read_phy_reg_mdic(struct e1000_hw *hw, u32 offset, u16 *data);
  86 s32  e1000_write_phy_reg_mdic(struct e1000_hw *hw, u32 offset, u16 data);
  87
  88 #define E1000_MAX_PHY_ADDR                8
  89
  90 /* IGP01E1000 Specific Registers */
  91 #define IGP01E1000_PHY_PORT_CONFIG        0x10 /* Port Config */
  92 #define IGP01E1000_PHY_PORT_STATUS        0x11 /* Status */
  93 #define IGP01E1000_PHY_PORT_CTRL          0x12 /* Control */
  94 #define IGP01E1000_PHY_LINK_HEALTH        0x13 /* PHY Link Health */
  95 #define IGP01E1000_GMII_FIFO              0x14 /* GMII FIFO */
  96 #define IGP01E1000_PHY_CHANNEL_QUALITY    0x15 /* PHY Channel Quality */
  97 #define IGP02E1000_PHY_POWER_MGMT         0x19 /* Power Management */
  98 #define IGP01E1000_PHY_PAGE_SELECT        0x1F /* Page Select */
  99 #define BM_PHY_PAGE_SELECT                22   /* Page Select for BM */
 100 #define IGP_PAGE_SHIFT                    5
 101 #define PHY_REG_MASK                      0x1F
 102
 103 #define IGP01E1000_PHY_PCS_INIT_REG       0x00B4
 104 #define IGP01E1000_PHY_POLARITY_MASK      0x0078
 105
 106 #define IGP01E1000_PSCR_AUTO_MDIX         0x1000
 107 #define IGP01E1000_PSCR_FORCE_MDI_MDIX    0x2000 /* 0=MDI, 1=MDIX */
 108
 109 #define IGP01E1000_PSCFR_SMART_SPEED      0x0080
 110
 111 /* Enable flexible speed on link-up */
 112 #define IGP01E1000_GMII_FLEX_SPD          0x0010
 113 #define IGP01E1000_GMII_SPD               0x0020 /* Enable SPD */
 114
 115 #define IGP02E1000_PM_SPD                 0x0001 /* Smart Power Down */
 116 #define IGP02E1000_PM_D0_LPLU             0x0002 /* For D0a states */
 117 #define IGP02E1000_PM_D3_LPLU             0x0004 /* For all other states */
 118
 119 #define IGP01E1000_PLHR_SS_DOWNGRADE      0x8000
 120
 121 #define IGP01E1000_PSSR_POLARITY_REVERSED 0x0002
 122 #define IGP01E1000_PSSR_MDIX              0x0800
 123 #define IGP01E1000_PSSR_SPEED_MASK        0xC000
 124 #define IGP01E1000_PSSR_SPEED_1000MBPS    0xC000
 125
 126 #define IGP02E1000_PHY_CHANNEL_NUM        4
 127 #define IGP02E1000_PHY_AGC_A              0x11B1
 128 #define IGP02E1000_PHY_AGC_B              0x12B1
 129 #define IGP02E1000_PHY_AGC_C              0x14B1
 130 #define IGP02E1000_PHY_AGC_D              0x18B1
 131
 132 #define IGP02E1000_AGC_LENGTH_SHIFT       9   /* Course - 15:13, Fine - 12:9 */
 133 #define IGP02E1000_AGC_LENGTH_MASK        0x7F
 134 #define IGP02E1000_AGC_RANGE              15
 135
 136 #define IGP03E1000_PHY_MISC_CTRL          0x1B
 137 #define IGP03E1000_PHY_MISC_DUPLEX_MANUAL_SET  0x1000 /* Manually Set Duplex */
 138
 139 #define E1000_CABLE_LENGTH_UNDEFINED      0xFF
 140
 141 #define E1000_KMRNCTRLSTA_OFFSET          0x001F0000
 142 #define E1000_KMRNCTRLSTA_OFFSET_SHIFT    16
 143 #define E1000_KMRNCTRLSTA_REN             0x00200000
 144 #define E1000_KMRNCTRLSTA_DIAG_OFFSET     0x3    /* Kumeran Diagnostic */
 145 #define E1000_KMRNCTRLSTA_TIMEOUTS        0x4    /* Kumeran Timeouts */
 146 #define E1000_KMRNCTRLSTA_INBAND_PARAM    0x9    /* Kumeran InBand Parameters */
 147 #define E1000_KMRNCTRLSTA_IBIST_DISABLE   0x0200 /* Kumeran IBIST Disable */
 148 #define E1000_KMRNCTRLSTA_DIAG_NELPBK     0x1000 /* Nearend Loopback mode */
 149
 150 #define IFE_PHY_EXTENDED_STATUS_CONTROL 0x10
 151 #define IFE_PHY_SPECIAL_CONTROL     0x11 /* 100BaseTx PHY Special Control */
 152 #define IFE_PHY_SPECIAL_CONTROL_LED 0x1B /* PHY Special and LED Control */
 153 #define IFE_PHY_MDIX_CONTROL        0x1C /* MDI/MDI-X Control */
 154
 155 /* IFE PHY Extended Status Control */
 156 #define IFE_PESC_POLARITY_REVERSED    0x0100
 157
 158 /* IFE PHY Special Control */
 159 #define IFE_PSC_AUTO_POLARITY_DISABLE      0x0010
 160 #define IFE_PSC_FORCE_POLARITY             0x0020
 161 #define IFE_PSC_DISABLE_DYNAMIC_POWER_DOWN 0x0100
 162
 163 /* IFE PHY Special Control and LED Control */
 164 #define IFE_PSCL_PROBE_MODE            0x0020
 165 #define IFE_PSCL_PROBE_LEDS_OFF        0x0006 /* Force LEDs 0 and 2 off */
 166 #define IFE_PSCL_PROBE_LEDS_ON         0x0007 /* Force LEDs 0 and 2 on */
 167
 168 /* IFE PHY MDIX Control */
 169 #define IFE_PMC_MDIX_STATUS      0x0020 /* 1=MDI-X, 0=MDI */
 170 #define IFE_PMC_FORCE_MDIX       0x0040 /* 1=force MDI-X, 0=force MDI */
 171 #define IFE_PMC_AUTO_MDIX        0x0080 /* 1=enable auto MDI/MDI-X, 0=disable */
 172
 173 /* SFP modules ID memory locations */
 174 #define E1000_SFF_IDENTIFIER_OFFSET 0x00
 175 #define E1000_SFF_IDENTIFIER_SFF    0x02
 176 #define E1000_SFF_IDENTIFIER_SFP    0x03
 177
 178 #define E1000_SFF_ETH_FLAGS_OFFSET  0x06
 179 /* Flags for SFP modules compatible with ETH up to 1Gb */
 180 struct sfp_e1000_flags {
 181         u8 e1000_base_sx:1;
 182         u8 e1000_base_lx:1;
 183         u8 e1000_base_cx:1;
 184         u8 e1000_base_t:1;
 185         u8 e100_base_lx:1;
 186         u8 e100_base_fx:1;
 187         u8 e10_base_bx10:1;
 188         u8 e10_base_px:1;
 189 };
 190
 191 /* Vendor OUIs: format of OUI is 0x[byte0][byte1][byte2][00] */
 192 #define E1000_SFF_VENDOR_OUI_TYCO     0x00407600
 193 #define E1000_SFF_VENDOR_OUI_FTL      0x00906500
 194 #define E1000_SFF_VENDOR_OUI_AVAGO    0x00176A00
 195 #define E1000_SFF_VENDOR_OUI_INTEL    0x001B2100
 196
 197 #endif