workbench/devs/networks/emac/emac.h

   1 #ifndef EMAC_H_
   2 #define EMAC_H_
   3
   4 #include <inttypes.h>
   5 #include <exec/libraries.h>
   6 #include <exec/devices.h>
   7 #include <exec/lists.h>
   8 #include <exec/semaphores.h>
   9 #include <dos/dosextens.h>
  10 #include <devices/timer.h>
  11 #include <devices/sana2.h>
  12 #include <devices/sana2specialstats.h>
  13
  14 #include "mal.h"
  15
  16 #define EMAC_TASK1_NAME      "IBM EMAC0 task"
  17 #define EMAC_TASK2_NAME      "IBM EMAC1 task"
  18 #define EMAC_PORT_NAME       "IBM EMAC port"
  19
  20 enum {
  21     WRITE_QUEUE,
  22     ADOPT_QUEUE,
  23     EVENT_QUEUE,
  24     GENERAL_QUEUE,
  25     REQUEST_QUEUE_COUNT
  26 };
  27
  28 struct EMACUnit;
  29
  30 struct EMACBase {
  31     struct Device               emb_Device;
  32     struct Sana2DeviceQuery     emb_Sana2Info;
  33     void                        *emb_Pool;
  34
  35     struct EMACUnit             *emb_Units[2];
  36
  37     mal_descriptor_t            *emb_MALRXChannels[2];
  38     mal_descriptor_t            *emb_MALTXChannels[4];
  39
  40     void                        *emb_MALHandlers[5];
  41 };
  42
  43 /* Standard interface flags (netdevice->flags). */
  44 #define IFF_UP          0x1             /* interface is up              */
  45 #define IFF_BROADCAST   0x2             /* broadcast address valid      */
  46 #define IFF_DEBUG       0x4             /* turn on debugging            */
  47 #define IFF_LOOPBACK    0x8             /* is a loopback net            */
  48 #define IFF_POINTOPOINT 0x10            /* interface is has p-p link    */
  49 #define IFF_NOTRAILERS  0x20            /* avoid use of trailers        */
  50 #define IFF_RUNNING     0x40            /* resources allocated          */
  51 #define IFF_NOARP       0x80            /* no ARP protocol              */
  52 #define IFF_PROMISC     0x100           /* receive all packets          */
  53 #define IFF_ALLMULTI    0x200           /* receive all multicast packets*/
  54
  55 #define IFF_MASTER      0x400           /* master of a load balancer    */
  56 #define IFF_SLAVE       0x800           /* slave of a load balancer     */
  57
  58 #define IFF_MULTICAST   0x1000          /* Supports multicast           */
  59
  60 #define IFF_VOLATILE    (IFF_LOOPBACK|IFF_POINTOPOINT|IFF_BROADCAST|IFF_MASTER|IFF_SLAVE|IFF_RUNNING)
  61
  62 #define IFF_PORTSEL     0x2000          /* can set media type           */
  63 #define IFF_AUTOMEDIA   0x4000          /* auto media select active     */
  64 #define IFF_DYNAMIC     0x8000          /* dialup device with changing addresses*/
  65 #define IFF_SHARED      0x10000         /* interface may be shared */
  66 #define IFF_CONFIGURED  0x20000         /* interface already configured */
  67
  68 struct Opener
  69 {
  70     struct MinNode  node;
  71     struct MsgPort  read_port;
  72     BOOL            (*rx_function)(APTR, APTR, ULONG);
  73     BOOL            (*tx_function)(APTR, APTR, ULONG);
  74     struct Hook     *filter_hook;
  75     struct MinList  initial_stats;
  76 };
  77
  78 struct TypeStats
  79 {
  80     struct MinNode node;
  81     ULONG packet_type;
  82     struct Sana2PacketTypeStats stats;
  83 };
  84
  85 struct TypeTracker
  86 {
  87     struct MinNode node;
  88     ULONG packet_type;
  89     struct Sana2PacketTypeStats stats;
  90     ULONG user_count;
  91 };
  92
  93 struct AddressRange
  94 {
  95     struct MinNode node;
  96     ULONG add_count;
  97     ULONG lower_bound_left;
  98     ULONG upper_bound_left;
  99     UWORD lower_bound_right;
 100     UWORD upper_bound_right;
 101 };
 102
 103 #define ETH_DATA_LEN        1500
 104 #define ETH_ADDRESSSIZE     6
 105 #define ETH_HEADERSIZE      14
 106 #define ETH_CRCSIZE         4
 107 #define ETH_MTU             (ETH_DATA_LEN)
 108 #define ETH_MAXPACKETSIZE   ((ETH_HEADERSIZE) + (ETH_MTU) + (ETH_CRCSIZE))
 109
 110 #define ETH_PACKET_DEST     0
 111 #define ETH_PACKET_SOURCE   6
 112 #define ETH_PACKET_TYPE     12
 113 #define ETH_PACKET_IEEELEN  12
 114 #define ETH_PACKET_SNAPTYPE 20
 115 #define ETH_PACKET_DATA     14
 116 #define ETH_PACKET_CRC      (ETH_PACKET_DATA + ETH_MTU)
 117
 118 #define RXTX_ALLOC_BUFSIZE  (ETH_MAXPACKETSIZE + 26)
 119
 120 struct eth_frame {
 121     uint8_t     eth_packet_dest[6];
 122     uint8_t     eth_packet_source[6];
 123     uint16_t    eth_packet_type;
 124     uint8_t     eth_packet_data[ETH_MTU];
 125     uint8_t     eth_packet_crc[4];
 126     uint8_t     eth_pad[RXTX_ALLOC_BUFSIZE - ETH_MAXPACKETSIZE];
 127 } __attribute__((packed));
 128
 129 #define TX_RING_SIZE      32    /* 256 max */
 130 #define RX_RING_SIZE      64    /* 256 max */
 131
 132 #define STAT_COUNT 3
 133
 134 struct EMACUnit {
 135     struct SignalSemaphore      eu_Lock;
 136     struct MinList      eu_Openers;
 137     struct MinList      eu_MulticastRanges;
 138     struct MinList      eu_TypeTrackers;
 139     struct Process      *eu_Process;
 140     struct EMACBase     *eu_EMACBase;
 141     void                *eu_IRQHandler;
 142
 143     struct Interrupt    eu_TXInt;
 144     struct Interrupt    eu_RXInt;
 145     struct Interrupt    eu_TXEndInt;
 146
 147     mal_packet_t        *eu_RXChannel;
 148     mal_packet_t        *eu_TXChannel;
 149     uint8_t             eu_LastRXSlot;
 150     uint8_t             eu_LastTXSlot;
 151
 152     intptr_t            eu_IOBase;
 153     uint32_t            eu_Flags;
 154     uint32_t            eu_OpenCount;
 155     uint32_t            eu_IER;
 156     int32_t             eu_RangeCount;
 157
 158     uint16_t            eu_MTU;
 159
 160     uint8_t             eu_DevAddr[ETH_ADDRESSSIZE];
 161     uint8_t             eu_OrgAddr[ETH_ADDRESSSIZE];
 162
 163     uint8_t             eu_UnitNum;
 164     uint8_t             eu_PHYAddr;
 165
 166     struct Sana2DeviceStats eu_Stats;
 167     uint32_t            eu_SpecialStats[STAT_COUNT];
 168
 169     int                (*start)(struct EMACUnit *);
 170     int                (*stop)(struct EMACUnit *);
 171     void               (*udelay)(struct EMACUnit *, uint32_t usec);
 172     void               (*set_multicast)(struct EMACUnit *);
 173     void               (*set_mac_address)(struct EMACUnit *);
 174
 175     struct MsgPort      *eu_RequestPorts[REQUEST_QUEUE_COUNT];
 176     struct MsgPort      *eu_InputPort;
 177
 178     struct MsgPort      eu_TimerPort;
 179     struct timerequest  eu_TimerRequest;
 180 };
 181
 182 void EMAC_Startup(struct EMACUnit *unit);
 183 void EMACIRQHandler(struct EMACBase *EMACBase, struct EMACUnit *Unit);
 184 struct EMACUnit *CreateUnit(struct EMACBase *EMACBase, uint8_t num);
 185 void handle_request(struct EMACBase *EMACBase, struct IOSana2Req *request);
 186 BOOL AddMulticastRange(struct EMACBase *EMACBase, struct EMACUnit *unit, const UBYTE *lower_bound, const UBYTE *upper_bound);
 187 BOOL RemMulticastRange(struct EMACBase *EMACBase, struct EMACUnit *unit, const UBYTE *lower_bound, const UBYTE *upper_bound);
 188 struct TypeStats *FindTypeStats(struct EMACBase *EMACBase, struct EMACUnit *unit,
 189                     struct MinList *list, ULONG packet_type);
 190
 191 int EMAC_miiphy_read(struct EMACUnit *unit, uint8_t reg, uint16_t *value);
 192 int EMAC_miiphy_write(struct EMACUnit *unit, uint8_t reg, uint16_t value);
 193 int EMAC_miiphy_reset(struct EMACUnit *unit);
 194 int EMAC_miiphy_speed(struct EMACUnit *unit);
 195 int EMAC_miiphy_duplex(struct EMACUnit *unit);
 196 int EMAC_miiphy_link(struct EMACUnit *unit);
 197 int EMAC_phy_setup_aneg (struct EMACUnit *unit);
 198
 199 /* PHY definitions */
 200
 201 /* phy seed setup */
 202 #define AUTO                    99
 203 #define _1000BASET              1000
 204 #define _100BASET               100
 205 #define _10BASET                10
 206 #define HALF                    22
 207 #define FULL                    44
 208
 209 /* phy register offsets */
 210 #define PHY_BMCR                0x00
 211 #define PHY_BMSR                0x01
 212 #define PHY_PHYIDR1             0x02
 213 #define PHY_PHYIDR2             0x03
 214 #define PHY_ANAR                0x04
 215 #define PHY_ANLPAR              0x05
 216 #define PHY_ANER                0x06
 217 #define PHY_ANNPTR              0x07
 218 #define PHY_ANLPNP              0x08
 219 #define PHY_1000BTCR            0x09
 220 #define PHY_1000BTSR            0x0A
 221 #define PHY_EXSR                0x0F
 222 #define PHY_PHYSTS              0x10
 223 #define PHY_MIPSCR              0x11
 224 #define PHY_MIPGSR              0x12
 225 #define PHY_DCR                 0x13
 226 #define PHY_FCSCR               0x14
 227 #define PHY_RECR                0x15
 228 #define PHY_PCSR                0x16
 229 #define PHY_LBR                 0x17
 230 #define PHY_10BTSCR             0x18
 231 #define PHY_PHYCTRL             0x19
 232
 233 /* PHY BMCR */
 234 #define PHY_BMCR_RESET          0x8000
 235 #define PHY_BMCR_LOOP           0x4000
 236 #define PHY_BMCR_100MB          0x2000
 237 #define PHY_BMCR_AUTON          0x1000
 238 #define PHY_BMCR_POWD           0x0800
 239 #define PHY_BMCR_ISO            0x0400
 240 #define PHY_BMCR_RST_NEG        0x0200
 241 #define PHY_BMCR_DPLX           0x0100
 242 #define PHY_BMCR_COL_TST        0x0080
 243
 244 #define PHY_BMCR_SPEED_MASK     0x2040
 245 #define PHY_BMCR_1000_MBPS      0x0040
 246 #define PHY_BMCR_100_MBPS       0x2000
 247 #define PHY_BMCR_10_MBPS        0x0000
 248
 249 /* phy BMSR */
 250 #define PHY_BMSR_100T4          0x8000
 251 #define PHY_BMSR_100TXF         0x4000
 252 #define PHY_BMSR_100TXH         0x2000
 253 #define PHY_BMSR_10TF           0x1000
 254 #define PHY_BMSR_10TH           0x0800
 255 #define PHY_BMSR_EXT_STAT       0x0100
 256 #define PHY_BMSR_PRE_SUP        0x0040
 257 #define PHY_BMSR_AUTN_COMP      0x0020
 258 #define PHY_BMSR_RF             0x0010
 259 #define PHY_BMSR_AUTN_ABLE      0x0008
 260 #define PHY_BMSR_LS             0x0004
 261 #define PHY_BMSR_JD             0x0002
 262 #define PHY_BMSR_EXT            0x0001
 263
 264 /*phy ANLPAR */
 265 #define PHY_ANLPAR_NP           0x8000
 266 #define PHY_ANLPAR_ACK          0x4000
 267 #define PHY_ANLPAR_RF           0x2000
 268 #define PHY_ANLPAR_ASYMP        0x0800
 269 #define PHY_ANLPAR_PAUSE        0x0400
 270 #define PHY_ANLPAR_T4           0x0200
 271 #define PHY_ANLPAR_TXFD         0x0100
 272 #define PHY_ANLPAR_TX           0x0080
 273 #define PHY_ANLPAR_10FD         0x0040
 274 #define PHY_ANLPAR_10           0x0020
 275 #define PHY_ANLPAR_100          0x0380  /* we can run at 100 */
 276 /* phy ANLPAR 1000BASE-X */
 277 #define PHY_X_ANLPAR_NP         0x8000
 278 #define PHY_X_ANLPAR_ACK        0x4000
 279 #define PHY_X_ANLPAR_RF_MASK    0x3000
 280 #define PHY_X_ANLPAR_PAUSE_MASK 0x0180
 281 #define PHY_X_ANLPAR_HD         0x0040
 282 #define PHY_X_ANLPAR_FD         0x0020
 283
 284 #define PHY_ANLPAR_PSB_MASK     0x001f
 285 #define PHY_ANLPAR_PSB_802_3    0x0001
 286 #define PHY_ANLPAR_PSB_802_9    0x0002
 287
 288 /* phy 1000BTCR */
 289 #define PHY_1000BTCR_1000FD     0x0200
 290 #define PHY_1000BTCR_1000HD     0x0100
 291
 292 /* phy 1000BTSR */
 293 #define PHY_1000BTSR_MSCF       0x8000
 294 #define PHY_1000BTSR_MSCR       0x4000
 295 #define PHY_1000BTSR_LRS        0x2000
 296 #define PHY_1000BTSR_RRS        0x1000
 297 #define PHY_1000BTSR_1000FD     0x0800
 298 #define PHY_1000BTSR_1000HD     0x0400
 299
 300 /* phy EXSR */
 301 #define PHY_EXSR_1000XF         0x8000
 302 #define PHY_EXSR_1000XH         0x4000
 303 #define PHY_EXSR_1000TF         0x2000
 304 #define PHY_EXSR_1000TH         0x1000
 305
 306
 307 #endif /*EMAC_H_*/