workbench/devs/networks/fec/fec.h

   1 /*
   2  * fec.h
   3  *
   4  *  Created on: May 15, 2009
   5  *      Author: misc
   6  */
   7
   8 #ifndef FEC_H_
   9 #define FEC_H_
  10
  11 #include <inttypes.h>
  12
  13 #include <exec/libraries.h>
  14 #include <exec/devices.h>
  15 #include <exec/semaphores.h>
  16 #include <exec/lists.h>
  17 #include <exec/interrupts.h>
  18
  19 #include <devices/sana2.h>
  20 #include <devices/sana2specialstats.h>
  21
  22 enum {
  23     WRITE_QUEUE,
  24     ADOPT_QUEUE,
  25     EVENT_QUEUE,
  26     GENERAL_QUEUE,
  27     REQUEST_QUEUE_COUNT
  28 };
  29
  30 /* Bits and pieces taken from linux */
  31
  32 typedef struct {
  33     uint32_t fec_id;                     /* FEC + 0x000 */
  34     uint32_t ievent;                     /* FEC + 0x004 */
  35     uint32_t imask;                      /* FEC + 0x008 */
  36
  37     uint32_t reserved0[1];               /* FEC + 0x00C */
  38     uint32_t r_des_active;               /* FEC + 0x010 */
  39     uint32_t x_des_active;               /* FEC + 0x014 */
  40     uint32_t r_des_active_cl;            /* FEC + 0x018 */
  41     uint32_t x_des_active_cl;            /* FEC + 0x01C */
  42     uint32_t ivent_set;                  /* FEC + 0x020 */
  43     uint32_t ecntrl;                     /* FEC + 0x024 */
  44
  45     uint32_t reserved1[6];               /* FEC + 0x028-03C */
  46     uint32_t mii_data;                   /* FEC + 0x040 */
  47     uint32_t mii_speed;                  /* FEC + 0x044 */
  48     uint32_t mii_status;                 /* FEC + 0x048 */
  49
  50     uint32_t reserved2[5];               /* FEC + 0x04C-05C */
  51     uint32_t mib_data;                   /* FEC + 0x060 */
  52     uint32_t mib_control;                /* FEC + 0x064 */
  53
  54     uint32_t reserved3[6];               /* FEC + 0x068-7C */
  55     uint32_t r_activate;                 /* FEC + 0x080 */
  56     uint32_t r_cntrl;                    /* FEC + 0x084 */
  57     uint32_t r_hash;                     /* FEC + 0x088 */
  58     uint32_t r_data;                     /* FEC + 0x08C */
  59     uint32_t ar_done;                    /* FEC + 0x090 */
  60     uint32_t r_test;                     /* FEC + 0x094 */
  61     uint32_t r_mib;                      /* FEC + 0x098 */
  62     uint32_t r_da_low;                   /* FEC + 0x09C */
  63     uint32_t r_da_high;                  /* FEC + 0x0A0 */
  64
  65     uint32_t reserved4[7];               /* FEC + 0x0A4-0BC */
  66     uint32_t x_activate;                 /* FEC + 0x0C0 */
  67     uint32_t x_cntrl;                    /* FEC + 0x0C4 */
  68     uint32_t backoff;                    /* FEC + 0x0C8 */
  69     uint32_t x_data;                     /* FEC + 0x0CC */
  70     uint32_t x_status;                   /* FEC + 0x0D0 */
  71     uint32_t x_mib;                      /* FEC + 0x0D4 */
  72     uint32_t x_test;                     /* FEC + 0x0D8 */
  73     uint32_t fdxfc_da1;                  /* FEC + 0x0DC */
  74     uint32_t fdxfc_da2;                  /* FEC + 0x0E0 */
  75     uint32_t paddr1;                     /* FEC + 0x0E4 */
  76     uint32_t paddr2;                     /* FEC + 0x0E8 */
  77     uint32_t op_pause;                   /* FEC + 0x0EC */
  78
  79     uint32_t reserved5[4];               /* FEC + 0x0F0-0FC */
  80     uint32_t instr_reg;                  /* FEC + 0x100 */
  81     uint32_t context_reg;                /* FEC + 0x104 */
  82     uint32_t test_cntrl;                 /* FEC + 0x108 */
  83     uint32_t acc_reg;                    /* FEC + 0x10C */
  84     uint32_t ones;                       /* FEC + 0x110 */
  85     uint32_t zeros;                      /* FEC + 0x114 */
  86     uint32_t iaddr1;                     /* FEC + 0x118 */
  87     uint32_t iaddr2;                     /* FEC + 0x11C */
  88     uint32_t gaddr1;                     /* FEC + 0x120 */
  89     uint32_t gaddr2;                     /* FEC + 0x124 */
  90     uint32_t random;                     /* FEC + 0x128 */
  91     uint32_t rand1;                      /* FEC + 0x12C */
  92     uint32_t tmp;                        /* FEC + 0x130 */
  93
  94     uint32_t reserved6[3];               /* FEC + 0x134-13C */
  95     uint32_t fifo_id;                    /* FEC + 0x140 */
  96     uint32_t x_wmrk;                     /* FEC + 0x144 */
  97     uint32_t fcntrl;                     /* FEC + 0x148 */
  98     uint32_t r_bound;                    /* FEC + 0x14C */
  99     uint32_t r_fstart;                   /* FEC + 0x150 */
 100     uint32_t r_count;                    /* FEC + 0x154 */
 101     uint32_t r_lag;                      /* FEC + 0x158 */
 102     uint32_t r_read;                     /* FEC + 0x15C */
 103     uint32_t r_write;                    /* FEC + 0x160 */
 104     uint32_t x_count;                    /* FEC + 0x164 */
 105     uint32_t x_lag;                      /* FEC + 0x168 */
 106     uint32_t x_retry;                    /* FEC + 0x16C */
 107     uint32_t x_write;                    /* FEC + 0x170 */
 108     uint32_t x_read;                     /* FEC + 0x174 */
 109
 110     uint32_t reserved7[2];               /* FEC + 0x178-17C */
 111     uint32_t fm_cntrl;                   /* FEC + 0x180 */
 112     uint32_t rfifo_data;                 /* FEC + 0x184 */
 113     uint32_t rfifo_status;               /* FEC + 0x188 */
 114     uint32_t rfifo_cntrl;                /* FEC + 0x18C */
 115     uint32_t rfifo_lrf_ptr;              /* FEC + 0x190 */
 116     uint32_t rfifo_lwf_ptr;              /* FEC + 0x194 */
 117     uint32_t rfifo_alarm;                /* FEC + 0x198 */
 118     uint32_t rfifo_rdptr;                /* FEC + 0x19C */
 119     uint32_t rfifo_wrptr;                /* FEC + 0x1A0 */
 120     uint32_t tfifo_data;                 /* FEC + 0x1A4 */
 121     uint32_t tfifo_status;               /* FEC + 0x1A8 */
 122     uint32_t tfifo_cntrl;                /* FEC + 0x1AC */
 123     uint32_t tfifo_lrf_ptr;              /* FEC + 0x1B0 */
 124     uint32_t tfifo_lwf_ptr;              /* FEC + 0x1B4 */
 125     uint32_t tfifo_alarm;                /* FEC + 0x1B8 */
 126     uint32_t tfifo_rdptr;                /* FEC + 0x1BC */
 127     uint32_t tfifo_wrptr;                /* FEC + 0x1C0 */
 128
 129     uint32_t reset_cntrl;                /* FEC + 0x1C4 */
 130     uint32_t xmit_fsm;                   /* FEC + 0x1C8 */
 131
 132     uint32_t reserved8[3];               /* FEC + 0x1CC-1D4 */
 133     uint32_t rdes_data0;                 /* FEC + 0x1D8 */
 134     uint32_t rdes_data1;                 /* FEC + 0x1DC */
 135     uint32_t r_length;                   /* FEC + 0x1E0 */
 136     uint32_t x_length;                   /* FEC + 0x1E4 */
 137     uint32_t x_addr;                     /* FEC + 0x1E8 */
 138     uint32_t cdes_data;                  /* FEC + 0x1EC */
 139     uint32_t status;                     /* FEC + 0x1F0 */
 140     uint32_t dma_control;                /* FEC + 0x1F4 */
 141     uint32_t des_cmnd;                   /* FEC + 0x1F8 */
 142     uint32_t data;                       /* FEC + 0x1FC */
 143
 144     uint32_t rmon_t_drop;                /* FEC + 0x200 */
 145     uint32_t rmon_t_packets;             /* FEC + 0x204 */
 146     uint32_t rmon_t_bc_pkt;              /* FEC + 0x208 */
 147     uint32_t rmon_t_mc_pkt;              /* FEC + 0x20C */
 148     uint32_t rmon_t_crc_align;           /* FEC + 0x210 */
 149     uint32_t rmon_t_undersize;           /* FEC + 0x214 */
 150     uint32_t rmon_t_oversize;            /* FEC + 0x218 */
 151     uint32_t rmon_t_frag;                /* FEC + 0x21C */
 152     uint32_t rmon_t_jab;                 /* FEC + 0x220 */
 153     uint32_t rmon_t_col;                 /* FEC + 0x224 */
 154     uint32_t rmon_t_p64;                 /* FEC + 0x228 */
 155     uint32_t rmon_t_p65to127;            /* FEC + 0x22C */
 156     uint32_t rmon_t_p128to255;           /* FEC + 0x230 */
 157     uint32_t rmon_t_p256to511;           /* FEC + 0x234 */
 158     uint32_t rmon_t_p512to1023;          /* FEC + 0x238 */
 159     uint32_t rmon_t_p1024to2047;         /* FEC + 0x23C */
 160     uint32_t rmon_t_p_gte2048;           /* FEC + 0x240 */
 161     uint32_t rmon_t_octets;              /* FEC + 0x244 */
 162     uint32_t ieee_t_drop;                /* FEC + 0x248 */
 163     uint32_t ieee_t_frame_ok;            /* FEC + 0x24C */
 164     uint32_t ieee_t_1col;                /* FEC + 0x250 */
 165     uint32_t ieee_t_mcol;                /* FEC + 0x254 */
 166     uint32_t ieee_t_def;                 /* FEC + 0x258 */
 167     uint32_t ieee_t_lcol;                /* FEC + 0x25C */
 168     uint32_t ieee_t_excol;               /* FEC + 0x260 */
 169     uint32_t ieee_t_macerr;              /* FEC + 0x264 */
 170     uint32_t ieee_t_cserr;               /* FEC + 0x268 */
 171     uint32_t ieee_t_sqe;                 /* FEC + 0x26C */
 172     uint32_t t_fdxfc;                    /* FEC + 0x270 */
 173     uint32_t ieee_t_octets_ok;           /* FEC + 0x274 */
 174
 175     uint32_t reserved9[2];               /* FEC + 0x278-27C */
 176     uint32_t rmon_r_drop;                /* FEC + 0x280 */
 177     uint32_t rmon_r_packets;             /* FEC + 0x284 */
 178     uint32_t rmon_r_bc_pkt;              /* FEC + 0x288 */
 179     uint32_t rmon_r_mc_pkt;              /* FEC + 0x28C */
 180     uint32_t rmon_r_crc_align;           /* FEC + 0x290 */
 181     uint32_t rmon_r_undersize;           /* FEC + 0x294 */
 182     uint32_t rmon_r_oversize;            /* FEC + 0x298 */
 183     uint32_t rmon_r_frag;                /* FEC + 0x29C */
 184     uint32_t rmon_r_jab;                 /* FEC + 0x2A0 */
 185
 186     uint32_t rmon_r_resvd_0;             /* FEC + 0x2A4 */
 187
 188     uint32_t rmon_r_p64;                 /* FEC + 0x2A8 */
 189     uint32_t rmon_r_p65to127;            /* FEC + 0x2AC */
 190     uint32_t rmon_r_p128to255;           /* FEC + 0x2B0 */
 191     uint32_t rmon_r_p256to511;           /* FEC + 0x2B4 */
 192     uint32_t rmon_r_p512to1023;          /* FEC + 0x2B8 */
 193     uint32_t rmon_r_p1024to2047;         /* FEC + 0x2BC */
 194     uint32_t rmon_r_p_gte2048;           /* FEC + 0x2C0 */
 195     uint32_t rmon_r_octets;              /* FEC + 0x2C4 */
 196     uint32_t ieee_r_drop;                /* FEC + 0x2C8 */
 197     uint32_t ieee_r_frame_ok;            /* FEC + 0x2CC */
 198     uint32_t ieee_r_crc;                 /* FEC + 0x2D0 */
 199     uint32_t ieee_r_align;               /* FEC + 0x2D4 */
 200     uint32_t r_macerr;                   /* FEC + 0x2D8 */
 201     uint32_t r_fdxfc;                    /* FEC + 0x2DC */
 202     uint32_t ieee_r_octets_ok;           /* FEC + 0x2E0 */
 203
 204     uint32_t reserved10[7];              /* FEC + 0x2E4-2FC */
 205
 206     uint32_t reserved11[64];             /* FEC + 0x300-3FF */
 207 } fec_t;
 208
 209 #define FEC_MIB_DISABLE                 0x80000000
 210
 211 #define FEC_IEVENT_HBERR                0x80000000
 212 #define FEC_IEVENT_BABR                 0x40000000
 213 #define FEC_IEVENT_BABT                 0x20000000
 214 #define FEC_IEVENT_GRA                  0x10000000
 215 #define FEC_IEVENT_TFINT                0x08000000
 216 #define FEC_IEVENT_MII                  0x00800000
 217 #define FEC_IEVENT_LATE_COL             0x00200000
 218 #define FEC_IEVENT_COL_RETRY_LIM        0x00100000
 219 #define FEC_IEVENT_XFIFO_UN             0x00080000
 220 #define FEC_IEVENT_XFIFO_ERROR          0x00040000
 221 #define FEC_IEVENT_RFIFO_ERROR          0x00020000
 222
 223 #define FEC_IMASK_HBERR                 0x80000000
 224 #define FEC_IMASK_BABR                  0x40000000
 225 #define FEC_IMASK_BABT                  0x20000000
 226 #define FEC_IMASK_GRA                   0x10000000
 227 #define FEC_IMASK_MII                   0x00800000
 228 #define FEC_IMASK_LATE_COL              0x00200000
 229 #define FEC_IMASK_COL_RETRY_LIM         0x00100000
 230 #define FEC_IMASK_XFIFO_UN              0x00080000
 231 #define FEC_IMASK_XFIFO_ERROR           0x00040000
 232 #define FEC_IMASK_RFIFO_ERROR           0x00020000
 233
 234 /* all but MII, which is enabled separately */
 235 #define FEC_IMASK_ENABLE        (FEC_IMASK_HBERR | FEC_IMASK_BABR | \
 236                 FEC_IMASK_BABT | FEC_IMASK_GRA | FEC_IMASK_LATE_COL | \
 237                 FEC_IMASK_COL_RETRY_LIM | FEC_IMASK_XFIFO_UN | \
 238                 FEC_IMASK_XFIFO_ERROR | FEC_IMASK_RFIFO_ERROR)
 239
 240 #define FEC_RCNTRL_MAX_FL_SHIFT         16
 241 #define FEC_RCNTRL_LOOP                 0x01
 242 #define FEC_RCNTRL_DRT                  0x02
 243 #define FEC_RCNTRL_MII_MODE             0x04
 244 #define FEC_RCNTRL_PROM                 0x08
 245 #define FEC_RCNTRL_BC_REJ               0x10
 246 #define FEC_RCNTRL_FCE                  0x20
 247
 248 #define FEC_TCNTRL_GTS                  0x00000001
 249 #define FEC_TCNTRL_HBC                  0x00000002
 250 #define FEC_TCNTRL_FDEN                 0x00000004
 251 #define FEC_TCNTRL_TFC_PAUSE            0x00000008
 252 #define FEC_TCNTRL_RFC_PAUSE            0x00000010
 253
 254 #define FEC_ECNTRL_RESET                0x00000001
 255 #define FEC_ECNTRL_ETHER_EN             0x00000002
 256
 257 #define FEC_MII_DATA_ST                 0x40000000      /* Start frame */
 258 #define FEC_MII_DATA_OP_RD              0x20000000      /* Perform read */
 259 #define FEC_MII_DATA_OP_WR              0x10000000      /* Perform write */
 260 #define FEC_MII_DATA_PA_MSK             0x0f800000      /* PHY Address mask */
 261 #define FEC_MII_DATA_RA_MSK             0x007c0000      /* PHY Register mask */
 262 #define FEC_MII_DATA_TA                 0x00020000      /* Turnaround */
 263 #define FEC_MII_DATA_DATAMSK            0x0000ffff      /* PHY data mask */
 264
 265 #define FEC_MII_READ_FRAME      (FEC_MII_DATA_ST | FEC_MII_DATA_OP_RD | FEC_MII_DATA_TA)
 266 #define FEC_MII_WRITE_FRAME     (FEC_MII_DATA_ST | FEC_MII_DATA_OP_WR | FEC_MII_DATA_TA)
 267
 268 #define FEC_MII_DATA_RA_SHIFT           0x12            /* MII reg addr bits */
 269 #define FEC_MII_DATA_PA_SHIFT           0x17            /* MII PHY addr bits */
 270
 271 #define FEC_PHYADDR_NONE                                -1
 272 #define FEC_PHYADDR_7WIRE                               -2
 273
 274 #define FEC_PADDR2_TYPE                 0x8808
 275
 276 #define FEC_OP_PAUSE_OPCODE             0x00010000
 277
 278 #define FEC_FIFO_WMRK_256B              0x3
 279
 280 #define FEC_FIFO_STATUS_ERR             0x00400000
 281 #define FEC_FIFO_STATUS_UF              0x00200000
 282 #define FEC_FIFO_STATUS_OF              0x00100000
 283
 284 #define FEC_FIFO_CNTRL_FRAME            0x08000000
 285 #define FEC_FIFO_CNTRL_LTG_7            0x07000000
 286
 287 #define FEC_RESET_CNTRL_RESET_FIFO      0x02000000
 288 #define FEC_RESET_CNTRL_ENABLE_IS_RESET 0x01000000
 289
 290 #define FEC_XMIT_FSM_APPEND_CRC         0x02000000
 291 #define FEC_XMIT_FSM_ENABLE_CRC         0x01000000
 292
 293 struct Opener
 294 {
 295     struct MinNode  node;
 296     struct MsgPort  read_port;
 297     BOOL            (*rx_function)(APTR, APTR, ULONG);
 298     BOOL            (*tx_function)(APTR, APTR, ULONG);
 299     struct Hook     *filter_hook;
 300     struct MinList  initial_stats;
 301 };
 302
 303 struct TypeStats
 304 {
 305     struct MinNode node;
 306     ULONG packet_type;
 307     struct Sana2PacketTypeStats stats;
 308 };
 309
 310 struct TypeTracker
 311 {
 312     struct MinNode node;
 313     ULONG packet_type;
 314     struct Sana2PacketTypeStats stats;
 315     ULONG user_count;
 316 };
 317
 318 struct AddressRange
 319 {
 320     struct MinNode node;
 321     ULONG add_count;
 322     ULONG lower_bound_left;
 323     ULONG upper_bound_left;
 324     UWORD lower_bound_right;
 325     UWORD upper_bound_right;
 326 };
 327
 328
 329 struct FECUnit;
 330
 331 struct FECBase {
 332         struct Device               feb_Device;
 333     struct Sana2DeviceQuery     feb_Sana2Info;
 334     void                        *feb_Pool;
 335
 336     struct FECUnit                              *feb_Unit;
 337 };
 338
 339 /* Standard interface flags (netdevice->flags). */
 340 #define IFF_UP          0x1             /* interface is up              */
 341 #define IFF_BROADCAST   0x2             /* broadcast address valid      */
 342 #define IFF_DEBUG       0x4             /* turn on debugging            */
 343 #define IFF_LOOPBACK    0x8             /* is a loopback net            */
 344 #define IFF_POINTOPOINT 0x10            /* interface is has p-p link    */
 345 #define IFF_NOTRAILERS  0x20            /* avoid use of trailers        */
 346 #define IFF_RUNNING     0x40            /* resources allocated          */
 347 #define IFF_NOARP       0x80            /* no ARP protocol              */
 348 #define IFF_PROMISC     0x100           /* receive all packets          */
 349 #define IFF_ALLMULTI    0x200           /* receive all multicast packets*/
 350
 351 #define IFF_MASTER      0x400           /* master of a load balancer    */
 352 #define IFF_SLAVE       0x800           /* slave of a load balancer     */
 353
 354 #define IFF_MULTICAST   0x1000          /* Supports multicast           */
 355
 356 #define IFF_VOLATILE    (IFF_LOOPBACK|IFF_POINTOPOINT|IFF_BROADCAST|IFF_MASTER|IFF_SLAVE|IFF_RUNNING)
 357
 358 #define IFF_PORTSEL     0x2000          /* can set media type           */
 359 #define IFF_AUTOMEDIA   0x4000          /* auto media select active     */
 360 #define IFF_DYNAMIC     0x8000          /* dialup device with changing addresses*/
 361 #define IFF_SHARED      0x10000         /* interface may be shared */
 362 #define IFF_CONFIGURED  0x20000         /* interface already configured */
 363
 364
 365 #define ETH_DATA_LEN        1500
 366 #define ETH_ADDRESSSIZE     6
 367 #define ETH_HEADERSIZE      14
 368 #define ETH_CRCSIZE         4
 369 #define ETH_MTU             (ETH_DATA_LEN)
 370 #define ETH_MAXPACKETSIZE   ((ETH_HEADERSIZE) + (ETH_MTU) + (ETH_CRCSIZE))
 371
 372 #define ETH_PACKET_DEST     0
 373 #define ETH_PACKET_SOURCE   6
 374 #define ETH_PACKET_TYPE     12
 375 #define ETH_PACKET_IEEELEN  12
 376 #define ETH_PACKET_SNAPTYPE 20
 377 #define ETH_PACKET_DATA     14
 378 #define ETH_PACKET_CRC      (ETH_PACKET_DATA + ETH_MTU)
 379
 380 #define RXTX_ALLOC_BUFSIZE  (ETH_MAXPACKETSIZE + 26)
 381
 382 /* PHY definitions */
 383
 384 /* phy seed setup */
 385 #define AUTO                    99
 386 #define _1000BASET              1000
 387 #define _100BASET               100
 388 #define _10BASET                10
 389 #define HALF                    22
 390 #define FULL                    44
 391
 392 /* phy register offsets */
 393 #define PHY_BMCR                0x00
 394 #define PHY_BMSR                0x01
 395 #define PHY_PHYIDR1             0x02
 396 #define PHY_PHYIDR2             0x03
 397 #define PHY_ANAR                0x04
 398 #define PHY_ANLPAR              0x05
 399 #define PHY_ANER                0x06
 400 #define PHY_ANNPTR              0x07
 401 #define PHY_ANLPNP              0x08
 402 #define PHY_1000BTCR            0x09
 403 #define PHY_1000BTSR            0x0A
 404 #define PHY_EXSR                0x0F
 405 #define PHY_PHYSTS              0x10
 406 #define PHY_MIPSCR              0x11
 407 #define PHY_MIPGSR              0x12
 408 #define PHY_DCR                 0x13
 409 #define PHY_FCSCR               0x14
 410 #define PHY_RECR                0x15
 411 #define PHY_PCSR                0x16
 412 #define PHY_LBR                 0x17
 413 #define PHY_10BTSCR             0x18
 414 #define PHY_PHYCTRL             0x19
 415
 416 /* PHY BMCR */
 417 #define PHY_BMCR_RESET          0x8000
 418 #define PHY_BMCR_LOOP           0x4000
 419 #define PHY_BMCR_100MB          0x2000
 420 #define PHY_BMCR_AUTON          0x1000
 421 #define PHY_BMCR_POWD           0x0800
 422 #define PHY_BMCR_ISO            0x0400
 423 #define PHY_BMCR_RST_NEG        0x0200
 424 #define PHY_BMCR_DPLX           0x0100
 425 #define PHY_BMCR_COL_TST        0x0080
 426
 427 #define PHY_BMCR_SPEED_MASK     0x2040
 428 #define PHY_BMCR_1000_MBPS      0x0040
 429 #define PHY_BMCR_100_MBPS       0x2000
 430 #define PHY_BMCR_10_MBPS        0x0000
 431
 432 /* phy BMSR */
 433 #define PHY_BMSR_100T4          0x8000
 434 #define PHY_BMSR_100TXF         0x4000
 435 #define PHY_BMSR_100TXH         0x2000
 436 #define PHY_BMSR_10TF           0x1000
 437 #define PHY_BMSR_10TH           0x0800
 438 #define PHY_BMSR_EXT_STAT       0x0100
 439 #define PHY_BMSR_PRE_SUP        0x0040
 440 #define PHY_BMSR_AUTN_COMP      0x0020
 441 #define PHY_BMSR_RF             0x0010
 442 #define PHY_BMSR_AUTN_ABLE      0x0008
 443 #define PHY_BMSR_LS             0x0004
 444 #define PHY_BMSR_JD             0x0002
 445 #define PHY_BMSR_EXT            0x0001
 446
 447 /*phy ANLPAR */
 448 #define PHY_ANLPAR_NP           0x8000
 449 #define PHY_ANLPAR_ACK          0x4000
 450 #define PHY_ANLPAR_RF           0x2000
 451 #define PHY_ANLPAR_ASYMP        0x0800
 452 #define PHY_ANLPAR_PAUSE        0x0400
 453 #define PHY_ANLPAR_T4           0x0200
 454 #define PHY_ANLPAR_TXFD         0x0100
 455 #define PHY_ANLPAR_TX           0x0080
 456 #define PHY_ANLPAR_10FD         0x0040
 457 #define PHY_ANLPAR_10           0x0020
 458 #define PHY_ANLPAR_100          0x0380  /* we can run at 100 */
 459 /* phy ANLPAR 1000BASE-X */
 460 #define PHY_X_ANLPAR_NP         0x8000
 461 #define PHY_X_ANLPAR_ACK        0x4000
 462 #define PHY_X_ANLPAR_RF_MASK    0x3000
 463 #define PHY_X_ANLPAR_PAUSE_MASK 0x0180
 464 #define PHY_X_ANLPAR_HD         0x0040
 465 #define PHY_X_ANLPAR_FD         0x0020
 466
 467 #define PHY_ANLPAR_PSB_MASK     0x001f
 468 #define PHY_ANLPAR_PSB_802_3    0x0001
 469 #define PHY_ANLPAR_PSB_802_9    0x0002
 470
 471 /* phy 1000BTCR */
 472 #define PHY_1000BTCR_1000FD     0x0200
 473 #define PHY_1000BTCR_1000HD     0x0100
 474
 475 /* phy 1000BTSR */
 476 #define PHY_1000BTSR_MSCF       0x8000
 477 #define PHY_1000BTSR_MSCR       0x4000
 478 #define PHY_1000BTSR_LRS        0x2000
 479 #define PHY_1000BTSR_RRS        0x1000
 480 #define PHY_1000BTSR_1000FD     0x0800
 481 #define PHY_1000BTSR_1000HD     0x0400
 482
 483 /* phy EXSR */
 484 #define PHY_EXSR_1000XF         0x8000
 485 #define PHY_EXSR_1000XH         0x4000
 486 #define PHY_EXSR_1000TF         0x2000
 487 #define PHY_EXSR_1000TH         0x1000
 488
 489 #define STAT_COUNT 3
 490
 491 struct FECUnit {
 492         struct Unit                             feu_Unit;
 493         struct SignalSemaphore  feu_Lock;
 494         struct MinList          feu_Openers;
 495         struct MinList          feu_MulticastRanges;
 496         struct MinList          feu_TypeTrackers;
 497         struct Process          *feu_Process;
 498         struct FECBase                  *feu_FECBase;
 499         void                    *feu_IRQHandler;
 500
 501         struct Interrupt        feu_TXInt;
 502         struct Interrupt        feu_RXInt;
 503         struct Interrupt        feu_TXEndInt;
 504
 505         struct Sana2DeviceStats feu_Stats;
 506         uint32_t                feu_SpecialStats[STAT_COUNT];
 507
 508         fec_t                                   *feu_regs;
 509
 510         uint32_t                                feu_phy_speed;
 511         int8_t                                  feu_phy_id;
 512
 513         uint16_t                                feu_speed;
 514         uint8_t                                 feu_duplex;
 515         uint8_t                                 feu_link;
 516
 517     uint8_t                     feu_DevAddr[ETH_ADDRESSSIZE];
 518     uint8_t                     feu_OrgAddr[ETH_ADDRESSSIZE];
 519
 520     uint32_t                    feu_Flags;
 521     uint32_t                    feu_OpenCount;
 522     int32_t                     feu_RangeCount;
 523
 524     struct MsgPort              *feu_RequestPorts[REQUEST_QUEUE_COUNT];
 525     struct MsgPort              *feu_InputPort;
 526
 527     struct MsgPort              feu_TimerPort;
 528     struct timerequest          feu_TimerRequest;
 529
 530     int                         (*start)(struct FECUnit *);
 531     int                         (*stop)(struct FECUnit *);
 532     void                        (*set_multicast)(struct FECUnit *);
 533     void                        (*set_mac_address)(struct FECUnit *);
 534 };
 535
 536
 537 BOOL AddMulticastRange(struct FECBase *FECBase, struct FECUnit *unit, const UBYTE *lower_bound, const UBYTE *upper_bound);
 538 BOOL RemMulticastRange(struct FECBase *FECBase, struct FECUnit *unit, const UBYTE *lower_bound, const UBYTE *upper_bound);
 539 struct TypeStats *FindTypeStats(struct FECBase *FECBase, struct FECUnit *unit, struct MinList *list, ULONG packet_type);
 540 int FEC_CreateUnit(struct FECBase *FECBase, fec_t *regs);
 541 void handle_request(struct FECBase *FECBase, struct IOSana2Req *request);
 542 void FEC_UDelay(struct FECUnit *unit, uint32_t usec);
 543 int FEC_MDIO_Read(struct FECUnit *unit, int32_t phy_id, int32_t reg);
 544 int FEC_MDIO_Write(struct FECUnit *unit, int32_t phy_id, int32_t reg, uint16_t data);
 545 void FEC_HW_Init(struct FECUnit *unit);
 546 void FEC_PHY_Init(struct FECUnit *unit);
 547 void FEC_Reset_Stats(struct FECUnit *unit);
 548 int8_t FEC_PHY_Find(struct FECUnit *unit);
 549 int FEC_PHY_Reset(struct FECUnit *unit);
 550 int FEC_PHY_Link(struct FECUnit *unit);
 551 int FEC_PHY_Speed(struct FECUnit *unit);
 552 int FEC_PHY_Duplex(struct FECUnit *unit);
 553 void FEC_PHY_Setup_Autonegotiation(struct FECUnit *unit);
 554
 555 #endif /* FEC_H_ */