workbench/devs/networks/rtl8139/rtl8139.h

   1 #ifndef _RTL8139_H
   2 #define _RTL8139_H
   3
   4 /*
   5  * $Id$
   6  */
   7
   8 /*
   9         This program is free software; you can redistribute it and/or modify
  10         it under the terms of the GNU General Public License as published by
  11         the Free Software Foundation; either version 2 of the License, or
  12         (at your option) any later version.
  13
  14         This program is distributed in the hope that it will be useful, but
  15         WITHOUT ANY WARRANTY; without even the implied warranty of
  16         MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
  17         General Public License for more details.
  18
  19         You should have received a copy of the GNU General Public License
  20         along with this program; if not, write to the Free Software
  21         Foundation, Inc., 59 Temple Place - Suite 330, Boston,
  22         MA 02111-1307, USA.
  23 */
  24
  25 #include <aros/debug.h>
  26
  27 #if DEBUG > 0
  28 #define RTL_DEBUG
  29 #endif
  30
  31 #define RTLD(d) \
  32         if (unit->rtl8139u_flags & IFF_DEBUG) \
  33         { \
  34                 d; \
  35         }
  36
  37 #include <exec/types.h>
  38 #include <exec/libraries.h>
  39 #include <exec/semaphores.h>
  40 #include <exec/devices.h>
  41 #include <exec/interrupts.h>
  42 #include <dos/bptr.h>
  43
  44 #include <oop/oop.h>
  45
  46 #include <hidd/pci.h>
  47
  48 #include <devices/timer.h>
  49 #include <devices/sana2.h>
  50 #include <devices/sana2specialstats.h>
  51
  52 #include <proto/exec.h>
  53
  54 #include LC_LIBDEFS_FILE
  55 #define LIBBASETYPEPTR struct RTL8139Base *
  56
  57 #define net_device RTL8139Unit
  58
  59 #define RTL8139_TASK_NAME       "%s.task"
  60 #define RTL8139_PORT_NAME       "%s.port"
  61
  62 /** Operational parameters that are set at compile time **/
  63 #define ETH_ZLEN  60 // Min. octets in frame sans FCS
  64
  65 // Maximum size of the in-memory receive ring (smaller if no memory)
  66 #define RX_BUF_LEN_IDX  2     // 0=8K, 1=16K, 2=32K, 3=64K
  67 #define RX_FIFO_THRESH  6    // Rx buffer level before first PCI xfer
  68 #define RX_DMA_BURST    6   // Maximum PCI burst, '4' is 256 bytes
  69
  70 // Size of the Tx bounce buffers -- must be at least (mtu+14+4)
  71 #define TX_BUF_SIZE 1536
  72 #define NUM_TX_DESC 4         // Number of Tx descriptor registers
  73 #define TX_FIFO_THRESH 256  // In bytes, rounded down to 32 byte units
  74 #define TX_DMA_BURST    6   // Calculate as 16 << val
  75
  76 /** Device Driver Structures **/
  77
  78 extern struct Library *OOPBase;
  79
  80 struct RTL8139Base
  81 {
  82     struct Device       rtl8139b_Device;
  83
  84     OOP_Object          *rtl8139b_PCI;
  85     OOP_AttrBase        rtl8139b_PCIDeviceAttrBase;
  86
  87     ULONG               rtl8139b_UnitCount;
  88     struct List         rtl8139b_Units;
  89 };
  90
  91 #undef HiddPCIDeviceAttrBase
  92 #define HiddPCIDeviceAttrBase   (LIBBASE->rtl8139b_PCIDeviceAttrBase)
  93
  94 struct RTL8139Startup
  95 {
  96     struct MsgPort           *rtl8139sm_SyncPort;
  97     struct RTL8139Unit       *rtl8139sm_Unit;
  98 };
  99
 100 enum
 101 {
 102         WRITE_QUEUE,
 103         ADOPT_QUEUE,
 104         EVENT_QUEUE,
 105         GENERAL_QUEUE,
 106         REQUEST_QUEUE_COUNT
 107 };
 108
 109 struct Opener
 110 {
 111         struct MinNode  node;
 112         struct MsgPort  read_port;
 113         BOOL            (*rx_function)(APTR, APTR, ULONG);
 114         BOOL            (*tx_function)(APTR, APTR, ULONG);
 115         struct Hook     *filter_hook;
 116         struct MinList  initial_stats;
 117 };
 118
 119 struct TypeStats
 120 {
 121         struct MinNode node;
 122         ULONG packet_type;
 123         struct Sana2PacketTypeStats stats;
 124 };
 125
 126
 127 struct TypeTracker
 128 {
 129         struct MinNode node;
 130         ULONG packet_type;
 131         struct Sana2PacketTypeStats stats;
 132         ULONG user_count;
 133 };
 134
 135
 136 struct AddressRange
 137 {
 138         struct MinNode node;
 139         ULONG add_count;
 140         ULONG lower_bound_left;
 141         ULONG upper_bound_left;
 142         UWORD lower_bound_right;
 143         UWORD upper_bound_right;
 144 };
 145
 146 /* Big endian: should work, but is untested */
 147
 148 struct rx_ring_desc
 149 {
 150         IPTR    PacketBuffer;
 151         UWORD   BufferLength;
 152         UWORD   BufferStatus;
 153         ULONG   BufferMsgLength;
 154         ULONG   Reserved;
 155 };
 156
 157 struct tx_ring_desc
 158 {
 159         IPTR    PacketBuffer;
 160         UWORD   BufferLength;
 161         UWORD   BufferStatus;
 162         ULONG   Misc;
 163         ULONG   Reserved;
 164 };
 165
 166 #define STAT_COUNT 3
 167
 168 struct RTL8139Unit {
 169         struct MinNode          rtl8139u_Node;
 170
 171         struct RTL8139Base    *rtl8139u_device;
 172
 173         STRPTR                  rtl8139u_name;
 174
 175         ULONG                   rtl8139u_UnitNum;
 176         IPTR                    rtl8139u_DriverFlags;
 177
 178         OOP_Object              *rtl8139u_PCIDevice;
 179         OOP_Object              *rtl8139u_PCIDriver;
 180         IPTR                    rtl8139u_IRQ;
 181
 182         int                     rtl8139u_open_count;
 183         struct SignalSemaphore  rtl8139u_unit_lock;
 184
 185         LONG                    rtl8139u_range_count;
 186         struct MinList          rtl8139u_Openers;
 187         struct MinList          rtl8139u_multicast_ranges;
 188         struct MinList          rtl8139u_type_trackers;
 189
 190         struct timeval          rtl8139u_toutPOLL;
 191         BOOL                    rtl8139u_toutNEED;
 192         BOOL                    rtl8139u_IntsAdded;
 193
 194         struct MsgPort          *rtl8139u_TimerSlowPort;
 195         struct timerequest      *rtl8139u_TimerSlowReq;
 196
 197         struct MsgPort          *rtl8139u_TimerFastPort;
 198         struct timerequest      *rtl8139u_TimerFastReq;
 199
 200         ULONG                   rtl8139u_mtu;
 201         ULONG                   rtl8139u_flags;
 202         struct Sana2DeviceQuery  rtl8139u_Sana2Info;
 203         struct Sana2DeviceStats rtl8139u_stats;
 204         ULONG                   rtl8139u_special_stats[STAT_COUNT];
 205
 206         char                    *rtl8139u_rtl_cardname;
 207         char                    *rtl8139u_rtl_chipname;
 208         ULONG                  rtl8139u_rtl_chipcapabilities;
 209
 210         ULONG                  rtl8139u_rtl_LinkSpeed;
 211 #define support_fdx     (1 << 0) // Supports Full Duplex
 212 #define support_mii     (1 << 1)
 213 #define support_fset    (1 << 2)
 214 #define support_ltint   (1 << 3)
 215 #define support_dxsuflo (1 << 4)
 216 /* Card Funcs */
 217         void                    (*initialize)(struct RTL8139Unit *);
 218         void                    (*deinitialize)(struct RTL8139Unit *);
 219         int                     (*start)(struct RTL8139Unit *);
 220         int                     (*stop)(struct RTL8139Unit *);
 221         int                     (*alloc_rx)(struct RTL8139Unit *);
 222         void                    (*set_mac_address)(struct RTL8139Unit *);
 223         void                    (*linkchange)(struct RTL8139Unit *);
 224         void                    (*linkirq)(struct RTL8139Unit *);
 225 //    ULONG                   (*descr_getlength)(struct ring_desc *prd, ULONG v);
 226         void                    (*set_multicast)(struct RTL8139Unit *);
 227
 228         struct Process          *rtl8139u_Process;
 229
 230         struct Interrupt        rtl8139u_irqhandler;
 231         struct Interrupt        rtl8139u_touthandler;
 232         IPTR                    rtl8139u_DeviceID;
 233         APTR                    rtl8139u_BaseMem;
 234         IPTR                    rtl8139u_SizeMem;
 235         IPTR                      rtl8139u_BaseIO;
 236
 237         BYTE                    rtl8139u_signal_0;
 238         BYTE                    rtl8139u_signal_1;
 239         BYTE                    rtl8139u_signal_2;
 240         BYTE                    rtl8139u_signal_3;
 241
 242         struct MsgPort          *rtl8139u_input_port;
 243
 244         struct MsgPort          *rtl8139u_request_ports[REQUEST_QUEUE_COUNT];
 245
 246         struct Interrupt        rtl8139u_rx_int;
 247         struct Interrupt        rtl8139u_tx_int;
 248
 249         ULONG                   rtl8139u_state;
 250         APTR                    rtl8139u_mc_list;
 251         UBYTE                   rtl8139u_dev_addr[6];
 252         UBYTE                   rtl8139u_org_addr[6];
 253         struct fe_priv          *rtl8139u_fe_priv;
 254 };
 255
 256 void handle_request(LIBBASETYPEPTR, struct IOSana2Req *);
 257
 258 /* Media selection options. */
 259 enum
 260 {
 261                 IF_PORT_UNKNOWN = 0,
 262                 IF_PORT_10BASE2,
 263                 IF_PORT_10BASET,
 264                 IF_PORT_AUI,
 265                 IF_PORT_100BASET,
 266                 IF_PORT_100BASETX,
 267                 IF_PORT_100BASEFX
 268 };
 269
 270 /* Standard interface flags (netdevice->flags). */
 271 #define IFF_UP          0x1             /* interface is up              */
 272 #define IFF_BROADCAST   0x2             /* broadcast address valid      */
 273 #define IFF_DEBUG       0x4             /* turn on debugging            */
 274 #define IFF_LOOPBACK    0x8             /* is a loopback net            */
 275 #define IFF_POINTOPOINT 0x10            /* interface is has p-p link    */
 276 #define IFF_NOTRAILERS  0x20            /* avoid use of trailers        */
 277 #define IFF_RUNNING     0x40            /* resources allocated          */
 278 #define IFF_NOARP       0x80            /* no ARP protocol              */
 279 #define IFF_PROMISC     0x100           /* receive all packets          */
 280 #define IFF_ALLMULTI    0x200           /* receive all multicast packets*/
 281
 282 #define IFF_MASTER      0x400           /* master of a load balancer    */
 283 #define IFF_SLAVE       0x800           /* slave of a load balancer     */
 284
 285 #define IFF_MULTICAST   0x1000          /* Supports multicast           */
 286
 287 #define IFF_VOLATILE    (IFF_LOOPBACK|IFF_POINTOPOINT|IFF_BROADCAST|IFF_MASTER|IFF_SLAVE|IFF_RUNNING)
 288
 289 #define IFF_PORTSEL     0x2000          /* can set media type           */
 290 #define IFF_AUTOMEDIA   0x4000          /* auto media select active     */
 291 #define IFF_DYNAMIC     0x8000          /* dialup device with changing addresses*/
 292 #define IFF_SHARED      0x10000         /* interface may be shared */
 293 #define IFF_CONFIGURED  0x20000         /* interface already configured */
 294
 295 /*
 296  *      We tag multicasts with these structures.
 297  */
 298
 299 #define MAX_ADDR_LEN    32
 300
 301 struct dev_mc_list
 302 {
 303         struct dev_mc_list      *next;
 304         UBYTE                   dmi_addr[MAX_ADDR_LEN];
 305         unsigned char           dmi_addrlen;
 306         int                     dmi_users;
 307         int                     dmi_gusers;
 308 };
 309
 310 struct fe_priv {
 311         struct RTL8139Unit      *pci_dev;
 312         int                     in_shutdown;
 313         ULONG                   linkspeed;
 314         int                     duplex;
 315         int                     autoneg;
 316         int                     fixed_mode;
 317         int                     phyaddr;
 318         int                     wolenabled;
 319         unsigned int            phy_oui;
 320         UWORD                   gigabit;
 321         ULONG                   desc_ver;
 322         struct SignalSemaphore  lock;
 323
 324         IPTR                    ring_addr;
 325
 326 /* Start - rtl new */
 327         int                     full_duplex;
 328
 329         char                    mii_phys[4]; //MII device address
 330         unsigned short          advertising;  //NWay media advertising
 331
 332         unsigned int            rx_config;
 333         UBYTE                   *rx_buffer;
 334         unsigned int            rx_buf_len;
 335         unsigned int            rx_current;
 336
 337         ULONG                   tx_flag;
 338         UBYTE                   *tx_buffer;
 339         unsigned char           *tx_pbuf[NUM_TX_DESC];
 340         unsigned char           *tx_buf[NUM_TX_DESC];
 341         unsigned int            tx_dirty;
 342         unsigned int            tx_current;
 343 /* End - rtl new */
 344
 345         unsigned short          cur_rx;
 346         ULONG                   refill_rx;
 347
 348         ULONG                   next_tx, nic_tx;
 349         ULONG                   tx_flags;
 350
 351         ULONG                   irqmask;
 352         ULONG                   need_linktimer;
 353         struct  timeval         link_timeout;
 354         UBYTE                   orig_mac[6];
 355 };
 356
 357 #define pci_name(unit)  (unit->rtl8139u_name)
 358
 359 /* ENET defines */
 360
 361 #define HZ                  1000000
 362 #define ETH_DATA_LEN        1500
 363
 364 #define ETH_ADDRESSSIZE     6
 365 #define ETH_HEADERSIZE      14
 366 #define ETH_CRCSIZE         4
 367 #define ETH_MTU             (ETH_DATA_LEN)
 368 #define ETH_MAXPACKETSIZE   ((ETH_HEADERSIZE) + (ETH_MTU) + (ETH_CRCSIZE))
 369
 370 #define ETH_PACKET_DEST     0
 371 #define ETH_PACKET_SOURCE   6
 372 #define ETH_PACKET_TYPE     12
 373 #define ETH_PACKET_IEEELEN  12
 374 #define ETH_PACKET_SNAPTYPE 20
 375 #define ETH_PACKET_DATA     14
 376 #define ETH_PACKET_CRC      (ETH_PACKET_DATA + ETH_MTU)
 377
 378 #define RXTX_ALLOC_BUFSIZE  (ETH_MAXPACKETSIZE + 26)
 379
 380 #define TX_LIMIT_STOP   63
 381 #define TX_LIMIT_START  62
 382
 383 struct eth_frame {
 384         UBYTE eth_packet_dest[6];
 385         UBYTE eth_packet_source[6];
 386         UWORD eth_packet_type;
 387         UBYTE eth_packet_data[ETH_MTU];
 388         UBYTE eth_packet_crc[4];
 389         UBYTE eth_pad[RXTX_ALLOC_BUFSIZE - ETH_MAXPACKETSIZE];
 390 } __attribute__((packed));
 391 #define eth_packet_ieeelen eth_packet_type
 392
 393 void rtl8139nic_get_functions(struct RTL8139Unit *Unit);
 394
 395 /* ***************************** */
 396 /*       RTL8139 DEFINES         */
 397 /* ***************************** */
 398
 399 enum rtl_boardcapabilities
 400 {
 401   RTLc_HAS_MII_XCVR    = 0x01,
 402   RTLc_HAS_CHIP_XCVR   = 0x02,
 403   RTLc_HAS_LNK_CHNG    = 0x04,
 404   RTLc_HAS_DESC        = 0x08
 405 };
 406
 407 // Symbolic offsets to registers
 408
 409 enum rtl_registers
 410 {
 411   RTLr_MAC0             = 0x00,       // Ethernet hardware address
 412   RTLr_MAR0             = 0x08,       // Multicast filter
 413   RTLr_TxStatus0        = 0x10,       // Transmit status (Four 32bit registers)
 414   RTLr_TxStatus1                = 0x14,
 415   RTLr_TxStatus2                = 0x18,
 416   RTLr_TxStatus3                = 0x1C,
 417   RTLr_TxAddr0          = 0x20,       // Tx descriptors (also four 32bit)
 418   RTLr_TxAddr1                  = 0x24,
 419   RTLr_TxAddr2                  = 0x28,
 420   RTLr_TxAddr3                  = 0x2c,
 421   RTLr_RxBuf            = 0x30,
 422   RTLr_RxEarlyCnt       = 0x34,
 423   RTLr_RxEarlyStatus    = 0x36,
 424   RTLr_ChipCmd          = 0x37,
 425   RTLr_RxBufPtr         = 0x38,
 426   RTLr_RxBufAddr        = 0x3A,
 427   RTLr_IntrMask         = 0x3C,
 428   RTLr_IntrStatus       = 0x3E,
 429   RTLr_TxConfig         = 0x40,
 430   RTLr_RxConfig         = 0x44,
 431   RTLr_Timer            = 0x48,        // A general-purpose counter
 432   RTLr_RxMissed         = 0x4C,        // 24 bits valid, write clears
 433   RTLr_Cfg9346          = 0x50,
 434   RTLr_Config0          = 0x51,
 435   RTLr_Config1          = 0x52,
 436   RTLr_FlashReg         = 0x54,            // Timer Interrupt Register ?
 437   RTLr_GPPinData        = 0x58,            // Media status register ?
 438   RTLr_GPPinDir         = 0x59,            // Configuration register 3
 439   RTLr_MII_SMI          = 0x5A,            // Configuration register 4
 440   RTLr_HltClk           = 0x5B,            // Reserved
 441   RTLr_MultiIntr        = 0x5C,
 442   RTLr_RERID                    = 0x5E,
 443   RTLr_TxSummary        = 0x60,            // Transmit status of all descriptors
 444   RTLr_MII_BMCR         = 0x62,            // Basic mode control register
 445   RTLr_MII_BMSR         = 0x64,            // Basic mode status register
 446   RTLr_NWayAdvert       = 0x66,            // Auto negociation expansion register
 447   RTLr_NWayLPAR         = 0x68,            // Auto negociation link partner register
 448   RTLr_NWayExpansion    = 0x6A,            // Auto negociation expansion register
 449   RTLr_DIS                              = 0x6C,            // Disconnect counter
 450   RTLr_FCSC                             = 0x6E,            // False carrier sense counter
 451
 452   // Undocumented registers, but required for proper operation
 453   RTLr_FIFOTMS          = 0x70,        // FIFO Control and test (N-way tezt register)
 454   RTLr_CSCR             = 0x74,        // Chip Status and Configuration Register
 455   RTLr_PARA78           = 0x78,            // PHY parameter 1
 456   RTLr_PARA7c           = 0x7c,        // Magic transceiver parameter register (Twister parameter)
 457 };
 458
 459 enum rtl_chipclearbitmasks
 460 {
 461   MultiIntrClear = 0xf000,
 462   CmdClear  = 0xe2,
 463   ConfigClear = (1 << 7) | (1 << 6) | (1 << 3) | (1 << 2) | (1 << 1)
 464 };
 465
 466 enum rtl_chipcmdbits
 467 {
 468   RxBufEmpty = 0x01,
 469   CmdTxEnb   = 0x04,
 470   CmdRxEnb   = 0x08,
 471   CmdReset   = 0x10,
 472 };
 473
 474 // Interrupt register bits
 475
 476 enum rtl_intrstatusbits
 477 {
 478   RxOK       = 0x0001,
 479   RxErr      = 0x0002,
 480   TxOK       = 0x0004,
 481   TxErr      = 0x0008,
 482   RxOverflow = 0x0010,
 483   RxUnderrun = 0x0020,
 484   RxFIFOOver = 0x0040,
 485   PCSTimeout = 0x4000,
 486   PCIErr     = 0x8000,
 487 };
 488
 489 #define RxAckBits (RxFIFOOver | RxOverflow | RxOK)
 490
 491 enum rtl_txstatusbits
 492 {
 493   TxHostOwns    = 0x00002000,
 494   TxUnderrun    = 0x00004000,
 495   TxStatOK      = 0x00008000,
 496   TxOutOfWindow = 0x20000000,
 497   TxAborted     = 0x40000000,
 498   TxCarrierLost = 0x80000000,
 499 };
 500
 501 enum rtl_rxstatusbits
 502 {
 503   RxStatusOK  = 0x0001,
 504   RxBadAlign  = 0x0002,
 505   RxCRCErr    = 0x0004,
 506   RxTooLong   = 0x0008,
 507   RxRunt      = 0x0010,
 508   RxBadSymbol = 0x0020,
 509   RxBroadcast = 0x2000,
 510   RxPhysical  = 0x4000,
 511   RxMulticast = 0x8000,
 512 };
 513
 514 // Bits in RxConfig
 515
 516 enum rtl_rxconfigbits
 517 {
 518   AcceptAllPhys   = 0x01,
 519   AcceptMyPhys    = 0x02,
 520   AcceptMulticast = 0x04,
 521   AcceptRunt      = 0x10,
 522   AcceptErr       = 0x20,
 523   AcceptBroadcast = 0x08,
 524 };
 525
 526 enum rtl_txconfigbits
 527 {
 528         /* Interframe Gap Time. Only TxIFG96 doesnt violate IEEE 802.3 */
 529         TxIFGShift = 24,
 530         TxIFG84 = (0<<TxIFGShift), /* 8.4us / 840ns */
 531         TxIFG88 = (1<<TxIFGShift), /* 8.8us / 880ns */
 532         TxIFG92 = (2<<TxIFGShift), /* 9.2us / 920ns */
 533         TxIFG96 = (3<<TxIFGShift), /* 9.6us / 960ns */
 534
 535         TxLoopBack = (1<<18) | (1<<17),  /* Enable loopback test mode */
 536         TxCRC          = (1<<16),                  /* Disable appending CRC to end of Tx Packet */
 537         TxClearAbt   = (1<<0),                    /* Clear abort (WO) */
 538         TxDMAShift = 8,                               /* DMA burst value (0-7) is shifted this many bits */
 539         TxRetryShift = 4,                              /* TXRR value (0-15) is shifted this many bits */
 540
 541         TxVersionMask = 0x7c800000        /* Mask out version bits 30-26, 23 */
 542 };
 543
 544
 545 enum rtl_config1bits
 546 {
 547         Cfg1_PM_Enable    = 0x01,
 548         Cfg1_VPD_Enable  = 0x02,
 549         Cfg1_PIO               = 0x04,
 550         Cfg1_MMIO           = 0x08,
 551         LWAKE                  = 0x10,               /* Not on 8139/8139A */
 552         Cfg1_Driver_Load = 0x20,
 553         Cfg1_LED0            = 0x40,
 554         Cfg1_LED1            = 0x80
 555 };
 556
 557 enum rtl_cscrbits
 558 {
 559   CSCR_LinkOKBit      = 0x00400,
 560   CSCR_LinkDownOffCmd = 0x003c0,
 561   CSCR_LinkChangeBit  = 0x00800,
 562   CSCR_LinkStatusBits = 0x0f000,
 563   CSCR_LinkDownCmd    = 0x0f3c0,
 564 };
 565
 566 /** Serial EEPROM section **/
 567
 568 //  EEPROM_Ctrl bits
 569
 570 #define EE_SHIFT_CLK      0x04  // EEPROM shift clock
 571 #define EE_CS                  0x08  // EEPROM chip select
 572 #define EE_DATA_WRITE   0x02  // EEPROM chip data in
 573 #define EE_WRITE_0         0x00
 574 #define EE_WRITE_1         0x02
 575 #define EE_DATA_READ    0x01  // EEPROM chip data out
 576 #define EE_ENB               (0x80 | EE_CS)
 577
 578 // Delay between EEPROM clock transitions.
 579 // No extra delay is needed with 33Mhz PCI, but 66Mhz may change this.
 580
 581 #define eeprom_delay(ee_addr)  LONGIN(ee_addr)
 582
 583 // The EEPROM commands include the alway-set leading bit
 584
 585 #define EE_WRITE_CMD  (5)
 586 #define EE_READ_CMD   (6)
 587 #define EE_ERASE_CMD  (7)
 588
 589 /** MII serial management **/
 590
 591 // Read and write the MII management registers using software-generated
 592 // serial MDIO protocol.
 593 // The maximum data clock rate is 2.5 Mhz.  The minimum timing is usually
 594 // met by back-to-back PCI I/O cycles, but we insert a delay to avoid
 595 // "overclocking" issues
 596
 597 #define MDIO_DIR              0x80
 598 #define MDIO_DATA_OUT  0x04
 599 #define MDIO_DATA_IN      0x02
 600 #define MDIO_CLK             0x01
 601 #define MDIO_WRITE0       (MDIO_DIR)
 602 #define MDIO_WRITE1       (MDIO_DIR | MDIO_DATA_OUT)
 603
 604 #define mdio_delay(mdio_addr) LONGIN(mdio_addr)
 605
 606 int rtl8139nic_set_rxmode(struct net_device *dev);
 607
 608 #endif