1 #include "rtl8168_hw.h"
3 void rtl8168cp_hw_phy_config(struct net_device
*unit
)
5 struct phy_reg phy_reg_init
[] =
14 rtl_phy_write(unit
, phy_reg_init
, ARRAY_SIZE(phy_reg_init
));
17 void rtl8168c_hw_phy_config(struct net_device
*unit
)
19 struct phy_reg phy_reg_init
[] =
37 rtl_phy_write(unit
, phy_reg_init
, ARRAY_SIZE(phy_reg_init
));
40 void rtl8168cx_hw_phy_config(struct net_device
*unit
)
42 struct phy_reg phy_reg_init
[] =
54 rtl_phy_write(unit
, phy_reg_init
, ARRAY_SIZE(phy_reg_init
));
57 void rtl_hw_start_8168(struct net_device
*unit
)
59 struct rtl8169_priv
*np
= get_pcnpriv(unit
);
60 APTR base
= get_hwbase(unit
);
63 RTL_W8(base
+ Cfg9346
, Cfg9346_Unlock
);
65 RTL_W8(base
+ EarlyTxThres
, EarlyTxThld
);
67 rtl_set_rx_max_size(unit
);
69 rtl_set_rx_tx_config_registers(unit
);
71 np
->cp_cmd
|= RTL_R16(base
+ CPlusCmd
) | PktCntrDisable
| INTT_1
;
73 RTL_W16(base
+ CPlusCmd
, np
->cp_cmd
);
75 /* Tx performance tweak. */
76 ctl
= HIDD_PCIDevice_ReadConfigByte(unit
->rtl8169u_PCIDevice
, 0x69);
77 ctl
= (ctl
& ~0x70) | 0x50;
78 HIDD_PCIDevice_WriteConfigByte(unit
->rtl8169u_PCIDevice
, 0x69, ctl
);
80 RTL_W16(base
+ IntrMitigate
, 0x5151);
82 rtl_set_rx_tx_desc_registers(unit
);
84 RTL_W8(base
+ Cfg9346
, Cfg9346_Lock
);
86 RTL_R8(base
+ IntrMask
);
88 RTL_W32(base
+ RxMissed
, 0);
90 rtl_set_rx_mode(unit
);
92 RTL_W8(base
+ ChipCmd
, CmdTxEnb
| CmdRxEnb
);
94 RTL_W16(base
+ MultiIntr
, RTL_R16(base
+ MultiIntr
) & 0xF000);
96 /* Work around for RxFIFO overflow. */
97 if (np
->mcfg
== RTL_GIGA_MAC_VER_11
)
99 np
->intr_event
|= RxFIFOOver
| PCSTimeout
;
100 np
->intr_event
&= ~RxOverflow
;
102 RTL_W16(base
+ IntrMask
, np
->intr_event
);