workbench/devs/networks/rtl8169/rtl8169_hw.c

   1 #include "rtl8169_hw.h"
   2
   3 UBYTE *get_hwbase(struct net_device *unit);
   4 struct rtl8169_priv *get_pcnpriv(struct net_device *unit);
   5
   6 void rtl8169_set_magic_reg(struct net_device *unit, unsigned mac_version)
   7 {
   8     APTR base = get_hwbase(unit);
   9         struct
  10         {
  11                 ULONG mac_version;
  12                 ULONG clk;
  13                 ULONG val;
  14         } cfg2_info [] =
  15         {
  16                 { RTL_GIGA_MAC_VER_05, PCI_Clock_33MHz, 0x000fff00 }, // 8110SCd
  17                 { RTL_GIGA_MAC_VER_05, PCI_Clock_66MHz, 0x000fffff },
  18                 { RTL_GIGA_MAC_VER_06, PCI_Clock_33MHz, 0x00ffff00 }, // 8110SCe
  19                 { RTL_GIGA_MAC_VER_06, PCI_Clock_66MHz, 0x00ffffff }
  20         }, *p = cfg2_info;
  21         unsigned int i;
  22         ULONG clk;
  23
  24         clk = RTL_R8(base + Config2) & PCI_Clock_66MHz;
  25         for (i = 0; i < ARRAY_SIZE(cfg2_info); i++, p++)
  26     {
  27                 if ((p->mac_version == mac_version) && (p->clk == clk))
  28                 {
  29                         RTL_W32(base + 0x7c, p->val);
  30                         break;
  31                 }
  32         }
  33 }
  34
  35 unsigned int rtl8169_tbi_link_ok(struct net_device *unit)
  36 {
  37     APTR base = get_hwbase(unit);
  38
  39         return RTL_R32(base + TBICSR) & TBILinkOk;
  40 }
  41
  42 unsigned int rtl8169_xmii_link_ok(struct net_device *unit)
  43 {
  44     APTR base = get_hwbase(unit);
  45
  46         return RTL_R8(base + PHYstatus) & LinkStatus;
  47 }
  48
  49 void rtl8169_tbi_reset_enable(struct net_device *unit)
  50 {
  51     APTR base = get_hwbase(unit);
  52
  53         RTL_W32(base + TBICSR, RTL_R32(base + TBICSR) | TBIReset);
  54 }
  55
  56 void rtl8169_xmii_reset_enable(struct net_device *unit)
  57 {
  58         unsigned int val;
  59
  60         val = mdio_read(unit, MII_BMCR) | BMCR_RESET;
  61         mdio_write(unit, MII_BMCR, val & 0xffff);
  62 }
  63
  64 unsigned int rtl8169_tbi_reset_pending(struct net_device *unit)
  65 {
  66     APTR base = get_hwbase(unit);
  67
  68         return RTL_R32(base + TBICSR) & TBIReset;
  69 }
  70
  71 unsigned int rtl8169_xmii_reset_pending(struct net_device *unit)
  72 {
  73         return mdio_read(unit, MII_BMCR) & BMCR_RESET;
  74 }
  75
  76 void rtl8169s_hw_phy_config(struct net_device *unit)
  77 {
  78         struct
  79         {
  80                 UWORD regs[5]; /* Beware of bit-sign propagation */
  81         } phy_magic[5] =
  82         { {
  83                 { 0x0000,       //w 4 15 12 0
  84                   0x00a1,       //w 3 15 0 00a1
  85                   0x0008,       //w 2 15 0 0008
  86                   0x1020,       //w 1 15 0 1020
  87                   0x1000 } },{  //w 0 15 0 1000
  88                 { 0x7000,       //w 4 15 12 7
  89                   0xff41,       //w 3 15 0 ff41
  90                   0xde60,       //w 2 15 0 de60
  91                   0x0140,       //w 1 15 0 0140
  92                   0x0077 } },{  //w 0 15 0 0077
  93                 { 0xa000,       //w 4 15 12 a
  94                   0xdf01,       //w 3 15 0 df01
  95                   0xdf20,       //w 2 15 0 df20
  96                   0xff95,       //w 1 15 0 ff95
  97                   0xfa00 } },{  //w 0 15 0 fa00
  98                 { 0xb000,       //w 4 15 12 b
  99                   0xff41,       //w 3 15 0 ff41
 100                   0xde20,       //w 2 15 0 de20
 101                   0x0140,       //w 1 15 0 0140
 102                   0x00bb } },{  //w 0 15 0 00bb
 103                 { 0xf000,       //w 4 15 12 f
 104                   0xdf01,       //w 3 15 0 df01
 105                   0xdf20,       //w 2 15 0 df20
 106                   0xff95,       //w 1 15 0 ff95
 107                   0xbf00 }      //w 0 15 0 bf00
 108                 }
 109         }, *p = phy_magic;
 110         unsigned int i;
 111
 112         mdio_write(unit, 0x1f, 0x0001);         //w 31 2 0 1
 113         mdio_write(unit, 0x15, 0x1000);         //w 21 15 0 1000
 114         mdio_write(unit, 0x18, 0x65c7);         //w 24 15 0 65c7
 115         rtl8169_write_gmii_reg_bit(unit, 4, 11, 0);     //w 4 11 11 0
 116
 117         for (i = 0; i < ARRAY_SIZE(phy_magic); i++, p++)
 118         {
 119                 int val, pos = 4;
 120
 121                 val = (mdio_read(unit, pos) & 0x0fff) | (p->regs[0] & 0xffff);
 122                 mdio_write(unit, pos, val);
 123                 while (--pos >= 0)
 124                 {
 125                         mdio_write(unit, pos, p->regs[4 - pos] & 0xffff);
 126         }
 127                 rtl8169_write_gmii_reg_bit(unit, 4, 11, 1); //w 4 11 11 1
 128                 rtl8169_write_gmii_reg_bit(unit, 4, 11, 0); //w 4 11 11 0
 129         }
 130         mdio_write(unit, 0x1f, 0x0000); //w 31 2 0 0
 131 }
 132
 133 void rtl8169sb_hw_phy_config(struct net_device *unit)
 134 {
 135         struct phy_reg phy_reg_init[] =
 136         {
 137                 { 0x1f, 0x0002 },
 138                 { 0x01, 0x90d0 },
 139                 { 0x1f, 0x0000 }
 140         };
 141
 142         rtl_phy_write(unit, phy_reg_init, ARRAY_SIZE(phy_reg_init));
 143 }
 144
 145 void rtl_hw_start_8169(struct net_device *unit)
 146 {
 147     struct rtl8169_priv *np = get_pcnpriv(unit);
 148     APTR base = get_hwbase(unit);
 149
 150     // UBYTE device_control;
 151     // UWORD ephy_data;
 152     // ULONG csi_tmp;
 153
 154     RTLD(bug("[%s] rtl8169nic_HWStart_8169()\n", unit->rtl8169u_name))
 155         if (np->mcfg == RTL_GIGA_MAC_VER_05)
 156         {
 157                 RTL_W16(base + CPlusCmd, RTL_R16(base + CPlusCmd) | PCIMulRW);
 158                 HIDD_PCIDevice_WriteConfigByte(unit->rtl8169u_PCIDevice, PCI_CACHE_LINE_SIZE, 0x08);
 159         }
 160
 161     RTL_W8(base + (Cfg9346), Cfg9346_Unlock);
 162
 163         if ((np->mcfg == RTL_GIGA_MAC_VER_01) ||
 164             (np->mcfg == RTL_GIGA_MAC_VER_02) ||
 165             (np->mcfg == RTL_GIGA_MAC_VER_03) ||
 166             (np->mcfg == RTL_GIGA_MAC_VER_04))
 167         {
 168                 RTL_W8(base + (ChipCmd), CmdTxEnb | CmdRxEnb);
 169     }
 170
 171     RTL_W8(base + (EarlyTxThres), EarlyTxThld);
 172
 173     rtl_set_rx_max_size(unit);
 174
 175         if ((np->mcfg == RTL_GIGA_MAC_VER_01) ||
 176             (np->mcfg == RTL_GIGA_MAC_VER_02) ||
 177             (np->mcfg == RTL_GIGA_MAC_VER_03) ||
 178             (np->mcfg == RTL_GIGA_MAC_VER_04))
 179         {
 180                 rtl_set_rx_tx_config_registers(unit);
 181     }
 182
 183     np->cp_cmd |= rtl_rw_cpluscmd(unit) | PCIMulRW;
 184
 185         if ((np->mcfg == RTL_GIGA_MAC_VER_02) ||
 186             (np->mcfg == RTL_GIGA_MAC_VER_03))
 187     {
 188                 np->cp_cmd |= (1 << 14);
 189         }
 190
 191         RTL_W16(base + CPlusCmd, np->cp_cmd);
 192
 193         rtl8169_set_magic_reg(unit, np->mcfg);
 194
 195         /*
 196          * Undocumented corner. Supposedly:
 197          * (TxTimer << 12) | (TxPackets << 8) | (RxTimer << 4) | RxPackets
 198          */
 199     RTL_W16(base + (IntrMitigate), 0);
 200
 201         rtl_set_rx_tx_desc_registers(unit);
 202
 203         if ((np->mcfg != RTL_GIGA_MAC_VER_01) &&
 204             (np->mcfg != RTL_GIGA_MAC_VER_02) &&
 205             (np->mcfg != RTL_GIGA_MAC_VER_03) &&
 206             (np->mcfg != RTL_GIGA_MAC_VER_04))
 207         {
 208                 RTL_W8(base + ChipCmd, CmdTxEnb | CmdRxEnb);
 209                 rtl_set_rx_tx_config_registers(unit);
 210         }
 211
 212         RTL_W8(base + Cfg9346, Cfg9346_Lock);
 213
 214         /* Initially a 10 us delay. Turned it into a PCI commit. - FR */
 215         RTL_R8(base + IntrMask);
 216
 217         RTL_W32(base + RxMissed, 0);
 218
 219         rtl_set_rx_mode(unit);
 220
 221         /* no early-rx interrupts */
 222         RTL_W16(base + MultiIntr, RTL_R16(base + MultiIntr) & 0xF000);
 223
 224         /* Enable all known interrupts by setting the interrupt mask. */
 225         RTL_W16(base + IntrMask, np->intr_event);
 226 }