2 Copyright © 2004-2017, The AROS Development Team. All rights reserved.
5 Desc: nvidia.hidd initialization
9 /***************************************************************************\
11 |* Copyright 2003 NVIDIA, Corporation. All rights reserved. *|
13 |* NOTICE TO USER: The source code is copyrighted under U.S. and *|
14 |* international laws. Users and possessors of this source code are *|
15 |* hereby granted a nonexclusive, royalty-free copyright license to *|
16 |* use this code in individual and commercial software. *|
18 |* Any use of this source code must include, in the user documenta- *|
19 |* tion and internal comments to the code, notices to the end user *|
22 |* Copyright 2003 NVIDIA, Corporation. All rights reserved. *|
24 |* NVIDIA, CORPORATION MAKES NO REPRESENTATION ABOUT THE SUITABILITY *|
25 |* OF THIS SOURCE CODE FOR ANY PURPOSE. IT IS PROVIDED "AS IS" *|
26 |* WITHOUT EXPRESS OR IMPLIED WARRANTY OF ANY KIND. NVIDIA, CORPOR- *|
27 |* ATION DISCLAIMS ALL WARRANTIES WITH REGARD TO THIS SOURCE CODE, *|
28 |* INCLUDING ALL IMPLIED WARRANTIES OF MERCHANTABILITY, NONINFRINGE- *|
29 |* MENT, AND FITNESS FOR A PARTICULAR PURPOSE. IN NO EVENT SHALL *|
30 |* NVIDIA, CORPORATION BE LIABLE FOR ANY SPECIAL, INDIRECT, INCI- *|
31 |* DENTAL, OR CONSEQUENTIAL DAMAGES, OR ANY DAMAGES WHATSOEVER RE- *|
32 |* SULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN ACTION *|
33 |* OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF *|
34 |* OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOURCE CODE. *|
36 |* U.S. Government End Users. This source code is a "commercial *|
37 |* item," as that term is defined at 48 C.F.R. 2.101 (OCT 1995), *|
38 |* consisting of "commercial computer software" and "commercial *|
39 |* computer software documentation," as such terms are used in *|
40 |* 48 C.F.R. 12.212 (SEPT 1995) and is provided to the U.S. Govern- *|
41 |* ment only as a commercial end item. Consistent with 48 C.F.R. *|
42 |* 12.212 and 48 C.F.R. 227.7202-1 through 227.7202-4 (JUNE 1995), *|
43 |* all U.S. Government End Users acquire the source code with only *|
44 |* those rights set forth herein. *|
46 \***************************************************************************/
48 #include <aros/libcall.h>
49 #include <aros/asmcall.h>
51 #include <exec/types.h>
52 #include <exec/nodes.h>
53 #include <exec/execbase.h>
54 #include <exec/resident.h>
55 #include <exec/libraries.h>
56 #include <exec/memory.h>
57 #include <exec/lists.h>
58 #include <exec/semaphores.h>
62 #include <libcore/compiler.h>
64 #include <utility/utility.h>
65 #include <utility/hooks.h>
66 #include <utility/tagitem.h>
71 #include <hidd/hidd.h>
74 #include <aros/symbolsets.h>
77 #include <aros/debug.h>
79 #include <proto/exec.h>
80 #include <proto/oop.h>
82 #include LC_LIBDEFS_FILE
85 #undef HiddPCIDeviceAttrBase
87 #undef HiddGfxAttrBase
88 #undef HiddPixFmtAttrBase
89 #undef HiddSyncAttrBase
90 #undef HiddBitMapAttrBase
91 #define HiddPCIDeviceAttrBase (sd->pciAttrBase)
92 #define HiddAttrBase (sd->hiddAttrBase)
93 #define HiddBitMapAttrBase (sd->bitMapAttrBase)
94 #define HiddNVidiaBitMapAttrBase (sd->nvBitMapAttrBase)
95 #define HiddPixFmtAttrBase (sd->pixFmtAttrBase)
96 #define HiddGfxAttrBase (sd->gfxAttrBase)
97 #define HiddSyncAttrBase (sd->syncAttrBase)
98 #define __IHidd_PlanarBM (sd->planarAttrBase)
100 static BOOL
GenericInit(struct staticdata
*sd
)
102 D(bug("[NVidia] Generic chip init\n"));
103 IPTR regs
= (IPTR
)sd
->Card
.Registers
;
104 UWORD architecture
= sd
->Card
.Architecture
;
105 UWORD implementation
= sd
->Card
.Chipset
;
106 UWORD implementation_masked
= implementation
& 0x0FF0;
108 sd
->Card
.EnableIRQ
= 0;
110 sd
->Card
.PRAMDAC0
= (ULONG
*)(regs
+ 0x00680000);
111 sd
->Card
.PFB
= (ULONG
*)(regs
+ 0x00100000);
112 sd
->Card
.PFIFO
= (ULONG
*)(regs
+ 0x00002000);
113 sd
->Card
.PGRAPH
= (ULONG
*)(regs
+ 0x00400000);
114 sd
->Card
.PEXTDEV
= (ULONG
*)(regs
+ 0x00101000);
115 sd
->Card
.PTIMER
= (ULONG
*)(regs
+ 0x00009000);
116 sd
->Card
.PMC
= (ULONG
*)(regs
+ 0x00000000);
117 sd
->Card
.FIFO
= (ULONG
*)(regs
+ 0x00800000);
118 sd
->Card
.PCIO0
= (UBYTE
*)(regs
+ 0x00601000);
119 sd
->Card
.PDIO0
= (UBYTE
*)(regs
+ 0x00681000);
120 sd
->Card
.PVIO
= (UBYTE
*)(regs
+ 0x000C0000);
122 sd
->Card
.FlatPanel
= 0;
124 sd
->Card
.twoHeads
= (architecture
>= NV_ARCH_10
) &&
125 (implementation_masked
!= 0x0100) &&
126 (implementation_masked
!= 0x0150) &&
127 (implementation_masked
!= 0x01A0) &&
128 (implementation_masked
!= 0x0200);
130 sd
->Card
.fpScaler
= (sd
->Card
.twoHeads
&& (implementation_masked
!= 0x0110));
132 sd
->Card
.twoStagePLL
= (implementation_masked
== 0x0310) ||
133 (implementation_masked
== 0x0340) ||
134 (architecture
== NV_ARCH_40
);
136 sd
->Card
.alphaCursor
= implementation_masked
>= 0x0110;
138 switch (implementation
)
162 case 0x0326: /* stegerg: checkme, not listed in xfree nv_setup.c */
167 case 0x032e: /* stegerg: checkme, not listed in xfree nv_setup.c */
181 D(bug("[NVidia] Assuming Digital FlatPanel\n"));
182 sd
->Card
.FlatPanel
= 1;
188 if (architecture
== NV_ARCH_04
)
197 if (!sd
->Card
.twoHeads
)
199 VGA_WR08(sd
->Card
.PCIO
, 0x3d4, 0x28);
200 if (VGA_RD08(sd
->Card
.PCIO
, 0x3d5) & 0x80)
201 sd
->Card
.FlatPanel
= 1;
203 sd
->Card
.FlatPanel
= 0;
207 UBYTE outputAfromCRTC
, outputBfromCRTC
;
209 UBYTE slaved_on_A
, slaved_on_B
,tvA
=0,tvB
=0;
210 BOOL analog_on_A
, analog_on_B
;
214 if(implementation_masked
!= 0x0110) {
215 if(sd
->Card
.PRAMDAC0
[0x0000052C/4] & 0x100)
219 if(sd
->Card
.PRAMDAC0
[0x0000252C/4] & 0x100)
223 analog_on_A
= NVIsConnected(sd
, 0);
224 analog_on_B
= NVIsConnected(sd
, 1);
232 VGA_WR08(sd
->Card
.PCIO
, 0x03D4, 0x44);
233 cr44
= VGA_RD08(sd
->Card
.PCIO
, 0x03D5);
235 VGA_WR08(sd
->Card
.PCIO
, 0x03D5, 3);
239 VGA_WR08(sd
->Card
.PCIO
, 0x03D4, 0x28);
240 slaved_on_B
= VGA_RD08(sd
->Card
.PCIO
, 0x03D5) & 0x80;
242 VGA_WR08(sd
->Card
.PCIO
, 0x03D4, 0x33);
243 tvB
= !(VGA_RD08(sd
->Card
.PCIO
, 0x03D5) & 0x01);
246 VGA_WR08(sd
->Card
.PCIO
, 0x03D4, 0x44);
247 VGA_WR08(sd
->Card
.PCIO
, 0x03D5, 0);
251 VGA_WR08(sd
->Card
.PCIO
, 0x03D4, 0x28);
252 slaved_on_A
= VGA_RD08(sd
->Card
.PCIO
, 0x03D5) & 0x80;
254 VGA_WR08(sd
->Card
.PCIO
, 0x03D4, 0x33);
255 tvA
= !(VGA_RD08(sd
->Card
.PCIO
, 0x03D5) & 0x01);
258 oldhead
= sd
->Card
.PCRTC0
[0x00000860/4];
259 sd
->Card
.PCRTC0
[0x00000860/4] = oldhead
| 0x00000010;
261 if(slaved_on_A
&& !tvA
) {
263 sd
->Card
.FlatPanel
= 1;
265 if(slaved_on_B
&& !tvB
) {
267 sd
->Card
.FlatPanel
= 1;
270 CRTCnumber
= outputAfromCRTC
;
271 sd
->Card
.FlatPanel
= 0;
274 CRTCnumber
= outputBfromCRTC
;
275 sd
->Card
.FlatPanel
= 0;
279 sd
->Card
.FlatPanel
= 1;
280 sd
->Card
.Television
= 1;
284 sd
->Card
.FlatPanel
= 1;
285 sd
->Card
.Television
= 1;
288 if (CRTCnumber
== -1)
290 D(bug("[NVidia] Unable to detect CRTC number, using defaults\n"));
292 if (sd
->Card
.FlatPanel
) sd
->Card
.CRTCnumber
= 1;
293 else sd
->Card
.CRTCnumber
= 0;
295 else sd
->Card
.CRTCnumber
= CRTCnumber
;
297 if(implementation_masked
== 0x0110)
298 cr44
= sd
->Card
.CRTCnumber
* 0x3;
300 sd
->Card
.PCRTC0
[0x00000860/4] = oldhead
;
302 VGA_WR08(sd
->Card
.PCIO
, 0x03D4, 0x44);
303 VGA_WR08(sd
->Card
.PCIO
, 0x03D5, cr44
);
304 NVSelectHead(sd
, sd
->Card
.CRTCnumber
);
307 if (sd
->Card
.FlatPanel
&& !sd
->Card
.Television
)
309 sd
->Card
.fpWidth
= sd
->Card
.PRAMDAC
[0x0820/4] + 1;
310 sd
->Card
.fpHeight
= sd
->Card
.PRAMDAC
[0x0800/4] + 1;
313 sd
->Card
.PRAMDAC
[0x0300/4] = 0;
315 D(bug("[NVidia] Configuration received.\n"));
316 D(bug("[NVidia] Card has %dMB of video memory\n",
317 sd
->Card
.RamAmountKBytes
>> 10));
319 sd
->Card
.FrameBufferSize
= sd
->Card
.RamAmountKBytes
* 1024;
320 sd
->Card
.FbUsableSize
= sd
->Card
.FrameBufferSize
- 128 * 1024;
322 D(bug("[NVidia] Max clock is %dMHz\n",
323 sd
->Card
.MaxVClockFreqKHz
/ 1000));
325 kprintf("\n=== NVidia GenericInit FlatPanel = %d TwoHeads = %d CRTCnumber = %d twostagepll = %d\n\n",
329 sd
->Card
.twoStagePLL
);
334 static BOOL
NV4Init(struct staticdata
*sd
)
336 sd
->Card
.PRAMIN
= sd
->Card
.Registers
+ 0x00710000;
337 sd
->Card
.PCRTC0
= sd
->Card
.Registers
+ 0x00600000;
338 return GenericInit(sd
);
341 static BOOL
NV10Init(struct staticdata
*sd
)
346 static BOOL
NV20Init(struct staticdata
*sd
)
351 /* List of DeviceID's of supported nvidia cards */
352 static const struct NVDevice
{
353 UWORD VendorID
, ProductID
;
356 BOOL (*Init
)(struct staticdata
*);
361 /* Known: match ProductID exactly */
362 { 0x10de, 0x0020, NV04
, NV_ARCH_04
, NV4Init
, FALSE
}, /* RIVA TNT */
363 { 0x10de, 0x0028, NV05
, NV_ARCH_04
, NV4Init
, FALSE
}, /* RIVA TNT2 */
364 { 0x10de, 0x0029, NV05
, NV_ARCH_04
, NV4Init
, FALSE
}, /* RIVA TNT2 Ultra */
365 { 0x10de, 0x002a, NV05
, NV_ARCH_04
, NV4Init
, FALSE
}, /* Unknown TNT2 */
366 { 0x10de, 0x002b, NV05
, NV_ARCH_04
, NV4Init
, FALSE
},
367 { 0x10de, 0x002c, NV05
, NV_ARCH_04
, NV4Init
, FALSE
}, /* Vanta */
368 { 0x10de, 0x002d, NV05M64
, NV_ARCH_04
, NV4Init
, FALSE
}, /* RIVA TNT2 Model 64 */
369 { 0x10de, 0x002e, NV06
, NV_ARCH_04
, NV4Init
, FALSE
},
370 { 0x10de, 0x002f, NV06
, NV_ARCH_04
, NV4Init
, FALSE
},
371 { 0x10de, 0x00a0, NV05
, NV_ARCH_04
, NV4Init
, FALSE
}, /* Aladdin TNT2 */
372 { 0x10de, 0x0100, NV10
, NV_ARCH_10
, NV10Init
, FALSE
}, /* GeForce 256 */
373 { 0x10de, 0x0101, NV10
, NV_ARCH_10
, NV10Init
, FALSE
}, /* GeForce DDR */
374 { 0x10de, 0x0102, NV10
, NV_ARCH_10
, NV10Init
, FALSE
},
375 { 0x10de, 0x0103, NV10
, NV_ARCH_10
, NV10Init
, FALSE
}, /* Quadro */
376 { 0x10de, 0x0110, NV11
, NV_ARCH_10
, NV10Init
, FALSE
}, /* GeForce2 MX/MX 400 */
377 { 0x10de, 0x0111, NV11
, NV_ARCH_10
, NV10Init
, FALSE
}, /* GeForce2 MX 100/200 */
378 { 0x10de, 0x0112, NV11
, NV_ARCH_10
, NV10Init
, FALSE
}, /* GeForce2 Go */
379 { 0x10de, 0x0113, NV11
, NV_ARCH_10
, NV10Init
, FALSE
}, /* Quadro2 MXR/EX/Go */
380 { 0x10de, 0x0150, NV15
, NV_ARCH_10
, NV10Init
, FALSE
}, /* GeForce2 GTS */
381 { 0x10de, 0x0151, NV15
, NV_ARCH_10
, NV10Init
, FALSE
}, /* GeForce2 Ti */
382 { 0x10de, 0x0152, NV15
, NV_ARCH_10
, NV10Init
, FALSE
}, /* GeForce2 Ultra */
383 { 0x10de, 0x0153, NV15
, NV_ARCH_10
, NV10Init
, FALSE
}, /* Quadro2 Pro */
384 { 0x10de, 0x0170, NV17
, NV_ARCH_10
, NV10Init
, FALSE
}, /* GeForce4 MX 460 */
385 { 0x10de, 0x0171, NV17
, NV_ARCH_10
, NV10Init
, FALSE
}, /* GeForce4 MX 440 */
386 { 0x10de, 0x0172, NV17
, NV_ARCH_10
, NV10Init
, FALSE
}, /* GeForce4 MX 420 */
387 { 0x10de, 0x0173, NV17
, NV_ARCH_10
, NV10Init
, FALSE
}, /* GeForce4 MX 440-SE */
388 { 0x10de, 0x0174, NV17
, NV_ARCH_10
, NV10Init
, FALSE
}, /* GeForce4 440 Go */
389 { 0x10de, 0x0175, NV17
, NV_ARCH_10
, NV10Init
, FALSE
}, /* GeForce4 420 Go */
390 { 0x10de, 0x0176, NV17
, NV_ARCH_10
, NV10Init
, FALSE
}, /* GeForce4 420 Go 32M */
391 { 0x10de, 0x0177, NV17
, NV_ARCH_10
, NV10Init
, FALSE
}, /* GeForce4 460 Go */
392 { 0x10de, 0x0178, NV17
, NV_ARCH_10
, NV10Init
, FALSE
}, /* Quadro4 550 XGL */
393 { 0x10de, 0x0179, NV17
, NV_ARCH_10
, NV10Init
, FALSE
}, /* GeForce4 440 Go 64M / GeForce4 Mx (Mac) */
394 { 0x10de, 0x017a, NV17
, NV_ARCH_10
, NV10Init
, FALSE
}, /* Quadro4 NVS */
395 { 0x10de, 0x017c, NV17
, NV_ARCH_10
, NV10Init
, FALSE
}, /* Quadro4 500 GoGL */
396 { 0x10de, 0x017d, NV17
, NV_ARCH_10
, NV10Init
, FALSE
}, /* GeForce4 410 Go 16M */
397 { 0x10de, 0x0180, NV18
, NV_ARCH_10
, NV10Init
, FALSE
},
398 { 0x10de, 0x0181, NV18
, NV_ARCH_10
, NV10Init
, FALSE
}, /* GeForce4 MX 440 with AGP8x */
399 { 0x10de, 0x0182, NV18
, NV_ARCH_10
, NV10Init
, FALSE
}, /* GeForce4 MX 440SE with AGP8x */
400 { 0x10de, 0x0183, NV18
, NV_ARCH_10
, NV10Init
, FALSE
}, /* GeForce4 MX 420 with AGP8x */
401 { 0x10de, 0x0186, NV18
, NV_ARCH_10
, NV10Init
, FALSE
}, /* GeForce4 448 Go */
402 { 0x10de, 0x0187, NV18
, NV_ARCH_10
, NV10Init
, FALSE
}, /* GeForce4 488 Go */
403 { 0x10de, 0x0188, NV18
, NV_ARCH_10
, NV10Init
, FALSE
}, /* Quadro4 580 XGL */
404 { 0x10de, 0x0189, NV18
, NV_ARCH_10
, NV10Init
, FALSE
}, /* GeForce4 MX with AGP8X (Mac) */
405 { 0x10de, 0x018a, NV18
, NV_ARCH_10
, NV10Init
, FALSE
}, /* Quadro4 280 NVS */
406 { 0x10de, 0x018b, NV18
, NV_ARCH_10
, NV10Init
, FALSE
}, /* Quadro4 380 XGL */
407 { 0x10de, 0x01a0, NV11
, NV_ARCH_10
, NV10Init
, FALSE
}, /* GeForce2 Integrated GPU */
408 { 0x10de, 0x01f0, NV17
, NV_ARCH_10
, NV10Init
, FALSE
}, /* GeForce4 MX Integerated GPU */
409 { 0x10de, 0x0200, NV20
, NV_ARCH_20
, NV20Init
, FALSE
}, /* GeForce3 */
410 { 0x10de, 0x0201, NV20
, NV_ARCH_20
, NV20Init
, FALSE
}, /* GeForce3 Ti 200 */
411 { 0x10de, 0x0202, NV20
, NV_ARCH_20
, NV20Init
, FALSE
}, /* GeForce3 Ti 500 */
412 { 0x10de, 0x0203, NV20
, NV_ARCH_20
, NV20Init
, FALSE
}, /* Quadro DCC */
413 { 0x10de, 0x0250, NV25
, NV_ARCH_20
, NV20Init
, FALSE
}, /* GeForce4 Ti 4600 */
414 { 0x10de, 0x0251, NV25
, NV_ARCH_20
, NV20Init
, FALSE
}, /* GeForce4 Ti 4400 */
415 { 0x10de, 0x0252, NV25
, NV_ARCH_20
, NV20Init
, FALSE
}, /* 0x252 */
416 { 0x10de, 0x0253, NV25
, NV_ARCH_20
, NV20Init
, FALSE
}, /* GeForce4 Ti 4200 */
417 { 0x10de, 0x0258, NV25
, NV_ARCH_20
, NV20Init
, FALSE
}, /* Quadro4 900 XGL */
418 { 0x10de, 0x0259, NV25
, NV_ARCH_20
, NV20Init
, FALSE
}, /* Quadro4 750 XGL */
419 { 0x10de, 0x025b, NV25
, NV_ARCH_20
, NV20Init
, FALSE
}, /* Quadro4 700 XGL */
420 { 0x10de, 0x0280, NV28
, NV_ARCH_20
, NV20Init
, FALSE
}, /* GeForce4 Ti 4800 */
421 { 0x10de, 0x0281, NV28
, NV_ARCH_20
, NV20Init
, FALSE
}, /* GeForce4 Ti 4200 with AGP8X */
422 { 0x10de, 0x0282, NV28
, NV_ARCH_20
, NV20Init
, FALSE
}, /* GeForce4 Ti 4800 SE */
423 { 0x10de, 0x0286, NV28
, NV_ARCH_20
, NV20Init
, FALSE
}, /* GeForce4 4200 Go */
424 { 0x10de, 0x0288, NV28
, NV_ARCH_20
, NV20Init
, FALSE
}, /* Quadro4 980 XGL */
425 { 0x10de, 0x0289, NV28
, NV_ARCH_20
, NV20Init
, FALSE
}, /* Quadro4 780 XGL */
426 { 0x10de, 0x028c, NV28
, NV_ARCH_20
, NV20Init
, FALSE
}, /* Quadro4 700 GoGL */
427 { 0x10de, 0x02a0, NV20
, NV_ARCH_20
, NV20Init
, FALSE
},
428 { 0x10de, 0x0301, NV30
, NV_ARCH_30
, NV20Init
, FALSE
}, /* GeForce FX 5800 Ultra */
429 { 0x10de, 0x0302, NV30
, NV_ARCH_30
, NV20Init
, FALSE
}, /* GeForce FX 5800 */
430 { 0x10de, 0x0308, NV30
, NV_ARCH_30
, NV20Init
, FALSE
}, /* Quadro FX 2000 */
431 { 0x10de, 0x0309, NV30
, NV_ARCH_30
, NV20Init
, FALSE
}, /* Quadro FX 1000 */
432 { 0x10de, 0x0311, NV31
, NV_ARCH_30
, NV20Init
, FALSE
}, /* GeForce FX 5600 Ultra */
433 { 0x10de, 0x0312, NV31
, NV_ARCH_30
, NV20Init
, FALSE
}, /* GeForce FX 5600 */
434 { 0x10de, 0x0313, NV31
, NV_ARCH_30
, NV20Init
, FALSE
}, /* 0x313 */
435 { 0x10de, 0x0314, NV31
, NV_ARCH_30
, NV20Init
, FALSE
}, /* GeForce FX 5600 SE */
436 { 0x10de, 0x0316, NV31
, NV_ARCH_30
, NV20Init
, FALSE
}, /* 0x316 */
437 { 0x10de, 0x0317, NV31
, NV_ARCH_30
, NV20Init
, FALSE
}, /* 0x317 */
438 { 0x10de, 0x031a, NV31
, NV_ARCH_30
, NV20Init
, FALSE
}, /* GeForce FX Go5600 */
439 { 0x10de, 0x031b, NV31
, NV_ARCH_30
, NV20Init
, FALSE
}, /* GeForce FX Go5650 */
440 { 0x10de, 0x031c, NV31
, NV_ARCH_30
, NV20Init
, FALSE
}, /* Quadro FX Go700 */
441 { 0x10de, 0x031d, NV31
, NV_ARCH_30
, NV20Init
, FALSE
}, /* 0x31d */
442 { 0x10de, 0x031e, NV31
, NV_ARCH_30
, NV20Init
, FALSE
}, /* 0x31e */
443 { 0x10de, 0x031f, NV31
, NV_ARCH_30
, NV20Init
, FALSE
}, /* 0x31f */
444 { 0x10de, 0x0320, NV34
, NV_ARCH_30
, NV20Init
, FALSE
}, /* GeForce FX 5200 */
445 { 0x10de, 0x0321, NV34
, NV_ARCH_30
, NV20Init
, FALSE
}, /* GeForce FX 5200 Ultra */
446 { 0x10de, 0x0322, NV34
, NV_ARCH_30
, NV20Init
, FALSE
}, /* GeForce FX 5200 */
447 { 0x10de, 0x0323, NV34
, NV_ARCH_30
, NV20Init
, FALSE
}, /* GeForce FX 5200SE */
448 { 0x10de, 0x0324, NV34
, NV_ARCH_30
, NV20Init
, FALSE
}, /* GeForce FX Go5200 */
449 { 0x10de, 0x0325, NV34
, NV_ARCH_30
, NV20Init
, FALSE
}, /* GeForce FX Go5250 */
450 { 0x10de, 0x0326, NV34
, NV_ARCH_30
, NV20Init
, FALSE
}, /* GeForce FX 5500 */
451 { 0x10de, 0x0327, NV34
, NV_ARCH_30
, NV20Init
, FALSE
}, /* GeForce FX 5100 */
452 { 0x10de, 0x0328, NV34
, NV_ARCH_30
, NV20Init
, FALSE
}, /* GeForce FX Go5200 32M/64M */
453 { 0x10de, 0x0329, NV34
, NV_ARCH_30
, NV20Init
, FALSE
}, /* 0x329 / GeForce FX 5200 (Mac) */
454 { 0x10de, 0x032a, NV34
, NV_ARCH_30
, NV20Init
, FALSE
}, /* Quadro NVS 280 PCI */
455 { 0x10de, 0x032b, NV34
, NV_ARCH_30
, NV20Init
, FALSE
}, /* Quadro FX 500/600 PCI */
456 { 0x10de, 0x032c, NV34
, NV_ARCH_30
, NV20Init
, FALSE
}, /* GeForce FX Go53xx Series */
457 { 0x10de, 0x032d, NV34
, NV_ARCH_30
, NV20Init
, FALSE
}, /* GeForce FX Go5100 */
458 { 0x10de, 0x032e, NV34
, NV_ARCH_30
, NV20Init
, FALSE
},
459 { 0x10de, 0x032f, NV34
, NV_ARCH_30
, NV20Init
, FALSE
}, /* 0x32F */
460 { 0x10de, 0x0330, NV34
, NV_ARCH_30
, NV20Init
, FALSE
}, /* GeForce Fx 5900 Ultra */
461 { 0x10de, 0x0331, NV34
, NV_ARCH_30
, NV20Init
, FALSE
}, /* GeForce FX 5900 */
462 { 0x10de, 0x0332, NV34
, NV_ARCH_30
, NV20Init
, FALSE
}, /* GeForce FX 5900XT */
463 { 0x10de, 0x0333, NV34
, NV_ARCH_30
, NV20Init
, FALSE
}, /* GeForce FX 5950 Ultra */
464 { 0x10de, 0x0334, NV34
, NV_ARCH_30
, NV20Init
, FALSE
}, /* GeForce FX 5900ZT */
465 { 0x10de, 0x0338, NV34
, NV_ARCH_30
, NV20Init
, FALSE
}, /* Quadro FX 3000 */
466 { 0x10de, 0x033F, NV34
, NV_ARCH_30
, NV20Init
, FALSE
}, /* Quadro FX 700 */
467 { 0x10de, 0x0341, NV36
, NV_ARCH_30
, NV20Init
, FALSE
}, /* GeForce FX 5700 Ultra */
468 { 0x10de, 0x0342, NV36
, NV_ARCH_30
, NV20Init
, FALSE
}, /* GeForce FX 5700 */
469 { 0x10de, 0x0343, NV36
, NV_ARCH_30
, NV20Init
, FALSE
}, /* GeForce FX 5700LE */
470 { 0x10de, 0x0344, NV36
, NV_ARCH_30
, NV20Init
, FALSE
}, /* GeForce FX 5700VE */
471 { 0x10de, 0x0345, NV36
, NV_ARCH_30
, NV20Init
, FALSE
}, /* 0x345 */
472 { 0x10de, 0x0347, NV36
, NV_ARCH_30
, NV20Init
, FALSE
}, /* GeForce FX Go5700 */
473 { 0x10de, 0x0348, NV36
, NV_ARCH_30
, NV20Init
, FALSE
}, /* GeForce FX Go5700 */
474 { 0x10de, 0x0349, NV36
, NV_ARCH_30
, NV20Init
, FALSE
}, /* 0x349 */
475 { 0x10de, 0x034B, NV36
, NV_ARCH_30
, NV20Init
, FALSE
}, /* 0x34B */
476 { 0x10de, 0x034C, NV36
, NV_ARCH_30
, NV20Init
, FALSE
}, /* Quadro FX Go1000 */
477 { 0x10de, 0x034E, NV36
, NV_ARCH_30
, NV20Init
, FALSE
}, /* Quadro FX 1100 */
478 { 0x10de, 0x034F, NV36
, NV_ARCH_30
, NV20Init
, FALSE
}, /* 0x34F */
479 { 0x10de, 0x0040, NV36
, NV_ARCH_40
, NV20Init
, FALSE
}, /* GeForce 6800 Ultra */
480 { 0x10de, 0x0041, NV36
, NV_ARCH_40
, NV20Init
, FALSE
}, /* GeForce 6800 */
481 { 0x10de, 0x0042, NV36
, NV_ARCH_40
, NV20Init
, FALSE
}, /* GeForce 6800 LE */
482 { 0x10de, 0x0043, NV36
, NV_ARCH_40
, NV20Init
, FALSE
}, /* 0x043 */
483 { 0x10de, 0x0045, NV36
, NV_ARCH_40
, NV20Init
, FALSE
}, /* GeForce 6800 GT */
484 { 0x10de, 0x0049, NV36
, NV_ARCH_40
, NV20Init
, FALSE
}, /* 0x049 */
485 { 0x10de, 0x004E, NV36
, NV_ARCH_40
, NV20Init
, FALSE
}, /* Quadro FX 4000 */
486 { 0x10de, 0x00C0, NV36
, NV_ARCH_40
, NV20Init
, FALSE
}, /* 0x0C0 */
487 { 0x10de, 0x00C1, NV36
, NV_ARCH_40
, NV20Init
, FALSE
}, /* 0x0C1 */
488 { 0x10de, 0x00C2, NV36
, NV_ARCH_40
, NV20Init
, FALSE
}, /* 0x0C2 */
489 { 0x10de, 0x00C8, NV36
, NV_ARCH_40
, NV20Init
, FALSE
}, /* 0x0C8 */
490 { 0x10de, 0x00C9, NV36
, NV_ARCH_40
, NV20Init
, FALSE
}, /* 0x0C9 */
491 { 0x10de, 0x00CC, NV36
, NV_ARCH_40
, NV20Init
, FALSE
}, /* 0x0CC */
492 { 0x10de, 0x00CE, NV36
, NV_ARCH_40
, NV20Init
, FALSE
}, /* 0x0CE */
493 { 0x10de, 0x00F1, NV36
, NV_ARCH_40
, NV20Init
, FALSE
}, /* GeForce 6600 / GeForce 6600 GT (Verified: LeadTek GeForce 6600 GT) */
494 { 0x10de, 0x00F2, NV43
, NV_ARCH_40
, NV20Init
, FALSE
}, /* GeForce 6600 / GeForce 6600 GT (Verified: Club3D GeForce 6600) */
495 { 0x10de, 0x0140, NV36
, NV_ARCH_40
, NV20Init
, FALSE
}, /* GeForce 6600 GT */
496 { 0x10de, 0x0141, NV36
, NV_ARCH_40
, NV20Init
, FALSE
}, /* GeForce 6600 */
497 { 0x10de, 0x0142, NV36
, NV_ARCH_40
, NV20Init
, FALSE
}, /* 0x0142 */
498 { 0x10de, 0x0143, NV36
, NV_ARCH_40
, NV20Init
, FALSE
}, /* 0x0143 */
499 { 0x10de, 0x0144, NV36
, NV_ARCH_40
, NV20Init
, FALSE
}, /* 0x0144 */
500 { 0x10de, 0x0145, NV36
, NV_ARCH_40
, NV20Init
, FALSE
}, /* GeForce 6610 XL */
501 { 0x10de, 0x0146, NV36
, NV_ARCH_40
, NV20Init
, FALSE
}, /* 0x0146 */
502 { 0x10de, 0x0147, NV36
, NV_ARCH_40
, NV20Init
, FALSE
}, /* 0x0147 */
503 { 0x10de, 0x0148, NV36
, NV_ARCH_40
, NV20Init
, FALSE
}, /* 0x0148 */
504 { 0x10de, 0x0149, NV36
, NV_ARCH_40
, NV20Init
, FALSE
}, /* 0x0149 */
505 { 0x10de, 0x014B, NV36
, NV_ARCH_40
, NV20Init
, FALSE
}, /* 0x014B */
506 { 0x10de, 0x014C, NV36
, NV_ARCH_40
, NV20Init
, FALSE
}, /* 0x014C */
507 { 0x10de, 0x014D, NV36
, NV_ARCH_40
, NV20Init
, FALSE
}, /* 0x014D */
508 { 0x10de, 0x014E, NV36
, NV_ARCH_40
, NV20Init
, FALSE
}, /* Quadro FX 540 */
509 { 0x10de, 0x014F, NV36
, NV_ARCH_40
, NV20Init
, FALSE
}, /* GeForce 6200 */
510 { 0x10de, 0x0160, NV36
, NV_ARCH_40
, NV20Init
, FALSE
}, /* 0x0160 */
511 { 0x10de, 0x0166, NV36
, NV_ARCH_40
, NV20Init
, FALSE
}, /* 0x0166 */
512 { 0x10de, 0x0210, NV36
, NV_ARCH_40
, NV20Init
, FALSE
}, /* 0x0210 */
513 { 0x10de, 0x0211, NV36
, NV_ARCH_40
, NV20Init
, FALSE
}, /* 0x0211 */
514 { 0x10de, 0x021D, NV36
, NV_ARCH_40
, NV20Init
, FALSE
}, /* 0x021D */
515 { 0x10de, 0x021E, NV36
, NV_ARCH_40
, NV20Init
, FALSE
}, /* 0x021E */
517 /* Unknown: Match ProductID & 0xFFF0 */
518 { 0x10de, 0x0170, NV17
, NV_ARCH_10
, NV10Init
, TRUE
},
519 { 0x10de, 0x0180, NV18
, NV_ARCH_10
, NV10Init
, TRUE
},
520 { 0x10de, 0x0250, NV25
, NV_ARCH_20
, NV20Init
, TRUE
},
521 { 0x10de, 0x0280, NV28
, NV_ARCH_20
, NV20Init
, TRUE
},
522 { 0x10de, 0x0300, NV30
, NV_ARCH_30
, NV20Init
, TRUE
},
523 { 0x10de, 0x0310, NV31
, NV_ARCH_30
, NV20Init
, TRUE
},
524 { 0x10de, 0x0320, NV34
, NV_ARCH_30
, NV20Init
, TRUE
},
525 { 0x10de, 0x0340, NV34
, NV_ARCH_30
, NV20Init
, TRUE
},
526 { 0x10de, 0x0040, NV36
, NV_ARCH_40
, NV20Init
, TRUE
},
527 { 0x10de, 0x00C0, NV36
, NV_ARCH_40
, NV20Init
, TRUE
},
528 { 0x10de, 0x0120, NV36
, NV_ARCH_40
, NV20Init
, TRUE
},
529 { 0x10de, 0x0140, NV36
, NV_ARCH_40
, NV20Init
, TRUE
},
530 { 0x10de, 0x0160, NV36
, NV_ARCH_40
, NV20Init
, TRUE
},
531 { 0x10de, 0x0130, NV36
, NV_ARCH_40
, NV20Init
, TRUE
},
532 { 0x10de, 0x01D0, NV36
, NV_ARCH_40
, NV20Init
, TRUE
},
533 { 0x10de, 0x0090, NV36
, NV_ARCH_40
, NV20Init
, TRUE
},
534 { 0x10de, 0x0210, NV36
, NV_ARCH_40
, NV20Init
, TRUE
},
539 #define sd ((struct staticdata*)hook->h_Data)
540 AROS_UFH3(void, Enumerator
,
541 AROS_UFHA(struct Hook
*, hook
, A0
),
542 AROS_UFHA(OOP_Object
*, pciDevice
, A2
),
543 AROS_UFHA(APTR
, message
, A1
))
547 struct NVDevice
*sup
= (struct NVDevice
*)support
;
551 /* Get the Device's ProductID */
552 OOP_GetAttr(pciDevice
, aHidd_PCIDevice_ProductID
, &ProductID
);
553 OOP_GetAttr(pciDevice
, aHidd_PCIDevice_VendorID
, &VendorID
);
555 D(bug("[NVidia] Enumerator: checking productid %d vendorid %d sd->Deivce %x\n",
556 ProductID
, VendorID
, sd
->Device
));
558 /* And try to match it with supported cards */
559 while (sup
->VendorID
)
563 if (sup
->VendorID
== VendorID
)
565 if (!sup
->masked_check
&& (sup
->ProductID
== ProductID
))
569 else if (sup
->masked_check
&& (sup
->ProductID
== (ProductID
& 0xFFF0)))
577 /* Matching card found */
580 struct pHidd_PCIDriver_MapPCI mappci
,*msg
= &mappci
;
584 struct TagItem attrs
[] = {
585 { aHidd_PCIDevice_isIO
, FALSE
}, /* Don't listen IO transactions */
586 { aHidd_PCIDevice_isMEM
, TRUE
}, /* Listen to MEM transactions */
587 { aHidd_PCIDevice_isMaster
, TRUE
}, /* Can work in BusMaster */
591 D(bug("[NVidia] Enumerator: found productid %d vendorid %d masked_check %d\n",
592 sup
->ProductID
, sup
->VendorID
, sup
->masked_check
));
595 sd
->Card
.ProductID
= ProductID
;
596 sd
->Card
.VendorID
= VendorID
;
597 sd
->Card
.Type
= sup
->Type
;
598 sd
->Card
.Architecture
= sup
->Arch
;
599 sd
->Card
.Chipset
= ProductID
;
601 D(bug("[NVidia] Chip architecture = %d\n", sd
->Card
.Architecture
));
603 /*-------- DO NOT CHANGE/REMOVE -------------*/
604 bug("\003\n"); /* Tell vga text mode debug output to die */
605 /*-------- DO NOT CHANGE/REMOVE -------------*/
608 Fix PCI device attributes (perhaps already set, but if the
609 NVidia would be the second card in the system, it may stay
612 OOP_SetAttrs(pciDevice
, (struct TagItem
*)&attrs
);
614 OOP_GetAttr(pciDevice
, aHidd_PCIDevice_Driver
, (APTR
)&driver
);
615 sd
->pcidriver
= driver
;
617 OOP_GetAttr(pciDevice
, aHidd_PCIDevice_Base1
, (APTR
)&buf
);
618 OOP_GetAttr(pciDevice
, aHidd_PCIDevice_Size1
, (APTR
)&size
);
620 sd
->mid_ReadLong
= OOP_GetMethodID(IID_Hidd_PCIDriver
, moHidd_PCIDriver_ReadConfigLong
);
622 mappci
.mID
= OOP_GetMethodID(IID_Hidd_PCIDriver
, moHidd_PCIDriver_MapPCI
);
623 mappci
.PCIAddress
= buf
;
624 mappci
.Length
= size
;
626 sd
->Card
.FbAddress
= buf
;
627 sd
->Card
.FrameBuffer
= (APTR
)OOP_DoMethod(driver
, (OOP_Msg
)msg
);
628 mc
= (struct MemChunk
*)sd
->Card
.FrameBuffer
;
630 sd
->CardMem
->mh_Node
.ln_Type
= NT_MEMORY
;
631 sd
->CardMem
->mh_Node
.ln_Name
= "nVidia Framebuffer";
632 sd
->CardMem
->mh_First
= mc
;
633 sd
->CardMem
->mh_Lower
= (APTR
)mc
;
635 D(bug("[NVidia] Got framebuffer @ %x (size=%x)\n", sd
->Card
.FrameBuffer
, size
));
637 OOP_GetAttr(pciDevice
, aHidd_PCIDevice_Base0
, (APTR
)&buf
);
638 OOP_GetAttr(pciDevice
, aHidd_PCIDevice_Size0
, (APTR
)&size
);
640 mappci
.PCIAddress
= buf
;
641 mappci
.Length
= size
;
643 sd
->Card
.Registers
= (APTR
)OOP_DoMethod(driver
, (OOP_Msg
)msg
);
644 D(bug("[NVidia] Got registers @ %x (size=%x)\n", sd
->Card
.Registers
, size
));
648 struct CardState
*state
= (struct CardState
*)AllocPooled(sd
->memPool
,
649 sizeof(struct CardState
));
651 sd
->CardMem
->mh_Free
= sd
->Card
.FbUsableSize
;
652 sd
->CardMem
->mh_Upper
= (APTR
)(sd
->CardMem
->mh_Free
+ (IPTR
)mc
);
655 mc
->mc_Bytes
= sd
->CardMem
->mh_Free
;
657 D(bug("[NVidia] Usable size: %dKB\n", sd
->CardMem
->mh_Free
>> 10));
659 sd
->Device
= pciDevice
;
661 InitMode(sd
, state
, 640, 480, 16, 25200, 0,
666 InitMode(sd, state, 800, 600, 24, 36000, 0,
671 LoadState(sd
, state
);
672 DPMS(sd
,vHidd_Gfx_DPMSLevel_On
);
674 sd
->scratch_buffer
= AllocBitmapArea(sd
, 65536, 1, 4, TRUE
);
679 struct pHidd_PCIDriver_UnmapPCI unmappci
,*msg
=&unmappci
;
681 OOP_GetAttr(pciDevice
, aHidd_PCIDevice_Size1
, (APTR
)&size
);
683 unmappci
.mID
= OOP_GetMethodID(IID_Hidd_PCIDriver
, moHidd_PCIDriver_UnmapPCI
);
684 unmappci
.CPUAddress
= sd
->Card
.FrameBuffer
;
685 unmappci
.Length
= size
;
687 OOP_DoMethod(driver
, (OOP_Msg
)msg
);
689 OOP_GetAttr(pciDevice
, aHidd_PCIDevice_Size0
, (APTR
)&size
);
690 unmappci
.CPUAddress
= sd
->Card
.Registers
;
691 unmappci
.Length
= size
;
693 OOP_DoMethod(driver
, (OOP_Msg
)msg
);
703 D(bug("[NVidia] Enumerator found a card (ProductID=%04x)\n", ProductID
));
704 D(bug("[NVidia] The card is %ssupported\n",
705 sd
->Device
? "":"un"));
711 static void Find_NV_Card(struct staticdata
*sd
)
713 D(bug("[NVidia] Find_NV_Card\n"));
715 if (HiddPCIDeviceAttrBase
)
717 sd
->pci
= OOP_NewObject(NULL
, CLID_Hidd_PCI
, NULL
);
719 D(bug("[NVidia] Creating PCI object\n"));
723 struct Hook FindHook
= {
724 h_Entry
: (IPTR (*)())Enumerator
,
728 struct TagItem Requirements
[] = {
729 { tHidd_PCI_Interface
, 0x00 },
730 { tHidd_PCI_Class
, 0x03 },
731 { tHidd_PCI_SubClass
, 0x00 },
732 { tHidd_PCI_VendorID
, 0x10de }, // NVidia VendorID. May require more of them
736 struct pHidd_PCI_EnumDevices enummsg
= {
737 mID
: OOP_GetMethodID(IID_Hidd_PCI
, moHidd_PCI_EnumDevices
),
739 requirements
: (struct TagItem
*)&Requirements
,
741 D(bug("[NVidia] Calling search Hook\n"));
742 OOP_DoMethod(sd
->pci
, (OOP_Msg
)msg
);
747 static int NV_Init(LIBBASETYPEPTR LIBBASE
)
749 D(bug("[NVidia] Initialization\n"));
751 /* Global memory pool and static data creation */
752 LIBBASE
->memPool
= CreatePool(MEMF_CLEAR
| MEMF_PUBLIC
| MEMF_SEM_PROTECTED
, 8192, 4096);
753 if (LIBBASE
->memPool
)
755 struct staticdata
*sd
= &LIBBASE
->sd
;
757 sd
->memPool
= LIBBASE
->memPool
;
758 sd
->CardMem
= &LIBBASE
->mh
;
760 InitSemaphore(&sd
->HWLock
);
761 InitSemaphore(&sd
->MultiBMLock
);
763 sd
->dpms
= vHidd_Gfx_DPMSLevel_On
;
766 struct OOP_ABDescr attrbases
[] =
768 { IID_Hidd_PCIDevice
, &HiddPCIDeviceAttrBase
},
769 { IID_Hidd
, &HiddAttrBase
},
770 { IID_Hidd_BitMap
, &HiddBitMapAttrBase
},
771 { IID_Hidd_PixFmt
, &HiddPixFmtAttrBase
},
772 { IID_Hidd_Sync
, &HiddSyncAttrBase
},
773 { IID_Hidd_Gfx
, &HiddGfxAttrBase
},
774 { IID_Hidd_nvBitMap
, &HiddNVidiaBitMapAttrBase
},
775 { IID_Hidd_PlanarBM
, &__IHidd_PlanarBM
},
779 sd
->basebm
= OOP_FindClass(CLID_Hidd_BitMap
);
781 if (OOP_ObtainAttrBases(attrbases
))
785 if (sd
->Device
!= NULL
)
789 OOP_ReleaseAttrBases(attrbases
);
791 OOP_DisposeObject(sd
->pci
);
796 Something failed. Ehm, that shouldn't happen at all. Now we have to
799 DeletePool(LIBBASE
->memPool
);
801 D(bug("[NVidia] nvBase=%x. FAILURE! Now freezing so you can check debug output!\n", LIBBASE
));
808 ADD2INITLIB(NV_Init
, 0)