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revert between 56095 -> 55830 in arch
[AROS.git] / workbench / libs / mesa / src / gallium / drivers / nvc0 / nvc0_screen.c
blob34bf0f0a2adb51fb2fdd3884bd750f13620f55de
1 /*
2 * Copyright 2010 Christoph Bumiller
3 *
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
10 *
11 * The above copyright notice and this permission notice shall be included in
12 * all copies or substantial portions of the Software.
13 *
14 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
15 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
16 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
17 * THE AUTHORS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
18 * WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF
19 * OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
20 * SOFTWARE.
21 */
22
23 #include "util/u_format.h"
24 #include "util/u_format_s3tc.h"
25 #include "pipe/p_screen.h"
26
27 #include "nvc0_context.h"
28 #include "nvc0_screen.h"
29
30 #include "nouveau/nv_object.xml.h"
31 #include "nvc0_graph_macros.h"
32
33 static boolean
34 nvc0_screen_is_format_supported(struct pipe_screen *pscreen,
35 enum pipe_format format,
36 enum pipe_texture_target target,
37 unsigned sample_count,
38 unsigned bindings)
39 {
40 if (sample_count > 1)
41 return FALSE;
42
43 if (!util_format_is_supported(format, bindings))
44 return FALSE;
45
46 /* transfers & shared are always supported */
47 bindings &= ~(PIPE_BIND_TRANSFER_READ |
48 PIPE_BIND_TRANSFER_WRITE |
49 PIPE_BIND_SHARED);
50
51 return (nvc0_format_table[format].usage & bindings) == bindings;
52 }
53
54 static int
55 nvc0_screen_get_param(struct pipe_screen *pscreen, enum pipe_cap param)
56 {
57 switch (param) {
58 case PIPE_CAP_MAX_TEXTURE_IMAGE_UNITS:
59 case PIPE_CAP_MAX_VERTEX_TEXTURE_UNITS:
60 return 32;
61 case PIPE_CAP_MAX_COMBINED_SAMPLERS:
62 return 64;
63 case PIPE_CAP_MAX_TEXTURE_2D_LEVELS:
64 return 13;
65 case PIPE_CAP_MAX_TEXTURE_3D_LEVELS:
66 return 10;
67 case PIPE_CAP_MAX_TEXTURE_CUBE_LEVELS:
68 return 13;
69 case PIPE_CAP_ARRAY_TEXTURES:
70 return 1;
71 case PIPE_CAP_TEXTURE_MIRROR_CLAMP:
72 case PIPE_CAP_TEXTURE_MIRROR_REPEAT:
73 case PIPE_CAP_TEXTURE_SWIZZLE:
74 case PIPE_CAP_TEXTURE_SHADOW_MAP:
75 case PIPE_CAP_NPOT_TEXTURES:
76 case PIPE_CAP_ANISOTROPIC_FILTER:
77 case PIPE_CAP_SEAMLESS_CUBE_MAP:
78 return 1;
79 case PIPE_CAP_SEAMLESS_CUBE_MAP_PER_TEXTURE:
80 return 0;
81 case PIPE_CAP_TWO_SIDED_STENCIL:
82 case PIPE_CAP_DEPTH_CLAMP:
83 case PIPE_CAP_DEPTHSTENCIL_CLEAR_SEPARATE:
84 case PIPE_CAP_POINT_SPRITE:
85 return 1;
86 case PIPE_CAP_GLSL:
87 case PIPE_CAP_SM3:
88 return 1;
89 case PIPE_CAP_MAX_RENDER_TARGETS:
90 return 8;
91 case PIPE_CAP_FRAGMENT_COLOR_CLAMP_CONTROL:
92 return 1;
93 case PIPE_CAP_TIMER_QUERY:
94 case PIPE_CAP_OCCLUSION_QUERY:
95 return 1;
96 case PIPE_CAP_STREAM_OUTPUT:
97 return 0;
98 case PIPE_CAP_BLEND_EQUATION_SEPARATE:
99 case PIPE_CAP_INDEP_BLEND_ENABLE:
100 case PIPE_CAP_INDEP_BLEND_FUNC:
101 return 1;
102 case PIPE_CAP_TGSI_FS_COORD_ORIGIN_UPPER_LEFT:
103 case PIPE_CAP_TGSI_FS_COORD_PIXEL_CENTER_HALF_INTEGER:
104 return 1;
105 case PIPE_CAP_TGSI_FS_COORD_ORIGIN_LOWER_LEFT:
106 case PIPE_CAP_TGSI_FS_COORD_PIXEL_CENTER_INTEGER:
107 return 0;
108 case PIPE_CAP_SHADER_STENCIL_EXPORT:
109 return 0;
110 case PIPE_CAP_PRIMITIVE_RESTART:
111 case PIPE_CAP_TGSI_INSTANCEID:
112 case PIPE_CAP_VERTEX_ELEMENT_INSTANCE_DIVISOR:
113 case PIPE_CAP_MIXED_COLORBUFFER_FORMATS:
114 return 1;
115 default:
116 NOUVEAU_ERR("unknown PIPE_CAP %d\n", param);
117 return 0;
118 }
119 }
120
121 static int
122 nvc0_screen_get_shader_param(struct pipe_screen *pscreen, unsigned shader,
123 enum pipe_shader_cap param)
124 {
125 switch (shader) {
126 case PIPE_SHADER_VERTEX:
127 /*
128 case PIPE_SHADER_TESSELLATION_CONTROL:
129 case PIPE_SHADER_TESSELLATION_EVALUATION:
130 */
131 case PIPE_SHADER_GEOMETRY:
132 case PIPE_SHADER_FRAGMENT:
133 break;
134 default:
135 return 0;
136 }
137
138 switch (param) {
139 case PIPE_SHADER_CAP_MAX_INSTRUCTIONS:
140 case PIPE_SHADER_CAP_MAX_ALU_INSTRUCTIONS:
141 case PIPE_SHADER_CAP_MAX_TEX_INSTRUCTIONS:
142 case PIPE_SHADER_CAP_MAX_TEX_INDIRECTIONS:
143 return 16384;
144 case PIPE_SHADER_CAP_MAX_CONTROL_FLOW_DEPTH:
145 return 4;
146 case PIPE_SHADER_CAP_MAX_INPUTS:
147 if (shader == PIPE_SHADER_VERTEX)
148 return 32;
149 return 0x300 / 16;
150 case PIPE_SHADER_CAP_MAX_CONSTS:
151 return 65536 / 16;
152 case PIPE_SHADER_CAP_MAX_CONST_BUFFERS:
153 return 14;
154 case PIPE_SHADER_CAP_MAX_ADDRS:
155 return 1;
156 case PIPE_SHADER_CAP_INDIRECT_INPUT_ADDR:
157 case PIPE_SHADER_CAP_INDIRECT_OUTPUT_ADDR:
158 return shader != PIPE_SHADER_FRAGMENT;
159 case PIPE_SHADER_CAP_INDIRECT_TEMP_ADDR:
160 case PIPE_SHADER_CAP_INDIRECT_CONST_ADDR:
161 return 1;
162 case PIPE_SHADER_CAP_MAX_PREDS:
163 return 0;
164 case PIPE_SHADER_CAP_MAX_TEMPS:
165 return NVC0_CAP_MAX_PROGRAM_TEMPS;
166 case PIPE_SHADER_CAP_TGSI_CONT_SUPPORTED:
167 return 1;
168 case PIPE_SHADER_CAP_SUBROUTINES:
169 return 0; /* please inline, or provide function declarations */
170 default:
171 NOUVEAU_ERR("unknown PIPE_SHADER_CAP %d\n", param);
172 return 0;
173 }
174 }
175
176 static float
177 nvc0_screen_get_paramf(struct pipe_screen *pscreen, enum pipe_cap param)
178 {
179 switch (param) {
180 case PIPE_CAP_MAX_LINE_WIDTH:
181 case PIPE_CAP_MAX_LINE_WIDTH_AA:
182 return 10.0f;
183 case PIPE_CAP_MAX_POINT_WIDTH:
184 case PIPE_CAP_MAX_POINT_WIDTH_AA:
185 return 64.0f;
186 case PIPE_CAP_MAX_TEXTURE_ANISOTROPY:
187 return 16.0f;
188 case PIPE_CAP_MAX_TEXTURE_LOD_BIAS:
189 return 4.0f;
190 default:
191 NOUVEAU_ERR("unknown PIPE_CAP %d\n", param);
192 return 0.0f;
193 }
194 }
195
196 static void
197 nvc0_screen_destroy(struct pipe_screen *pscreen)
198 {
199 struct nvc0_screen *screen = nvc0_screen(pscreen);
200
201 nouveau_fence_wait(screen->base.fence.current);
202 nouveau_fence_ref(NULL, &screen->base.fence.current);
203
204 nouveau_bo_ref(NULL, &screen->text);
205 nouveau_bo_ref(NULL, &screen->tls);
206 nouveau_bo_ref(NULL, &screen->txc);
207 nouveau_bo_ref(NULL, &screen->fence.bo);
208 nouveau_bo_ref(NULL, &screen->vfetch_cache);
209
210 nouveau_resource_destroy(&screen->text_heap);
211
212 if (screen->tic.entries)
213 FREE(screen->tic.entries);
214
215 nouveau_mm_destroy(screen->mm_VRAM_fe0);
216
217 nouveau_grobj_free(&screen->fermi);
218 nouveau_grobj_free(&screen->eng2d);
219 nouveau_grobj_free(&screen->m2mf);
220
221 nouveau_screen_fini(&screen->base);
222
223 FREE(screen);
224 }
225
226 static int
227 nvc0_graph_set_macro(struct nvc0_screen *screen, uint32_t m, unsigned pos,
228 unsigned size, const uint32_t *data)
229 {
230 struct nouveau_channel *chan = screen->base.channel;
231
232 size /= 4;
233
234 BEGIN_RING(chan, RING_3D_(NVC0_GRAPH_MACRO_ID), 2);
235 OUT_RING (chan, (m - 0x3800) / 8);
236 OUT_RING (chan, pos);
237 BEGIN_RING_1I(chan, RING_3D_(NVC0_GRAPH_MACRO_UPLOAD_POS), size + 1);
238 OUT_RING (chan, pos);
239 OUT_RINGp (chan, data, size);
240
241 return pos + size;
242 }
243
244 static void
245 nvc0_magic_3d_init(struct nouveau_channel *chan)
246 {
247 BEGIN_RING(chan, RING_3D_(0x10cc), 1);
248 OUT_RING (chan, 0xff);
249 BEGIN_RING(chan, RING_3D_(0x10e0), 2);
250 OUT_RING(chan, 0xff);
251 OUT_RING(chan, 0xff);
252 BEGIN_RING(chan, RING_3D_(0x10ec), 2);
253 OUT_RING(chan, 0xff);
254 OUT_RING(chan, 0xff);
255 BEGIN_RING(chan, RING_3D_(0x074c), 1);
256 OUT_RING (chan, 0x3f);
257
258 BEGIN_RING(chan, RING_3D_(0x16a8), 1);
259 OUT_RING (chan, (3 << 16) | 3);
260 BEGIN_RING(chan, RING_3D_(0x1794), 1);
261 OUT_RING (chan, (2 << 16) | 2);
262 BEGIN_RING(chan, RING_3D_(0x0de8), 1);
263 OUT_RING (chan, 1);
264
265 #if 0 /* software method */
266 BEGIN_RING(chan, RING_3D_(0x1528), 1); /* MP poke */
267 OUT_RING (chan, 0);
268 #endif
269
270 BEGIN_RING(chan, RING_3D_(0x12ac), 1);
271 OUT_RING (chan, 0);
272 BEGIN_RING(chan, RING_3D_(0x0218), 1);
273 OUT_RING (chan, 0x10);
274 BEGIN_RING(chan, RING_3D_(0x10fc), 1);
275 OUT_RING (chan, 0x10);
276 BEGIN_RING(chan, RING_3D_(0x1290), 1);
277 OUT_RING (chan, 0x10);
278 BEGIN_RING(chan, RING_3D_(0x12d8), 2);
279 OUT_RING (chan, 0x10);
280 OUT_RING (chan, 0x10);
281 BEGIN_RING(chan, RING_3D_(0x06d4), 1);
282 OUT_RING (chan, 8);
283 BEGIN_RING(chan, RING_3D_(0x1140), 1);
284 OUT_RING (chan, 0x10);
285 BEGIN_RING(chan, RING_3D_(0x1610), 1);
286 OUT_RING (chan, 0xe);
287
288 BEGIN_RING(chan, RING_3D_(0x164c), 1);
289 OUT_RING (chan, 1 << 12);
290 BEGIN_RING(chan, RING_3D_(0x151c), 1);
291 OUT_RING (chan, 1);
292 BEGIN_RING(chan, RING_3D_(0x030c), 1);
293 OUT_RING (chan, 0);
294 BEGIN_RING(chan, RING_3D_(0x0300), 1);
295 OUT_RING (chan, 3);
296 #if 0 /* software method */
297 BEGIN_RING(chan, RING_3D_(0x1280), 1); /* PGRAPH poke */
298 OUT_RING (chan, 0);
299 #endif
300 BEGIN_RING(chan, RING_3D_(0x02d0), 1);
301 OUT_RING (chan, 0x1f40);
302 BEGIN_RING(chan, RING_3D_(0x00fdc), 1);
303 OUT_RING (chan, 1);
304 BEGIN_RING(chan, RING_3D_(0x19c0), 1);
305 OUT_RING (chan, 1);
306 BEGIN_RING(chan, RING_3D_(0x075c), 1);
307 OUT_RING (chan, 3);
308 }
309
310 static void
311 nvc0_screen_fence_emit(struct pipe_screen *pscreen, u32 sequence)
312 {
313 struct nvc0_screen *screen = nvc0_screen(pscreen);
314 struct nouveau_channel *chan = screen->base.channel;
315
316 MARK_RING (chan, 5, 2);
317 BEGIN_RING(chan, RING_3D(QUERY_ADDRESS_HIGH), 4);
318 OUT_RELOCh(chan, screen->fence.bo, 0, NOUVEAU_BO_WR);
319 OUT_RELOCl(chan, screen->fence.bo, 0, NOUVEAU_BO_WR);
320 OUT_RING (chan, sequence);
321 OUT_RING (chan, NVC0_3D_QUERY_GET_FENCE | NVC0_3D_QUERY_GET_SHORT |
322 (0xf << NVC0_3D_QUERY_GET_UNIT__SHIFT));
323 }
324
325 static u32
326 nvc0_screen_fence_update(struct pipe_screen *pscreen)
327 {
328 struct nvc0_screen *screen = nvc0_screen(pscreen);
329 return screen->fence.map[0];
330 }
331
332 #define FAIL_SCREEN_INIT(str, err) \
333 do { \
334 NOUVEAU_ERR(str, err); \
335 nvc0_screen_destroy(pscreen); \
336 return NULL; \
337 } while(0)
338
339 struct pipe_screen *
340 nvc0_screen_create(struct pipe_winsys *ws, struct nouveau_device *dev)
341 {
342 struct nvc0_screen *screen;
343 struct nouveau_channel *chan;
344 struct pipe_screen *pscreen;
345 int ret;
346 unsigned i;
347
348 screen = CALLOC_STRUCT(nvc0_screen);
349 if (!screen)
350 return NULL;
351 pscreen = &screen->base.base;
352
353 screen->base.sysmem_bindings = PIPE_BIND_CONSTANT_BUFFER;
354
355 ret = nouveau_screen_init(&screen->base, dev);
356 if (ret) {
357 nvc0_screen_destroy(pscreen);
358 return NULL;
359 }
360 chan = screen->base.channel;
361
362 pscreen->winsys = ws;
363 pscreen->destroy = nvc0_screen_destroy;
364 pscreen->context_create = nvc0_create;
365 pscreen->is_format_supported = nvc0_screen_is_format_supported;
366 pscreen->get_param = nvc0_screen_get_param;
367 pscreen->get_shader_param = nvc0_screen_get_shader_param;
368 pscreen->get_paramf = nvc0_screen_get_paramf;
369
370 nvc0_screen_init_resource_functions(pscreen);
371
372 ret = nouveau_bo_new(dev, NOUVEAU_BO_GART | NOUVEAU_BO_MAP, 0, 4096,
373 &screen->fence.bo);
374 if (ret)
375 goto fail;
376 nouveau_bo_map(screen->fence.bo, NOUVEAU_BO_RDWR);
377 screen->fence.map = screen->fence.bo->map;
378 nouveau_bo_unmap(screen->fence.bo);
379 screen->base.fence.emit = nvc0_screen_fence_emit;
380 screen->base.fence.update = nvc0_screen_fence_update;
381
382 for (i = 0; i < NVC0_SCRATCH_NR_BUFFERS; ++i) {
383 ret = nouveau_bo_new(dev, NOUVEAU_BO_GART, 0, NVC0_SCRATCH_SIZE,
384 &screen->scratch.bo[i]);
385 if (ret)
386 goto fail;
387 }
388
389 ret = nouveau_grobj_alloc(chan, 0xbeef9039, NVC0_M2MF, &screen->m2mf);
390 if (ret)
391 FAIL_SCREEN_INIT("Error allocating PGRAPH context for M2MF: %d\n", ret);
392
393 BIND_RING (chan, screen->m2mf, NVC0_SUBCH_MF);
394 BEGIN_RING(chan, RING_MF(NOTIFY_ADDRESS_HIGH), 3);
395 OUT_RELOCh(chan, screen->fence.bo, 16, NOUVEAU_BO_GART | NOUVEAU_BO_RDWR);
396 OUT_RELOCl(chan, screen->fence.bo, 16, NOUVEAU_BO_GART | NOUVEAU_BO_RDWR);
397 OUT_RING (chan, 0);
398
399 ret = nouveau_grobj_alloc(chan, 0xbeef902d, NVC0_2D, &screen->eng2d);
400 if (ret)
401 FAIL_SCREEN_INIT("Error allocating PGRAPH context for 2D: %d\n", ret);
402
403 BIND_RING (chan, screen->eng2d, NVC0_SUBCH_2D);
404 BEGIN_RING(chan, RING_2D(OPERATION), 1);
405 OUT_RING (chan, NVC0_2D_OPERATION_SRCCOPY);
406 BEGIN_RING(chan, RING_2D(CLIP_ENABLE), 1);
407 OUT_RING (chan, 0);
408 BEGIN_RING(chan, RING_2D(COLOR_KEY_ENABLE), 1);
409 OUT_RING (chan, 0);
410 BEGIN_RING(chan, RING_2D_(0x0884), 1);
411 OUT_RING (chan, 0x3f);
412 BEGIN_RING(chan, RING_2D_(0x0888), 1);
413 OUT_RING (chan, 1);
414
415 ret = nouveau_grobj_alloc(chan, 0xbeef9097, NVC0_3D, &screen->fermi);
416 if (ret)
417 FAIL_SCREEN_INIT("Error allocating PGRAPH context for 3D: %d\n", ret);
418
419 BIND_RING (chan, screen->fermi, NVC0_SUBCH_3D);
420 BEGIN_RING(chan, RING_3D(NOTIFY_ADDRESS_HIGH), 3);
421 OUT_RELOCh(chan, screen->fence.bo, 32, NOUVEAU_BO_GART | NOUVEAU_BO_RDWR);
422 OUT_RELOCl(chan, screen->fence.bo, 32, NOUVEAU_BO_GART | NOUVEAU_BO_RDWR);
423 OUT_RING (chan, 0);
424
425 BEGIN_RING(chan, RING_3D(COND_MODE), 1);
426 OUT_RING (chan, NVC0_3D_COND_MODE_ALWAYS);
427
428 BEGIN_RING(chan, RING_3D(RT_CONTROL), 1);
429 OUT_RING (chan, 1);
430
431 BEGIN_RING(chan, RING_3D(CSAA_ENABLE), 1);
432 OUT_RING (chan, 0);
433 BEGIN_RING(chan, RING_3D(MULTISAMPLE_ENABLE), 1);
434 OUT_RING (chan, 0);
435 BEGIN_RING(chan, RING_3D(MULTISAMPLE_MODE), 1);
436 OUT_RING (chan, NVC0_3D_MULTISAMPLE_MODE_1X);
437 BEGIN_RING(chan, RING_3D(MULTISAMPLE_CTRL), 1);
438 OUT_RING (chan, 0);
439 BEGIN_RING(chan, RING_3D(LINE_WIDTH_SEPARATE), 1);
440 OUT_RING (chan, 1);
441 BEGIN_RING(chan, RING_3D(LINE_LAST_PIXEL), 1);
442 OUT_RING (chan, 0);
443 BEGIN_RING(chan, RING_3D(BLEND_SEPARATE_ALPHA), 1);
444 OUT_RING (chan, 1);
445 BEGIN_RING(chan, RING_3D(BLEND_ENABLE_COMMON), 1);
446 OUT_RING (chan, 0);
447 BEGIN_RING(chan, RING_3D(TEX_MISC), 1);
448 OUT_RING (chan, NVC0_3D_TEX_MISC_SEAMLESS_CUBE_MAP);
449
450 nvc0_magic_3d_init(chan);
451
452 ret = nouveau_bo_new(dev, NOUVEAU_BO_VRAM, 1 << 17, 1 << 20, &screen->text);
453 if (ret)
454 goto fail;
455
456 /* XXX: getting a page fault at the end of the code buffer every few
457 * launches, don't use the last 256 bytes to work around them - prefetch ?
458 */
459 nouveau_resource_init(&screen->text_heap, 0, (1 << 20) - 0x100);
460
461 ret = nouveau_bo_new(dev, NOUVEAU_BO_VRAM, 1 << 12, 6 << 16,
462 &screen->uniforms);
463 if (ret)
464 goto fail;
465
466 /* auxiliary constants (6 user clip planes, base instance id) */
467 BEGIN_RING(chan, RING_3D(CB_SIZE), 3);
468 OUT_RING (chan, 256);
469 OUT_RELOCh(chan, screen->uniforms, 5 << 16, NOUVEAU_BO_VRAM | NOUVEAU_BO_RD);
470 OUT_RELOCl(chan, screen->uniforms, 5 << 16, NOUVEAU_BO_VRAM | NOUVEAU_BO_RD);
471 for (i = 0; i < 5; ++i) {
472 BEGIN_RING(chan, RING_3D(CB_BIND(i)), 1);
473 OUT_RING (chan, (15 << 4) | 1);
474 }
475
476 screen->tls_size = (16 * 32) * (NVC0_CAP_MAX_PROGRAM_TEMPS * 16);
477 ret = nouveau_bo_new(dev, NOUVEAU_BO_VRAM, 1 << 17,
478 screen->tls_size, &screen->tls);
479 if (ret)
480 goto fail;
481
482 BEGIN_RING(chan, RING_3D(CODE_ADDRESS_HIGH), 2);
483 OUT_RELOCh(chan, screen->text, 0, NOUVEAU_BO_VRAM | NOUVEAU_BO_RD);
484 OUT_RELOCl(chan, screen->text, 0, NOUVEAU_BO_VRAM | NOUVEAU_BO_RD);
485 BEGIN_RING(chan, RING_3D(LOCAL_ADDRESS_HIGH), 4);
486 OUT_RELOCh(chan, screen->tls, 0, NOUVEAU_BO_VRAM | NOUVEAU_BO_RDWR);
487 OUT_RELOCl(chan, screen->tls, 0, NOUVEAU_BO_VRAM | NOUVEAU_BO_RDWR);
488 OUT_RING (chan, screen->tls_size >> 32);
489 OUT_RING (chan, screen->tls_size);
490 BEGIN_RING(chan, RING_3D_(0x07a0), 1);
491 OUT_RING (chan, 0);
492 BEGIN_RING(chan, RING_3D(LOCAL_BASE), 1);
493 OUT_RING (chan, 0);
494
495 for (i = 0; i < 5; ++i) {
496 BEGIN_RING(chan, RING_3D(TEX_LIMITS(i)), 1);
497 OUT_RING (chan, 0x54);
498 }
499 BEGIN_RING(chan, RING_3D(LINKED_TSC), 1);
500 OUT_RING (chan, 0);
501
502 ret = nouveau_bo_new(dev, NOUVEAU_BO_VRAM, 1 << 17, 1 << 20,
503 &screen->vfetch_cache);
504 if (ret)
505 goto fail;
506
507 BEGIN_RING(chan, RING_3D(VERTEX_QUARANTINE_ADDRESS_HIGH), 3);
508 OUT_RELOCh(chan, screen->vfetch_cache, 0, NOUVEAU_BO_VRAM | NOUVEAU_BO_RDWR);
509 OUT_RELOCl(chan, screen->vfetch_cache, 0, NOUVEAU_BO_VRAM | NOUVEAU_BO_RDWR);
510 OUT_RING (chan, 3);
511
512 ret = nouveau_bo_new(dev, NOUVEAU_BO_VRAM, 1 << 17, 1 << 17, &screen->txc);
513 if (ret)
514 goto fail;
515
516 BEGIN_RING(chan, RING_3D(TIC_ADDRESS_HIGH), 3);
517 OUT_RELOCh(chan, screen->txc, 0, NOUVEAU_BO_VRAM | NOUVEAU_BO_RD);
518 OUT_RELOCl(chan, screen->txc, 0, NOUVEAU_BO_VRAM | NOUVEAU_BO_RD);
519 OUT_RING (chan, NVC0_TIC_MAX_ENTRIES - 1);
520
521 BEGIN_RING(chan, RING_3D(TSC_ADDRESS_HIGH), 3);
522 OUT_RELOCh(chan, screen->txc, 65536, NOUVEAU_BO_VRAM | NOUVEAU_BO_RD);
523 OUT_RELOCl(chan, screen->txc, 65536, NOUVEAU_BO_VRAM | NOUVEAU_BO_RD);
524 OUT_RING (chan, NVC0_TSC_MAX_ENTRIES - 1);
525
526 BEGIN_RING(chan, RING_3D(SCREEN_Y_CONTROL), 1);
527 OUT_RING (chan, 0);
528 BEGIN_RING(chan, RING_3D(WINDOW_OFFSET_X), 2);
529 OUT_RING (chan, 0);
530 OUT_RING (chan, 0);
531 BEGIN_RING(chan, RING_3D_(0x1590), 1); /* deactivate ZCULL */
532 OUT_RING (chan, 0x3f);
533
534 BEGIN_RING(chan, RING_3D(CLIP_RECTS_MODE), 1);
535 OUT_RING (chan, NVC0_3D_CLIP_RECTS_MODE_INSIDE_ANY);
536 BEGIN_RING(chan, RING_3D(CLIP_RECT_HORIZ(0)), 8 * 2);
537 for (i = 0; i < 8 * 2; ++i)
538 OUT_RING(chan, 0);
539 BEGIN_RING(chan, RING_3D(CLIP_RECTS_EN), 1);
540 OUT_RING (chan, 0);
541 BEGIN_RING(chan, RING_3D(CLIPID_ENABLE), 1);
542 OUT_RING (chan, 0);
543
544 /* neither scissors, viewport nor stencil mask should affect clears */
545 BEGIN_RING(chan, RING_3D(CLEAR_FLAGS), 1);
546 OUT_RING (chan, 0);
547
548 BEGIN_RING(chan, RING_3D(VIEWPORT_TRANSFORM_EN), 1);
549 OUT_RING (chan, 1);
550 BEGIN_RING(chan, RING_3D(DEPTH_RANGE_NEAR(0)), 2);
551 OUT_RINGf (chan, 0.0f);
552 OUT_RINGf (chan, 1.0f);
553 BEGIN_RING(chan, RING_3D(VIEW_VOLUME_CLIP_CTRL), 1);
554 OUT_RING (chan, NVC0_3D_VIEW_VOLUME_CLIP_CTRL_UNK1_UNK1);
555
556 /* We use scissors instead of exact view volume clipping,
557 * so they're always enabled.
558 */
559 BEGIN_RING(chan, RING_3D(SCISSOR_ENABLE(0)), 3);
560 OUT_RING (chan, 1);
561 OUT_RING (chan, 8192 << 16);
562 OUT_RING (chan, 8192 << 16);
563
564 #define MK_MACRO(m, n) i = nvc0_graph_set_macro(screen, m, i, sizeof(n), n);
565
566 i = 0;
567 MK_MACRO(NVC0_3D_BLEND_ENABLES, nvc0_9097_blend_enables);
568 MK_MACRO(NVC0_3D_VERTEX_ARRAY_SELECT, nvc0_9097_vertex_array_select);
569 MK_MACRO(NVC0_3D_TEP_SELECT, nvc0_9097_tep_select);
570 MK_MACRO(NVC0_3D_GP_SELECT, nvc0_9097_gp_select);
571 MK_MACRO(NVC0_3D_POLYGON_MODE_FRONT, nvc0_9097_poly_mode_front);
572 MK_MACRO(NVC0_3D_POLYGON_MODE_BACK, nvc0_9097_poly_mode_back);
573
574 BEGIN_RING(chan, RING_3D(RASTERIZE_ENABLE), 1);
575 OUT_RING (chan, 1);
576 BEGIN_RING(chan, RING_3D(RT_SEPARATE_FRAG_DATA), 1);
577 OUT_RING (chan, 1);
578 BEGIN_RING(chan, RING_3D(GP_SELECT), 1);
579 OUT_RING (chan, 0x40);
580 BEGIN_RING(chan, RING_3D(LAYER), 1);
581 OUT_RING (chan, 0);
582 BEGIN_RING(chan, RING_3D(TEP_SELECT), 1);
583 OUT_RING (chan, 0x30);
584 BEGIN_RING(chan, RING_3D(PATCH_VERTICES), 1);
585 OUT_RING (chan, 3);
586 BEGIN_RING(chan, RING_3D(SP_SELECT(2)), 1);
587 OUT_RING (chan, 0x20);
588 BEGIN_RING(chan, RING_3D(SP_SELECT(0)), 1);
589 OUT_RING (chan, 0x00);
590
591 BEGIN_RING(chan, RING_3D(POINT_COORD_REPLACE), 1);
592 OUT_RING (chan, 0);
593 BEGIN_RING(chan, RING_3D(POINT_RASTER_RULES), 1);
594 OUT_RING (chan, NVC0_3D_POINT_RASTER_RULES_OGL);
595
596 BEGIN_RING(chan, RING_3D(EDGEFLAG_ENABLE), 1);
597 OUT_RING (chan, 1);
598
599 BEGIN_RING(chan, RING_3D(VERTEX_RUNOUT_ADDRESS_HIGH), 2);
600 OUT_RING (chan, 0xab);
601 OUT_RING (chan, 0x00000000);
602
603 FIRE_RING (chan);
604
605 screen->tic.entries = CALLOC(4096, sizeof(void *));
606 screen->tsc.entries = screen->tic.entries + 2048;
607
608 screen->mm_VRAM_fe0 = nouveau_mm_create(dev, NOUVEAU_BO_VRAM, 0xfe0);
609
610 nouveau_fence_new(&screen->base, &screen->base.fence.current, FALSE);
611
612 return pscreen;
613
614 fail:
615 nvc0_screen_destroy(pscreen);
616 return NULL;
617 }
618
619 void
620 nvc0_screen_make_buffers_resident(struct nvc0_screen *screen)
621 {
622 struct nouveau_channel *chan = screen->base.channel;
623
624 const unsigned flags = NOUVEAU_BO_VRAM | NOUVEAU_BO_RD;
625
626 MARK_RING(chan, 5, 5);
627 nouveau_bo_validate(chan, screen->text, flags);
628 nouveau_bo_validate(chan, screen->uniforms, flags);
629 nouveau_bo_validate(chan, screen->txc, flags);
630 nouveau_bo_validate(chan, screen->vfetch_cache, flags);
631
632 if (screen->cur_ctx && screen->cur_ctx->state.tls_required)
633 nouveau_bo_validate(chan, screen->tls, flags);
634 }
635
636 int
637 nvc0_screen_tic_alloc(struct nvc0_screen *screen, void *entry)
638 {
639 int i = screen->tic.next;
640
641 while (screen->tic.lock[i / 32] & (1 << (i % 32)))
642 i = (i + 1) & (NVC0_TIC_MAX_ENTRIES - 1);
643
644 screen->tic.next = (i + 1) & (NVC0_TIC_MAX_ENTRIES - 1);
645
646 if (screen->tic.entries[i])
647 nv50_tic_entry(screen->tic.entries[i])->id = -1;
648
649 screen->tic.entries[i] = entry;
650 return i;
651 }
652
653 int
654 nvc0_screen_tsc_alloc(struct nvc0_screen *screen, void *entry)
655 {
656 int i = screen->tsc.next;
657
658 while (screen->tsc.lock[i / 32] & (1 << (i % 32)))
659 i = (i + 1) & (NVC0_TSC_MAX_ENTRIES - 1);
660
661 screen->tsc.next = (i + 1) & (NVC0_TSC_MAX_ENTRIES - 1);
662
663 if (screen->tsc.entries[i])
664 nv50_tsc_entry(screen->tsc.entries[i])->id = -1;
665
666 screen->tsc.entries[i] = entry;
667 return i;
668 }
Mirror of AROS' svn.