revert between 56095 -> 55830 in arch
[AROS.git] / workbench / libs / mesa / src / gallium / drivers / nvc0 / nvc0_screen.h
blob015807e2f5d97fabb90adef8b65547dd2e18124b
1 #ifndef __NVC0_SCREEN_H__
2 #define __NVC0_SCREEN_H__
4 #define NOUVEAU_NVC0
5 #include "nouveau/nouveau_screen.h"
6 #include "nouveau/nouveau_mm.h"
7 #undef NOUVEAU_NVC0
8 #include "nvc0_winsys.h"
9 #include "nvc0_stateobj.h"
11 #define NVC0_TIC_MAX_ENTRIES 2048
12 #define NVC0_TSC_MAX_ENTRIES 2048
14 struct nvc0_context;
16 #define NVC0_SCRATCH_SIZE (2 << 20)
17 #define NVC0_SCRATCH_NR_BUFFERS 2
19 #define NVC0_SCREEN_RESIDENT_BO_COUNT 5
21 struct nvc0_screen {
22 struct nouveau_screen base;
23 struct nouveau_winsys *nvws;
25 struct nvc0_context *cur_ctx;
27 struct nouveau_bo *text;
28 struct nouveau_bo *uniforms;
29 struct nouveau_bo *tls;
30 struct nouveau_bo *txc; /* TIC (offset 0) and TSC (65536) */
31 struct nouveau_bo *vfetch_cache;
33 uint64_t tls_size;
35 struct nouveau_resource *text_heap;
37 struct {
38 struct nouveau_bo *bo[NVC0_SCRATCH_NR_BUFFERS];
39 uint8_t *buf;
40 int index;
41 uint32_t offset;
42 } scratch;
44 struct {
45 void **entries;
46 int next;
47 uint32_t lock[NVC0_TIC_MAX_ENTRIES / 32];
48 } tic;
50 struct {
51 void **entries;
52 int next;
53 uint32_t lock[NVC0_TSC_MAX_ENTRIES / 32];
54 } tsc;
56 struct {
57 struct nouveau_bo *bo;
58 uint32_t *map;
59 } fence;
61 struct nouveau_mman *mm_VRAM_fe0;
63 struct nouveau_grobj *fermi;
64 struct nouveau_grobj *eng2d;
65 struct nouveau_grobj *m2mf;
68 static INLINE struct nvc0_screen *
69 nvc0_screen(struct pipe_screen *screen)
71 return (struct nvc0_screen *)screen;
74 void nvc0_screen_make_buffers_resident(struct nvc0_screen *);
76 int nvc0_screen_tic_alloc(struct nvc0_screen *, void *);
77 int nvc0_screen_tsc_alloc(struct nvc0_screen *, void *);
79 static INLINE void
80 nvc0_resource_fence(struct nv04_resource *res, uint32_t flags)
82 struct nvc0_screen *screen = nvc0_screen(res->base.screen);
84 if (res->mm) {
85 nouveau_fence_ref(screen->base.fence.current, &res->fence);
87 if (flags & NOUVEAU_BO_WR)
88 nouveau_fence_ref(screen->base.fence.current, &res->fence_wr);
92 static INLINE void
93 nvc0_resource_validate(struct nv04_resource *res, uint32_t flags)
95 struct nvc0_screen *screen = nvc0_screen(res->base.screen);
97 if (likely(res->bo)) {
98 nouveau_bo_validate(screen->base.channel, res->bo, flags);
100 if (flags & NOUVEAU_BO_WR)
101 res->status |= NOUVEAU_BUFFER_STATUS_GPU_WRITING;
102 if (flags & NOUVEAU_BO_RD)
103 res->status |= NOUVEAU_BUFFER_STATUS_GPU_READING;
105 nvc0_resource_fence(res, flags);
109 struct nvc0_format {
110 uint32_t rt;
111 uint32_t tic;
112 uint32_t vtx;
113 uint32_t usage;
116 extern const struct nvc0_format nvc0_format_table[];
118 static INLINE void
119 nvc0_screen_tic_unlock(struct nvc0_screen *screen, struct nv50_tic_entry *tic)
121 if (tic->id >= 0)
122 screen->tic.lock[tic->id / 32] &= ~(1 << (tic->id % 32));
125 static INLINE void
126 nvc0_screen_tsc_unlock(struct nvc0_screen *screen, struct nv50_tsc_entry *tsc)
128 if (tsc->id >= 0)
129 screen->tsc.lock[tsc->id / 32] &= ~(1 << (tsc->id % 32));
132 static INLINE void
133 nvc0_screen_tic_free(struct nvc0_screen *screen, struct nv50_tic_entry *tic)
135 if (tic->id >= 0) {
136 screen->tic.entries[tic->id] = NULL;
137 screen->tic.lock[tic->id / 32] &= ~(1 << (tic->id % 32));
141 static INLINE void
142 nvc0_screen_tsc_free(struct nvc0_screen *screen, struct nv50_tsc_entry *tsc)
144 if (tsc->id >= 0) {
145 screen->tsc.entries[tsc->id] = NULL;
146 screen->tsc.lock[tsc->id / 32] &= ~(1 << (tsc->id % 32));
150 #endif