workbench/libs/mesa/src/gallium/drivers/nvfx/nvfx_screen.c

   1 #include "pipe/p_screen.h"
   2 #include "pipe/p_state.h"
   3 #include "util/u_format.h"
   4 #include "util/u_format_s3tc.h"
   5 #include "util/u_simple_screen.h"
   6
   7 #include "nouveau/nouveau_screen.h"
   8 #include "nouveau/nv_object.xml.h"
   9 #include "nvfx_context.h"
  10 #include "nvfx_screen.h"
  11 #include "nvfx_resource.h"
  12 #include "nvfx_tex.h"
  13
  14 #define NV30_3D_CHIPSET_3X_MASK 0x00000003
  15 #define NV34_3D_CHIPSET_3X_MASK 0x00000010
  16 #define NV35_3D_CHIPSET_3X_MASK 0x000001e0
  17
  18 #define NV4X_GRCLASS4097_CHIPSETS 0x00000baf
  19 #define NV4X_GRCLASS4497_CHIPSETS 0x00005450
  20 #define NV6X_GRCLASS4497_CHIPSETS 0x00000088
  21
  22 static int
  23 nvfx_screen_get_param(struct pipe_screen *pscreen, enum pipe_cap param)
  24 {
  25         struct nvfx_screen *screen = nvfx_screen(pscreen);
  26
  27         switch (param) {
  28         case PIPE_CAP_MAX_TEXTURE_IMAGE_UNITS:
  29                 return 16;
  30         case PIPE_CAP_NPOT_TEXTURES:
  31                 return screen->advertise_npot;
  32         case PIPE_CAP_TWO_SIDED_STENCIL:
  33                 return 1;
  34         case PIPE_CAP_GLSL:
  35                 return 1;
  36         case PIPE_CAP_SM3:
  37                 /* TODO: >= nv4x support Shader Model 3.0 */
  38                 return 0;
  39         case PIPE_CAP_ANISOTROPIC_FILTER:
  40                 return 1;
  41         case PIPE_CAP_POINT_SPRITE:
  42                 return 1;
  43         case PIPE_CAP_MAX_RENDER_TARGETS:
  44                 return screen->use_nv4x ? 4 : 1;
  45         case PIPE_CAP_OCCLUSION_QUERY:
  46                 return 1;
  47         case PIPE_CAP_TIMER_QUERY:
  48                 return 0;
  49         case PIPE_CAP_TEXTURE_SHADOW_MAP:
  50                 return 1;
  51         case PIPE_CAP_TEXTURE_SWIZZLE:
  52                 return 1;
  53         case PIPE_CAP_MAX_TEXTURE_2D_LEVELS:
  54                 return 13;
  55         case PIPE_CAP_MAX_TEXTURE_3D_LEVELS:
  56                 return 10;
  57         case PIPE_CAP_MAX_TEXTURE_CUBE_LEVELS:
  58                 return 13;
  59         case PIPE_CAP_TEXTURE_MIRROR_CLAMP:
  60                 return !!screen->use_nv4x;
  61         case PIPE_CAP_TEXTURE_MIRROR_REPEAT:
  62                 return 1;
  63         case PIPE_CAP_MAX_VERTEX_TEXTURE_UNITS:
  64                 return 0; /* We have 4 on nv40 - but unsupported currently */
  65         case PIPE_CAP_BLEND_EQUATION_SEPARATE:
  66                 return screen->advertise_blend_equation_separate;
  67         case PIPE_CAP_MAX_COMBINED_SAMPLERS:
  68                 return 16;
  69         case PIPE_CAP_INDEP_BLEND_ENABLE:
  70                 /* TODO: on nv40 we have separate color masks */
  71                 /* TODO: nv40 mrt blending is probably broken */
  72                 return 0;
  73         case PIPE_CAP_INDEP_BLEND_FUNC:
  74                 return 0;
  75         case PIPE_CAP_DEPTHSTENCIL_CLEAR_SEPARATE:
  76                 return 0;
  77         case PIPE_CAP_TGSI_FS_COORD_ORIGIN_LOWER_LEFT:
  78         case PIPE_CAP_TGSI_FS_COORD_PIXEL_CENTER_HALF_INTEGER:
  79         case PIPE_CAP_TGSI_FS_COORD_ORIGIN_UPPER_LEFT:
  80         case PIPE_CAP_TGSI_FS_COORD_PIXEL_CENTER_INTEGER:
  81                 return 1;
  82         case PIPE_CAP_DEPTH_CLAMP:
  83                 return 0; // TODO: implement depth clamp
  84         case PIPE_CAP_PRIMITIVE_RESTART:
  85                 return 0; // TODO: implement primitive restart
  86         case PIPE_CAP_ARRAY_TEXTURES:
  87         case PIPE_CAP_TGSI_INSTANCEID:
  88         case PIPE_CAP_VERTEX_ELEMENT_INSTANCE_DIVISOR:
  89         case PIPE_CAP_FRAGMENT_COLOR_CLAMP_CONTROL:
  90         case PIPE_CAP_SEAMLESS_CUBE_MAP:
  91         case PIPE_CAP_SEAMLESS_CUBE_MAP_PER_TEXTURE:
  92         case PIPE_CAP_SHADER_STENCIL_EXPORT:
  93                 return 0;
  94         case PIPE_CAP_MIXED_COLORBUFFER_FORMATS:
  95                 return 0;
  96         default:
  97                 NOUVEAU_ERR("Warning: unknown PIPE_CAP %d\n", param);
  98                 return 0;
  99         }
 100 }
 101
 102 static int
 103 nvfx_screen_get_shader_param(struct pipe_screen *pscreen, unsigned shader, enum pipe_shader_cap param)
 104 {
 105         struct nvfx_screen *screen = nvfx_screen(pscreen);
 106
 107         switch(shader) {
 108         case PIPE_SHADER_FRAGMENT:
 109                 switch(param) {
 110                 case PIPE_SHADER_CAP_MAX_INSTRUCTIONS:
 111                 case PIPE_SHADER_CAP_MAX_ALU_INSTRUCTIONS:
 112                 case PIPE_SHADER_CAP_MAX_TEX_INSTRUCTIONS:
 113                 case PIPE_SHADER_CAP_MAX_TEX_INDIRECTIONS:
 114                         return 4096;
 115                 case PIPE_SHADER_CAP_MAX_CONTROL_FLOW_DEPTH:
 116                         /* FIXME: is it the dynamic (nv30:0/nv40:24) or the static
 117                          value (nv30:0/nv40:4) ? */
 118                         return screen->use_nv4x ? 4 : 0;
 119                 case PIPE_SHADER_CAP_MAX_INPUTS:
 120                         return screen->use_nv4x ? 12 : 10;
 121                 case PIPE_SHADER_CAP_MAX_CONSTS:
 122                         return screen->use_nv4x ? 224 : 32;
 123                 case PIPE_SHADER_CAP_MAX_CONST_BUFFERS:
 124                     return 1;
 125                 case PIPE_SHADER_CAP_MAX_TEMPS:
 126                         return 32;
 127                 case PIPE_SHADER_CAP_MAX_ADDRS:
 128                         return screen->use_nv4x ? 1 : 0;
 129                 case PIPE_SHADER_CAP_MAX_PREDS:
 130                         return 0; /* we could expose these, but nothing uses them */
 131                 case PIPE_SHADER_CAP_TGSI_CONT_SUPPORTED:
 132                     return 0;
 133                 case PIPE_SHADER_CAP_INDIRECT_INPUT_ADDR:
 134                 case PIPE_SHADER_CAP_INDIRECT_OUTPUT_ADDR:
 135                 case PIPE_SHADER_CAP_INDIRECT_TEMP_ADDR:
 136                 case PIPE_SHADER_CAP_INDIRECT_CONST_ADDR:
 137                         return 0;
 138                 case PIPE_SHADER_CAP_SUBROUTINES:
 139                         return screen->use_nv4x ? 1 : 0;
 140                 default:
 141                         break;
 142                 }
 143                 break;
 144         case PIPE_SHADER_VERTEX:
 145                 switch(param) {
 146                 case PIPE_SHADER_CAP_MAX_INSTRUCTIONS:
 147                 case PIPE_SHADER_CAP_MAX_ALU_INSTRUCTIONS:
 148                         return screen->use_nv4x ? 512 : 256;
 149                 case PIPE_SHADER_CAP_MAX_TEX_INSTRUCTIONS:
 150                 case PIPE_SHADER_CAP_MAX_TEX_INDIRECTIONS:
 151                         return screen->use_nv4x ? 512 : 0;
 152                 case PIPE_SHADER_CAP_MAX_CONTROL_FLOW_DEPTH:
 153                         /* FIXME: is it the dynamic (nv30:24/nv40:24) or the static
 154                          value (nv30:1/nv40:4) ? */
 155                         return screen->use_nv4x ? 4 : 1;
 156                 case PIPE_SHADER_CAP_MAX_INPUTS:
 157                         return 16;
 158                 case PIPE_SHADER_CAP_MAX_CONSTS:
 159                         /* - 6 is for clip planes; Gallium should be fixed to put
 160                          * them in the vertex shader itself, so we don't need to reserve these */
 161                         return (screen->use_nv4x ? 468 : 256) - 6;
 162                      case PIPE_SHADER_CAP_MAX_CONST_BUFFERS:
 163                             return 1;
 164                 case PIPE_SHADER_CAP_MAX_TEMPS:
 165                         return screen->use_nv4x ? 32 : 13;
 166                 case PIPE_SHADER_CAP_MAX_ADDRS:
 167                         return 2;
 168                 case PIPE_SHADER_CAP_MAX_PREDS:
 169                         return 0; /* we could expose these, but nothing uses them */
 170                 case PIPE_SHADER_CAP_TGSI_CONT_SUPPORTED:
 171                         return 1;
 172                 case PIPE_SHADER_CAP_INDIRECT_INPUT_ADDR:
 173                 case PIPE_SHADER_CAP_INDIRECT_OUTPUT_ADDR:
 174                 case PIPE_SHADER_CAP_INDIRECT_TEMP_ADDR:
 175                         return 0;
 176                 case PIPE_SHADER_CAP_INDIRECT_CONST_ADDR:
 177                         return 1;
 178                 case PIPE_SHADER_CAP_SUBROUTINES:
 179                         return 1;
 180                 default:
 181                         break;
 182                 }
 183                 break;
 184         default:
 185                 break;
 186         }
 187         return 0;
 188 }
 189
 190 static float
 191 nvfx_screen_get_paramf(struct pipe_screen *pscreen, enum pipe_cap param)
 192 {
 193         struct nvfx_screen *screen = nvfx_screen(pscreen);
 194
 195         switch (param) {
 196         case PIPE_CAP_MAX_LINE_WIDTH:
 197         case PIPE_CAP_MAX_LINE_WIDTH_AA:
 198                 return 10.0;
 199         case PIPE_CAP_MAX_POINT_WIDTH:
 200         case PIPE_CAP_MAX_POINT_WIDTH_AA:
 201                 return 64.0;
 202         case PIPE_CAP_MAX_TEXTURE_ANISOTROPY:
 203                 return screen->use_nv4x ? 16.0 : 8.0;
 204         case PIPE_CAP_MAX_TEXTURE_LOD_BIAS:
 205                 return 15.0;
 206         default:
 207                 NOUVEAU_ERR("Unknown PIPE_CAP %d\n", param);
 208                 return 0.0;
 209         }
 210 }
 211
 212 static boolean
 213 nvfx_screen_is_format_supported(struct pipe_screen *pscreen,
 214                                      enum pipe_format format,
 215                                      enum pipe_texture_target target,
 216                                      unsigned sample_count,
 217                                      unsigned bind)
 218 {
 219         struct nvfx_screen *screen = nvfx_screen(pscreen);
 220
 221         if (!util_format_is_supported(format, bind))
 222                 return FALSE;
 223
 224          if (sample_count > 1)
 225                 return FALSE;
 226
 227         if (bind & PIPE_BIND_RENDER_TARGET) {
 228                 switch (format) {
 229                 case PIPE_FORMAT_B8G8R8A8_UNORM:
 230                 case PIPE_FORMAT_B8G8R8X8_UNORM:
 231                 case PIPE_FORMAT_R8G8B8A8_UNORM:
 232                 case PIPE_FORMAT_R8G8B8X8_UNORM:
 233                 case PIPE_FORMAT_B5G6R5_UNORM:
 234                         break;
 235                 case PIPE_FORMAT_R16G16B16A16_FLOAT:
 236                         if(!screen->advertise_fp16)
 237                                 return FALSE;
 238                         break;
 239                 case PIPE_FORMAT_R32G32B32A32_FLOAT:
 240                         if(!screen->advertise_fp32)
 241                                 return FALSE;
 242                         break;
 243                 default:
 244                         return FALSE;
 245                 }
 246         }
 247
 248         if (bind & PIPE_BIND_DEPTH_STENCIL) {
 249                 switch (format) {
 250                 case PIPE_FORMAT_S8_USCALED_Z24_UNORM:
 251                 case PIPE_FORMAT_X8Z24_UNORM:
 252                 case PIPE_FORMAT_Z16_UNORM:
 253                         break;
 254                 default:
 255                         return FALSE;
 256                 }
 257         }
 258
 259         if (bind & PIPE_BIND_SAMPLER_VIEW) {
 260                 struct nvfx_texture_format* tf = &nvfx_texture_formats[format];
 261                 if(util_format_is_s3tc(format) && !util_format_s3tc_enabled)
 262                         return FALSE;
 263                 if(format == PIPE_FORMAT_R16G16B16A16_FLOAT && !screen->advertise_fp16)
 264                         return FALSE;
 265                 if(format == PIPE_FORMAT_R32G32B32A32_FLOAT && !screen->advertise_fp32)
 266                         return FALSE;
 267                 if(screen->use_nv4x)
 268                 {
 269                         if(tf->fmt[4] < 0)
 270                                 return FALSE;
 271                 }
 272                 else
 273                 {
 274                         if(tf->fmt[0] < 0)
 275                                 return FALSE;
 276                 }
 277         }
 278
 279         // note that we do actually support everything through translate
 280         if (bind & PIPE_BIND_VERTEX_BUFFER) {
 281                 unsigned type = nvfx_vertex_formats[format];
 282                 if(!type)
 283                         return FALSE;
 284         }
 285
 286         if (bind & PIPE_BIND_INDEX_BUFFER) {
 287                 // 8-bit indices supported, but not in hardware index buffer
 288                 if(format != PIPE_FORMAT_R16_USCALED && format != PIPE_FORMAT_R32_USCALED)
 289                         return FALSE;
 290         }
 291
 292         if(bind & PIPE_BIND_STREAM_OUTPUT)
 293                 return FALSE;
 294
 295         return TRUE;
 296 }
 297
 298 static void
 299 nvfx_screen_destroy(struct pipe_screen *pscreen)
 300 {
 301         struct nvfx_screen *screen = nvfx_screen(pscreen);
 302
 303         nouveau_resource_destroy(&screen->vp_exec_heap);
 304         nouveau_resource_destroy(&screen->vp_data_heap);
 305         nouveau_resource_destroy(&screen->query_heap);
 306         nouveau_notifier_free(&screen->query);
 307         nouveau_notifier_free(&screen->sync);
 308         nouveau_grobj_free(&screen->eng3d);
 309         nvfx_screen_surface_takedown(pscreen);
 310         nouveau_bo_ref(NULL, &screen->fence);
 311
 312         nouveau_screen_fini(&screen->base);
 313
 314         FREE(pscreen);
 315 }
 316
 317 static void nv30_screen_init(struct nvfx_screen *screen)
 318 {
 319         struct nouveau_channel *chan = screen->base.channel;
 320         struct nouveau_grobj *eng3d = screen->eng3d;
 321         int i;
 322
 323         /* TODO: perhaps we should do some of this on nv40 too? */
 324         for (i=1; i<8; i++) {
 325                 BEGIN_RING(chan, eng3d, NV30_3D_VIEWPORT_CLIP_HORIZ(i), 1);
 326                 OUT_RING(chan, 0);
 327                 BEGIN_RING(chan, eng3d, NV30_3D_VIEWPORT_CLIP_VERT(i), 1);
 328                 OUT_RING(chan, 0);
 329         }
 330
 331         BEGIN_RING(chan, eng3d, 0x220, 1);
 332         OUT_RING(chan, 1);
 333
 334         BEGIN_RING(chan, eng3d, 0x03b0, 1);
 335         OUT_RING(chan, 0x00100000);
 336         BEGIN_RING(chan, eng3d, 0x1454, 1);
 337         OUT_RING(chan, 0);
 338         BEGIN_RING(chan, eng3d, 0x1d80, 1);
 339         OUT_RING(chan, 3);
 340         BEGIN_RING(chan, eng3d, 0x1450, 1);
 341         OUT_RING(chan, 0x00030004);
 342
 343         /* NEW */
 344         BEGIN_RING(chan, eng3d, 0x1e98, 1);
 345         OUT_RING(chan, 0);
 346         BEGIN_RING(chan, eng3d, 0x17e0, 3);
 347         OUT_RING(chan, fui(0.0));
 348         OUT_RING(chan, fui(0.0));
 349         OUT_RING(chan, fui(1.0));
 350         BEGIN_RING(chan, eng3d, 0x1f80, 16);
 351         for (i=0; i<16; i++) {
 352                 OUT_RING(chan, (i==8) ? 0x0000ffff : 0);
 353         }
 354
 355         BEGIN_RING(chan, eng3d, 0x120, 3);
 356         OUT_RING(chan, 0);
 357         OUT_RING(chan, 1);
 358         OUT_RING(chan, 2);
 359
 360         BEGIN_RING(chan, eng3d, 0x1d88, 1);
 361         OUT_RING(chan, 0x00001200);
 362
 363         BEGIN_RING(chan, eng3d, NV30_3D_RC_ENABLE, 1);
 364         OUT_RING(chan, 0);
 365
 366         BEGIN_RING(chan, eng3d, NV30_3D_DEPTH_RANGE_NEAR, 2);
 367         OUT_RING(chan, fui(0.0));
 368         OUT_RING(chan, fui(1.0));
 369
 370         BEGIN_RING(chan, eng3d, NV30_3D_MULTISAMPLE_CONTROL, 1);
 371         OUT_RING(chan, 0xffff0000);
 372
 373         /* enables use of vp rather than fixed-function somehow */
 374         BEGIN_RING(chan, eng3d, 0x1e94, 1);
 375         OUT_RING(chan, 0x13);
 376 }
 377
 378 static void nv40_screen_init(struct nvfx_screen *screen)
 379 {
 380         struct nouveau_channel *chan = screen->base.channel;
 381         struct nouveau_grobj *eng3d = screen->eng3d;
 382
 383         BEGIN_RING(chan, eng3d, NV40_3D_DMA_COLOR2, 2);
 384         OUT_RING(chan, screen->base.channel->vram->handle);
 385         OUT_RING(chan, screen->base.channel->vram->handle);
 386
 387         BEGIN_RING(chan, eng3d, 0x1450, 1);
 388         OUT_RING(chan, 0x00000004);
 389
 390         BEGIN_RING(chan, eng3d, 0x1ea4, 3);
 391         OUT_RING(chan, 0x00000010);
 392         OUT_RING(chan, 0x01000100);
 393         OUT_RING(chan, 0xff800006);
 394
 395         /* vtxprog output routing */
 396         BEGIN_RING(chan, eng3d, 0x1fc4, 1);
 397         OUT_RING(chan, 0x06144321);
 398         BEGIN_RING(chan, eng3d, 0x1fc8, 2);
 399         OUT_RING(chan, 0xedcba987);
 400         OUT_RING(chan, 0x0000006f);
 401         BEGIN_RING(chan, eng3d, 0x1fd0, 1);
 402         OUT_RING(chan, 0x00171615);
 403         BEGIN_RING(chan, eng3d, 0x1fd4, 1);
 404         OUT_RING(chan, 0x001b1a19);
 405
 406         BEGIN_RING(chan, eng3d, 0x1ef8, 1);
 407         OUT_RING(chan, 0x0020ffff);
 408         BEGIN_RING(chan, eng3d, 0x1d64, 1);
 409         OUT_RING(chan, 0x01d300d4);
 410         BEGIN_RING(chan, eng3d, 0x1e94, 1);
 411         OUT_RING(chan, 0x00000001);
 412
 413         BEGIN_RING(chan, eng3d, NV40_3D_MIPMAP_ROUNDING, 1);
 414         OUT_RING(chan, NV40_3D_MIPMAP_ROUNDING_MODE_DOWN);
 415 }
 416
 417 static unsigned
 418 nvfx_screen_get_vertex_buffer_flags(struct nvfx_screen* screen)
 419 {
 420         int vram_hack_default = 0;
 421         int vram_hack;
 422         // TODO: this is a bit of a guess; also add other cards that may need this hack.
 423         // It may also depend on the specific card or the AGP/PCIe chipset.
 424         if(screen->base.device->chipset == 0x47 /* G70 */
 425                 || screen->base.device->chipset == 0x49 /* G71 */
 426                 || screen->base.device->chipset == 0x46 /* G72 */
 427                 )
 428                 vram_hack_default = 1;
 429         vram_hack = debug_get_bool_option("NOUVEAU_VTXIDX_IN_VRAM", vram_hack_default);
 430
 431         return vram_hack ? NOUVEAU_BO_VRAM : NOUVEAU_BO_GART;
 432 }
 433
 434 static void nvfx_channel_flush_notify(struct nouveau_channel* chan)
 435 {
 436         struct nvfx_screen* screen = chan->user_private;
 437         struct nvfx_context* nvfx = screen->cur_ctx;
 438         if(nvfx)
 439                 nvfx->relocs_needed = NVFX_RELOCATE_ALL;
 440 }
 441
 442 struct pipe_screen *
 443 nvfx_screen_create(struct pipe_winsys *ws, struct nouveau_device *dev)
 444 {
 445         static const unsigned query_sizes[] = {(4096 - 4 * 32) / 32, 3 * 1024 / 32, 2 * 1024 / 32, 1024 / 32};
 446         struct nvfx_screen *screen = CALLOC_STRUCT(nvfx_screen);
 447         struct nouveau_channel *chan;
 448         struct pipe_screen *pscreen;
 449         unsigned eng3d_class = 0;
 450         int ret, i;
 451
 452         if (!screen)
 453                 return NULL;
 454
 455         pscreen = &screen->base.base;
 456
 457         ret = nouveau_screen_init(&screen->base, dev);
 458         if (ret) {
 459                 nvfx_screen_destroy(pscreen);
 460                 return NULL;
 461         }
 462         chan = screen->base.channel;
 463         screen->cur_ctx = NULL;
 464         chan->user_private = screen;
 465         chan->flush_notify = nvfx_channel_flush_notify;
 466
 467         pscreen->winsys = ws;
 468         pscreen->destroy = nvfx_screen_destroy;
 469         pscreen->get_param = nvfx_screen_get_param;
 470         pscreen->get_shader_param = nvfx_screen_get_shader_param;
 471         pscreen->get_paramf = nvfx_screen_get_paramf;
 472         pscreen->is_format_supported = nvfx_screen_is_format_supported;
 473         pscreen->context_create = nvfx_create;
 474
 475         ret = nouveau_bo_new(dev, NOUVEAU_BO_VRAM, 0, 4096, &screen->fence);
 476         if (ret) {
 477                 nvfx_screen_destroy(pscreen);
 478                 return NULL;
 479         }
 480
 481         switch (dev->chipset & 0xf0) {
 482         case 0x30:
 483                 if (NV30_3D_CHIPSET_3X_MASK & (1 << (dev->chipset & 0x0f)))
 484                         eng3d_class = NV30_3D;
 485                 else if (NV34_3D_CHIPSET_3X_MASK & (1 << (dev->chipset & 0x0f)))
 486                         eng3d_class = NV34_3D;
 487                 else if (NV35_3D_CHIPSET_3X_MASK & (1 << (dev->chipset & 0x0f)))
 488                         eng3d_class = NV35_3D;
 489                 break;
 490         case 0x40:
 491                 if (NV4X_GRCLASS4097_CHIPSETS & (1 << (dev->chipset & 0x0f)))
 492                         eng3d_class = NV40_3D;
 493                 else if (NV4X_GRCLASS4497_CHIPSETS & (1 << (dev->chipset & 0x0f)))
 494                         eng3d_class = NV44_3D;
 495                 screen->is_nv4x = ~0;
 496                 break;
 497         case 0x60:
 498                 if (NV6X_GRCLASS4497_CHIPSETS & (1 << (dev->chipset & 0x0f)))
 499                         eng3d_class = NV44_3D;
 500                 screen->is_nv4x = ~0;
 501                 break;
 502         }
 503
 504         if (!eng3d_class) {
 505                 NOUVEAU_ERR("Unknown nv3x/nv4x chipset: nv%02x\n", dev->chipset);
 506                 return NULL;
 507         }
 508
 509         screen->advertise_npot = !!screen->is_nv4x;
 510         screen->advertise_blend_equation_separate = !!screen->is_nv4x;
 511         screen->use_nv4x = screen->is_nv4x;
 512
 513         if(screen->is_nv4x) {
 514                 if(debug_get_bool_option("NVFX_SIMULATE_NV30", FALSE))
 515                         screen->use_nv4x = 0;
 516                 if(!debug_get_bool_option("NVFX_NPOT", TRUE))
 517                         screen->advertise_npot = 0;
 518                 if(!debug_get_bool_option("NVFX_BLEND_EQ_SEP", TRUE))
 519                         screen->advertise_blend_equation_separate = 0;
 520         }
 521
 522         screen->force_swtnl = debug_get_bool_option("NVFX_SWTNL", FALSE);
 523         screen->trace_draw = debug_get_bool_option("NVFX_TRACE_DRAW", FALSE);
 524
 525         screen->buffer_allocation_cost = debug_get_num_option("NVFX_BUFFER_ALLOCATION_COST", 16384);
 526         screen->inline_cost_per_hardware_cost = atof(debug_get_option("NVFX_INLINE_COST_PER_HARDWARE_COST", "1.0"));
 527         screen->static_reuse_threshold = atof(debug_get_option("NVFX_STATIC_REUSE_THRESHOLD", "2.0"));
 528
 529         /* We don't advertise these by default because filtering and blending doesn't work as
 530          * it should, due to several restrictions.
 531          * The only exception is fp16 on nv40.
 532          */
 533         screen->advertise_fp16 = debug_get_bool_option("NVFX_FP16", !!screen->use_nv4x);
 534         screen->advertise_fp32 = debug_get_bool_option("NVFX_FP32", 0);
 535
 536         screen->vertex_buffer_reloc_flags = nvfx_screen_get_vertex_buffer_flags(screen);
 537
 538         /* surely both nv3x and nv44 support index buffers too: find out how and test that */
 539         if(eng3d_class == NV40_3D)
 540                 screen->index_buffer_reloc_flags = screen->vertex_buffer_reloc_flags;
 541
 542         if(!screen->force_swtnl && screen->vertex_buffer_reloc_flags == screen->index_buffer_reloc_flags)
 543                 screen->base.vertex_buffer_flags = screen->base.index_buffer_flags = screen->vertex_buffer_reloc_flags;
 544
 545         nvfx_screen_init_resource_functions(pscreen);
 546
 547         ret = nouveau_grobj_alloc(chan, 0xbeef3097, eng3d_class, &screen->eng3d);
 548         if (ret) {
 549                 NOUVEAU_ERR("Error creating 3D object: %d\n", ret);
 550                 return FALSE;
 551         }
 552
 553         /* 2D engine setup */
 554         nvfx_screen_surface_init(pscreen);
 555
 556         /* Notifier for sync purposes */
 557         ret = nouveau_notifier_alloc(chan, 0xbeef0301, 1, &screen->sync);
 558         if (ret) {
 559                 NOUVEAU_ERR("Error creating notifier object: %d\n", ret);
 560                 nvfx_screen_destroy(pscreen);
 561                 return NULL;
 562         }
 563
 564         /* Query objects */
 565         for(i = 0; i < sizeof(query_sizes) / sizeof(query_sizes[0]); ++i)
 566         {
 567                 ret = nouveau_notifier_alloc(chan, 0xbeef0302, query_sizes[i], &screen->query);
 568                 if(!ret)
 569                         break;
 570         }
 571
 572         if (ret) {
 573                 NOUVEAU_ERR("Error initialising query objects: %d\n", ret);
 574                 nvfx_screen_destroy(pscreen);
 575                 return NULL;
 576         }
 577
 578         ret = nouveau_resource_init(&screen->query_heap, 0, query_sizes[i]);
 579         if (ret) {
 580                 NOUVEAU_ERR("Error initialising query object heap: %d\n", ret);
 581                 nvfx_screen_destroy(pscreen);
 582                 return NULL;
 583         }
 584
 585         LIST_INITHEAD(&screen->query_list);
 586
 587         /* Vtxprog resources */
 588         if (nouveau_resource_init(&screen->vp_exec_heap, 0, screen->use_nv4x ? 512 : 256) ||
 589             nouveau_resource_init(&screen->vp_data_heap, 0, screen->use_nv4x ? 468 : 256)) {
 590                 nvfx_screen_destroy(pscreen);
 591                 return NULL;
 592         }
 593
 594         BIND_RING(chan, screen->eng3d, 7);
 595
 596         /* Static eng3d initialisation */
 597         /* note that we just started using the channel, so we must have space in the pushbuffer */
 598         BEGIN_RING(chan, screen->eng3d, NV30_3D_DMA_NOTIFY, 1);
 599         OUT_RING(chan, screen->sync->handle);
 600         BEGIN_RING(chan, screen->eng3d, NV30_3D_DMA_TEXTURE0, 2);
 601         OUT_RING(chan, chan->vram->handle);
 602         OUT_RING(chan, chan->gart->handle);
 603         BEGIN_RING(chan, screen->eng3d, NV30_3D_DMA_COLOR1, 1);
 604         OUT_RING(chan, chan->vram->handle);
 605         BEGIN_RING(chan, screen->eng3d, NV30_3D_DMA_COLOR0, 2);
 606         OUT_RING(chan, chan->vram->handle);
 607         OUT_RING(chan, chan->vram->handle);
 608         BEGIN_RING(chan, screen->eng3d, NV30_3D_DMA_VTXBUF0, 2);
 609         OUT_RING(chan, chan->vram->handle);
 610         OUT_RING(chan, chan->gart->handle);
 611
 612         BEGIN_RING(chan, screen->eng3d, NV30_3D_DMA_FENCE, 2);
 613         OUT_RING(chan, 0);
 614         OUT_RING(chan, screen->query->handle);
 615
 616         BEGIN_RING(chan, screen->eng3d, NV30_3D_DMA_UNK1AC, 2);
 617         OUT_RING(chan, chan->vram->handle);
 618         OUT_RING(chan, chan->vram->handle);
 619
 620         if(!screen->is_nv4x)
 621                 nv30_screen_init(screen);
 622         else
 623                 nv40_screen_init(screen);
 624
 625         return pscreen;
 626 }