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scripts: add crosstools packages for i386 and armhf
[AROS.git] / rom / hidds / pci / pcideviceclass.c
blobdffad6a6770f364bd803a5b45dc35be5368cb549
1 /*
2 Copyright © 2004-2016, The AROS Development Team. All rights reserved.
3 $Id$
4
5 Desc: PCI device class
6 Lang: English
7 */
8
9 #include <exec/types.h>
10 #include <hidd/pci.h>
11 #include <oop/oop.h>
12 #include <utility/tagitem.h>
13 #include <proto/exec.h>
14 #include <proto/utility.h>
15 #include <proto/oop.h>
16
17 #include "pci.h"
18 #include "pcie.h"
19 #include "pciutil.h"
20
21 #include <aros/debug.h>
22
23 /*****************************************************************************************
24
25 NAME
26 aoHidd_PCIDevice_Owner
27
28 SYNOPSIS
29 [..G], APTR
30
31 LOCATION
32 CLID_Hidd_PCIDevice
33
34 FUNCTION
35 Returns name of current device's owner or NULL if the device is
36 not owned by anyone.
37
38 NOTES
39 This attribute is provided for diagnostics utilities like PCITool.
40 There is no need to check current owner before attempting to own
41 the device. moHidd_PCIDevice_Obtain method performs this check
42 and owns the device atomically.
43
44 EXAMPLE
45
46 BUGS
47
48 SEE ALSO
49
50 INTERNALS
51
52 *****************************************************************************************/
53 static IPTR hasExtendedConfig(OOP_Class *cl, OOP_Object *o)
54 {
55 tDeviceData *dev = (tDeviceData *)OOP_INST_DATA(cl,o);
56
57 return dev->extendedconfig;
58 }
59
60 static void setLong(OOP_Class *cl, OOP_Object *o, ULONG reg, ULONG value)
61 {
62 tDeviceData *dev = (tDeviceData *)OOP_INST_DATA(cl,o);
63
64 HIDD_PCIDriver_WriteConfigLong(dev->driver, (OOP_Object *)dev, dev->bus, dev->dev, dev->sub, reg, value);
65 }
66
67 static void setWord(OOP_Class *cl, OOP_Object *o, ULONG reg, UWORD value)
68 {
69 tDeviceData *dev = (tDeviceData *)OOP_INST_DATA(cl,o);
70
71 HIDD_PCIDriver_WriteConfigWord(dev->driver, (OOP_Object *)dev, dev->bus, dev->dev, dev->sub, reg, value);
72 }
73
74 static void setByte(OOP_Class *cl, OOP_Object *o, ULONG reg, UBYTE value)
75 {
76 tDeviceData *dev = (tDeviceData *)OOP_INST_DATA(cl,o);
77
78 HIDD_PCIDriver_WriteConfigByte(dev->driver, (OOP_Object *)dev, dev->bus, dev->dev, dev->sub, reg, value);
79 }
80
81 static ULONG getLong(OOP_Class *cl, OOP_Object *o, ULONG reg)
82 {
83 tDeviceData *dev = (tDeviceData *)OOP_INST_DATA(cl,o);
84
85 return HIDD_PCIDriver_ReadConfigLong(dev->driver, (OOP_Object *)dev, dev->bus, dev->dev, dev->sub, reg);
86 }
87
88 static UWORD getWord(OOP_Class *cl, OOP_Object *o, ULONG reg)
89 {
90 tDeviceData *dev = (tDeviceData *)OOP_INST_DATA(cl,o);
91
92 return HIDD_PCIDriver_ReadConfigWord(dev->driver, (OOP_Object *)dev, dev->bus, dev->dev, dev->sub, reg);
93 }
94
95 static UBYTE getByte(OOP_Class *cl, OOP_Object *o, ULONG reg)
96 {
97 tDeviceData *dev = (tDeviceData *)OOP_INST_DATA(cl,o);
98
99 return HIDD_PCIDriver_ReadConfigByte(dev->driver, (OOP_Object *)dev, dev->bus, dev->dev, dev->sub, reg);
100 }
101
102 /* Returns offset of capability area in config area or 0 if capability is not present */
103 static UBYTE findCapabilityOffset(OOP_Class * cl, OOP_Object *o, UBYTE capability)
104 {
105 UWORD where = 0x34; /* First cap list entry */
106 UBYTE capid = 0;
107
108 /* Check if capabilities present at all */
109 if ((getWord(cl, o, PCICS_STATUS) & PCISTF_CAPABILITIES) != PCISTF_CAPABILITIES)
110 return 0;
111
112 /* Iterate over capabilities */
113 while(where < 0xff)
114 {
115 where = getByte(cl, o, where);
116
117 if (where < 0x40)
118 break;
119
120 where &= ~3;
121 capid = getByte(cl, o, where);
122
123 if (capid == 0xff)
124 break;
125
126 if (capid == capability) return (UBYTE)where;
127
128 where += 1; /* next cap */
129 }
130
131 return 0;
132 }
133
134 /* Returns offset of PCI Express extended capability or 0 if capability is not present */
135 static UWORD findExpressExtendedCapabilityOffset(OOP_Class * cl, OOP_Object *o, UWORD capability)
136 {
137 UWORD where = 0x100; /* First PCI Express extended cap list entry */
138 ULONG caphdr;
139
140 while((where > 0xff) && (where < 0xfff))
141 {
142 caphdr = getLong(cl, o, where);
143 if( (caphdr == -1) || (caphdr == 0)) return 0;
144
145 if ((caphdr & 0xffff) == capability) return (UWORD)where;
146
147 where = (caphdr>>20)&~3;
148 }
149
150 return 0;
151 }
152
153 BOOL PCIDev__Hidd_PCIDevice__HasExtendedConfig(OOP_Class *cl, OOP_Object *o, struct pHidd_PCIDevice_HasExtendedConfig *msg)
154 {
155 return hasExtendedConfig(cl, o);
156 }
157
158 UBYTE PCIDev__Hidd_PCIDevice__ReadConfigByte(OOP_Class *cl, OOP_Object *o, struct pHidd_PCIDevice_ReadConfigByte *msg)
159 {
160 return getByte(cl, o, msg->reg);
161 }
162
163 UWORD PCIDev__Hidd_PCIDevice__ReadConfigWord(OOP_Class *cl, OOP_Object *o, struct pHidd_PCIDevice_ReadConfigWord *msg)
164 {
165 return getWord(cl, o, msg->reg);
166 }
167
168 ULONG PCIDev__Hidd_PCIDevice__ReadConfigLong(OOP_Class *cl, OOP_Object *o, struct pHidd_PCIDevice_ReadConfigLong *msg)
169 {
170 return getLong(cl, o, msg->reg);
171 }
172
173 VOID PCIDev__Hidd_PCIDevice__WriteConfigByte(OOP_Class *cl, OOP_Object *o, struct pHidd_PCIDevice_WriteConfigByte *msg)
174 {
175 setByte(cl, o, msg->reg, msg->val);
176 }
177
178 VOID PCIDev__Hidd_PCIDevice__WriteConfigWord(OOP_Class *cl, OOP_Object *o, struct pHidd_PCIDevice_WriteConfigWord *msg)
179 {
180 setWord(cl, o, msg->reg, msg->val);
181 }
182
183 VOID PCIDev__Hidd_PCIDevice__WriteConfigLong(OOP_Class *cl, OOP_Object *o, struct pHidd_PCIDevice_WriteConfigLong *msg)
184 {
185 setLong(cl, o, msg->reg, msg->val);
186 }
187
188 /*****************************************************************************************
189
190 NAME
191 moHidd_PCIDevice_AddInterrupt
192
193 SYNOPSIS
194 OOP_Object *OOP_DoMethod(OOP_Object *obj, struct pHidd_PCIDevice_AddInterrupt *Msg);
195
196 OOP_Object *HIDD_PCIDriver_AddInterrupt(OOP_Object *obj, OOP_Object *device,
197 struct Interrupt *interrupt);
198
199 LOCATION
200 CLID_Hidd_PCIDevice
201
202 FUNCTION
203 Add interrupt handler for the device.
204
205 INPUTS
206 obj - Pointer to device object.
207 interrupt - Interrupt structure to add.
208
209 RESULT
210 TRUE it successful or FALSE on failure.
211
212 NOTES
213
214 EXAMPLE
215
216 BUGS
217
218 SEE ALSO
219 moHidd_PCIDevice_RemoveInterrupt
220
221 INTERNALS
222
223 *****************************************************************************************/
224
225 BOOL PCIDev__Hidd_PCIDevice__AddInterrupt(OOP_Class *cl, OOP_Object *o,
226 struct pHidd_PCIDevice_AddInterrupt *msg)
227 {
228 tDeviceData *dev = OOP_INST_DATA(cl, o);
229
230 return HIDD_PCIDriver_AddInterrupt(dev->driver, o, msg->interrupt);
231 }
232
233 /*****************************************************************************************
234
235 NAME
236 moHidd_PCIDevice_RemoveInterrupt
237
238 SYNOPSIS
239 OOP_Object *OOP_DoMethod(OOP_Object *obj, struct pHidd_PCIDevice_RemoveInterrupt *Msg);
240
241 OOP_Object *HIDD_PCIDevice_RemoveInterrupt(OOP_Object *obj, OOP_Object *device,
242 struct Interrupt *interrupt);
243
244 LOCATION
245 CLID_Hidd_PCIDevice
246
247 FUNCTION
248 Remove interrupt handler from the device.
249
250 INPUTS
251 obj - Pointer to the device object.
252 interrupt - Interrupt structure to remove.
253
254 RESULT
255 None.
256
257 NOTES
258
259 EXAMPLE
260
261 BUGS
262
263 SEE ALSO
264 moHidd_PCIDevice_AddInterrupt
265
266 INTERNALS
267
268 *****************************************************************************************/
269
270 VOID PCIDev__Hidd_PCIDevice__RemoveInterrupt(OOP_Class *cl, OOP_Object *o,
271 struct pHidd_PCIDevice_RemoveInterrupt *msg)
272 {
273 tDeviceData *dev = OOP_INST_DATA(cl, o);
274
275 return HIDD_PCIDriver_RemoveInterrupt(dev->driver, o, msg->interrupt);
276 }
277
278 /*****************************************************************************************
279
280 NAME
281 moHidd_PCIDevice_Obtain
282
283 SYNOPSIS
284 OOP_Object *OOP_DoMethod(OOP_Object *obj, struct pHidd_PCIDevice_Obtain *Msg);
285
286 OOP_Object *HIDD_PCIDevice_Obtain(OOP_Object *obj, CONST_STRPTR owner);
287
288 LOCATION
289 CLID_Hidd_PCIDevice
290
291 FUNCTION
292 Lock the device for exclusive use.
293
294 INPUTS
295 obj - Pointer to the device object.
296 owner - A string identifying the owner.
297
298 RESULT
299 NULL on success or string identifying current owner.
300
301 NOTES
302
303 EXAMPLE
304
305 BUGS
306
307 SEE ALSO
308 moHidd_PCIDevice_Release
309
310 INTERNALS
311
312 *****************************************************************************************/
313
314 CONST_STRPTR PCIDev__Hidd_PCIDevice__Obtain(OOP_Class *cl, OOP_Object *o,
315 struct pHidd_PCIDevice_Obtain *msg)
316 {
317 tDeviceData *dev = OOP_INST_DATA(cl, o);
318 CONST_STRPTR current = NULL;
319
320 /*
321 * FIXME: Actually this is just atomic compare and swap.
322 * I believe it should be impemented in assembler.
323 * Ouch, on Amiga such operations are unsafe, at least
324 * in CHIP memory. Too bad...
325 */
326 ObtainSemaphore(&dev->ownerLock);
327
328 /* While we are using semaphore, owner name is embedded in its node */
329 if (dev->ownerLock.ss_Link.ln_Name)
330 current = dev->ownerLock.ss_Link.ln_Name;
331 else
332 dev->ownerLock.ss_Link.ln_Name = (STRPTR)msg->owner;
333
334 ReleaseSemaphore(&dev->ownerLock);
335
336 return current;
337 }
338
339 /*****************************************************************************************
340
341 NAME
342 moHidd_PCIDevice_Release
343
344 SYNOPSIS
345 OOP_Object *OOP_DoMethod(OOP_Object *obj, struct pHidd_PCIDevice_Release *Msg);
346
347 OOP_Object *HIDD_PCIDevice_Release(OOP_Object *obj);
348
349 LOCATION
350 CLID_Hidd_PCIDevice
351
352 FUNCTION
353 Release ownership of the device.
354
355 INPUTS
356 obj - Pointer to the device object.
357
358 RESULT
359 None.
360
361 NOTES
362 You should call this function only on devices owned by you. Doing
363 this on someone else's devices will not do any good things.
364
365 EXAMPLE
366
367 BUGS
368
369 SEE ALSO
370 moHidd_PCIDevice_Obtain
371
372 INTERNALS
373
374 *****************************************************************************************/
375
376 VOID PCIDev__Hidd_PCIDevice__Release(OOP_Class *cl, OOP_Object *o,
377 struct pHidd_PCIDevice_Release *msg)
378 {
379 tDeviceData *dev = OOP_INST_DATA(cl, o);
380
381 dev->ownerLock.ss_Link.ln_Name = NULL;
382 }
383
384 /*
385 PCIDevice::New method is invoked by base pci class. It passes to the device
386 class information about the driver this class should use and location of
387 created device on the PCI bus handled by given driver.
388 */
389 OOP_Object *PCIDev__Root__New(OOP_Class *cl, OOP_Object *o, struct pRoot_New *msg)
390 {
391 int i;
392
393 o = (OOP_Object *)OOP_DoSuperMethod(cl, o, (OOP_Msg) msg);
394 if (o)
395 {
396 struct TagItem *tag, *tags;
397 tDeviceData *dev = (tDeviceData *)OOP_INST_DATA(cl, o);
398 OOP_Object *driver = NULL;
399
400 InitSemaphore(&dev->ownerLock);
401
402 tags=(struct TagItem *)msg->attrList;
403
404 /*
405 Get all information passed by pci class calling OOP_NewObject()
406 */
407 while((tag = NextTagItem(&tags)))
408 {
409 ULONG idx;
410
411 if (IS_PCIDEV_ATTR(tag->ti_Tag, idx))
412 {
413 switch(idx)
414 {
415 case aoHidd_PCIDevice_Driver:
416 dev->driver = (OOP_Object*)tag->ti_Data;
417 driver = dev->driver;
418 break;
419
420 case aoHidd_PCIDevice_Bus:
421 dev->bus = tag->ti_Data;
422 break;
423
424 case aoHidd_PCIDevice_Dev:
425 dev->dev = tag->ti_Data;
426 break;
427
428 case aoHidd_PCIDevice_Sub:
429 dev->sub = tag->ti_Data;
430 break;
431
432 case aoHidd_PCIDevice_ExtendedConfig:
433 dev->extendedconfig = tag->ti_Data;
434 break;
435 }
436 }
437 }
438
439 /*
440 If driver is passed (*HAS TO* be passed) acquire some unchangeable
441 information regarding given device
442 */
443 if (driver)
444 {
445 UBYTE ht;
446
447 /*
448 Get the header type in order to determine whether it is a
449 device or bridge
450 */
451 ht = getByte(cl, o, PCICS_HEADERTYPE) & PCIHT_MASK;
452 dev->isBridge = 0;
453 if (ht == PCIHT_BRIDGE)
454 {
455 dev->isBridge = 1;
456 dev->subbus = getByte(cl, o, PCIBR_SUBBUS);
457 }
458
459 /* Get all constant ID's */
460 dev->VendorID = getWord(cl, o, PCICS_VENDOR);
461 dev->ProductID = getWord(cl, o, PCICS_PRODUCT);
462
463 dev->RevisionID = getByte(cl, o, PCICS_REVISION);
464 dev->Interface = getByte(cl, o, PCICS_PROGIF);
465 dev->SubClass = getByte(cl, o, PCICS_SUBCLASS);
466 dev->Class = getByte(cl, o, PCICS_CLASS);
467
468 dev->SubsysVID = getWord(cl, o, PCICS_SUBVENDOR);
469 dev->SubsystemID = getWord(cl, o, PCICS_SUBSYSTEM);
470
471 dev->IRQLine = getByte(cl, o, PCICS_INT_PIN);
472
473 if (dev->IRQLine)
474 {
475 dev->INTLine = getByte(cl, o, PCICS_INT_LINE);
476 }
477 else dev->INTLine = 0;
478
479 dev->HeaderType = ht;
480
481 getPCIClassDesc(dev->Class, dev->SubClass, dev->Interface,
482 &dev->strClass, &dev->strSubClass, &dev->strInterface);
483
484 /* Satisfy BUG watchers ;) */
485 D(bug("[PCIDevice] %02x.%02x.%x = %04.4lx:%04.4lx (%s %s %s)\n",
486 dev->bus, dev->dev, dev->sub,
487 dev->VendorID, dev->ProductID,
488 dev->strClass, dev->strSubClass, dev->strInterface));
489 D(bug("[PCIDevice] > IRQ %u INT %u\n", dev->IRQLine, dev->INTLine));
490
491 // print out a warning to the user in case the interrupt line is not assigned by BIOS
492 if (dev->INTLine == 255 && !dev->isBridge)
493 bug("[PCIDevice] WARNING: Interrupt line is not assigned! Device may freeze or malfunction at use!\n");
494
495 /* Read two first base addresses */
496 for (i = 0; i < 2; i++)
497 {
498 dev->BaseReg[i].addr = getLong(cl, o, PCICS_BAR0 + (i << 2));
499 dev->BaseReg[i].size = sizePCIBaseReg(driver, PSD(cl), dev, dev->bus,
500 dev->dev, dev->sub, i);
501 }
502
503 /* Address and size of ROM */
504 dev->RomBase = getLong(cl, o, PCICS_EXPROM_BASE);
505 dev->RomSize = sizePCIBaseReg(driver, PSD(cl), dev, dev->bus,
506 dev->dev, dev->sub, (PCICS_EXPROM_BASE - PCICS_BAR0) >> 2);
507
508 /*
509 Bridges specify only first two base addresses. If not bridge,
510 check the rest now
511 */
512 if (! dev->isBridge)
513 {
514 for (i = 2; i < 6; i++)
515 {
516 dev->BaseReg[i].addr = getLong(cl, o, PCICS_BAR0 + (i << 2));
517 dev->BaseReg[i].size = sizePCIBaseReg(driver, PSD(cl), dev, dev->bus,
518 dev->dev, dev->sub, i);
519 }
520 }
521 }
522 }
523
524 return o;
525 }
526
527 /*
528 PCIDevice::Get method splitted into few parts in order to make switch'es shorter.
529 */
530
531 static void dispatch_generic(OOP_Class *cl, OOP_Object *o, struct pRoot_Get *msg)
532 {
533 ULONG idx;
534 tDeviceData *dev = (tDeviceData *)OOP_INST_DATA(cl,o);
535
536 idx = msg->attrID - HiddPCIDeviceAttrBase;
537
538 switch(idx)
539 {
540 case aoHidd_PCIDevice_Driver:
541 *msg->storage = (IPTR)dev->driver;
542 break;
543
544 case aoHidd_PCIDevice_Bus:
545 *msg->storage = (IPTR)dev->bus;
546 break;
547
548 case aoHidd_PCIDevice_Dev:
549 *msg->storage = (IPTR)dev->dev;
550 break;
551
552 case aoHidd_PCIDevice_Sub:
553 *msg->storage = (IPTR)dev->sub;
554 break;
555
556 case aoHidd_PCIDevice_VendorID:
557 *msg->storage = (IPTR)dev->VendorID;
558 break;
559
560 case aoHidd_PCIDevice_ProductID:
561 *msg->storage = (IPTR)dev->ProductID;
562 break;
563
564 case aoHidd_PCIDevice_RevisionID:
565 *msg->storage = (IPTR)dev->RevisionID;
566 break;
567
568 case aoHidd_PCIDevice_Interface:
569 *msg->storage = (IPTR)dev->Interface;
570 break;
571
572 case aoHidd_PCIDevice_Class:
573 *msg->storage = (IPTR)dev->Class;
574 break;
575
576 case aoHidd_PCIDevice_SubClass:
577 *msg->storage = (IPTR)dev->SubClass;
578 break;
579
580 case aoHidd_PCIDevice_SubsystemVendorID:
581 *msg->storage = (IPTR)dev->SubsysVID;
582 break;
583
584 case aoHidd_PCIDevice_SubsystemID:
585 *msg->storage = (IPTR)dev->SubsystemID;
586 break;
587
588 case aoHidd_PCIDevice_IRQLine:
589 *msg->storage = (IPTR)dev->IRQLine;
590 break;
591
592 case aoHidd_PCIDevice_RomBase:
593 *msg->storage = (IPTR)dev->RomBase;
594 break;
595
596 case aoHidd_PCIDevice_RomSize:
597 *msg->storage = (IPTR)dev->RomSize;
598 break;
599
600 case aoHidd_PCIDevice_ExtendedConfig:
601 *msg->storage = (IPTR)dev->extendedconfig;
602 break;
603
604 case aoHidd_PCIDevice_ConfigSize:
605 if(dev->extendedconfig) {
606 *msg->storage = 4096;
607 } else {
608 *msg->storage = 256;
609 }
610 break;
611
612 }
613 }
614
615 static void dispatch_base(OOP_Class *cl, OOP_Object *o, struct pRoot_Get *msg)
616 {
617 ULONG idx,id;
618 tDeviceData *dev = (tDeviceData *)OOP_INST_DATA(cl,o);
619
620 idx = msg->attrID - HiddPCIDeviceAttrBase;
621 id = 0;
622
623 switch(idx)
624 {
625 case aoHidd_PCIDevice_Base0: id = 0; break;
626 case aoHidd_PCIDevice_Base1: id = 1; break;
627 case aoHidd_PCIDevice_Base2: id = 2; break;
628 case aoHidd_PCIDevice_Base3: id = 3; break;
629 case aoHidd_PCIDevice_Base4: id = 4; break;
630 case aoHidd_PCIDevice_Base5: id = 5; break;
631 }
632
633 /* Do not allow reading of more than two base addresses in case of PCI-PCI bridges */
634 if (dev->isBridge && id >= 2) { *msg->storage = 0; return; }
635
636 *msg->storage = (IPTR)dev->BaseReg[id].addr;
637 if ((dev->BaseReg[id].addr & PCIBAR_MASK_TYPE)==PCIBAR_TYPE_IO)
638 {
639 IPTR IOBase = 0;
640 *msg->storage &= PCIBAR_MASK_IO;
641 OOP_GetAttr(dev->driver, aHidd_PCIDriver_IOBase, &IOBase);
642 *msg->storage += IOBase;
643 }
644 else
645 {
646 *msg->storage &= PCIBAR_MASK_MEM;
647 }
648 }
649
650 static void dispatch_type(OOP_Class *cl, OOP_Object *o, struct pRoot_Get *msg)
651 {
652 ULONG idx,id;
653 tDeviceData *dev = (tDeviceData *)OOP_INST_DATA(cl,o);
654
655 idx = msg->attrID - HiddPCIDeviceAttrBase;
656 id = 0;
657
658 switch(idx)
659 {
660 case aoHidd_PCIDevice_Type0: id = 0; break;
661 case aoHidd_PCIDevice_Type1: id = 1; break;
662 case aoHidd_PCIDevice_Type2: id = 2; break;
663 case aoHidd_PCIDevice_Type3: id = 3; break;
664 case aoHidd_PCIDevice_Type4: id = 4; break;
665 case aoHidd_PCIDevice_Type5: id = 5; break;
666 }
667
668 /* Do not allow reading of more than two base addresses in case of PCI-PCI bridges */
669 if (dev->isBridge && id >= 2) { *msg->storage = 0; return; }
670
671 *msg->storage = (IPTR)dev->BaseReg[id].addr;
672 if ((dev->BaseReg[id].addr & PCIBAR_MASK_TYPE)==PCIBAR_TYPE_IO)
673 {
674 *msg->storage &= ~PCIBAR_MASK_IO;
675 }
676 else
677 {
678 *msg->storage &= ~PCIBAR_MASK_MEM;
679 }
680 }
681
682 static void dispatch_size(OOP_Class *cl, OOP_Object *o, struct pRoot_Get *msg)
683 {
684 ULONG idx,id;
685 tDeviceData *dev = (tDeviceData *)OOP_INST_DATA(cl,o);
686
687 idx = msg->attrID - HiddPCIDeviceAttrBase;
688 id = 0;
689
690 switch(idx)
691 {
692 case aoHidd_PCIDevice_Size0: id = 0; break;
693 case aoHidd_PCIDevice_Size1: id = 1; break;
694 case aoHidd_PCIDevice_Size2: id = 2; break;
695 case aoHidd_PCIDevice_Size3: id = 3; break;
696 case aoHidd_PCIDevice_Size4: id = 4; break;
697 case aoHidd_PCIDevice_Size5: id = 5; break;
698 }
699
700 /* Do not allow reading of more than two base addresses in case of PCI-PCI bridges */
701 if (dev->isBridge && id >= 2) { *msg->storage = 0; return;}
702
703 *msg->storage = (IPTR)dev->BaseReg[id].size;
704 }
705
706 static void dispatch_pci2pcibridge(OOP_Class *cl, OOP_Object *o, struct pRoot_Get *msg)
707 {
708 ULONG idx;
709 tDeviceData *dev = (tDeviceData *)OOP_INST_DATA(cl,o);
710
711 UWORD control;
712
713 /* If device is not a PCI-PCI bridge, do nothing */
714 if (!dev->isBridge) { *msg->storage = 0; return; }
715
716 control = getWord(cl, o, PCIBR_CONTROL);
717
718 idx = msg->attrID - HiddPCIDeviceAttrBase;
719
720 switch(idx)
721 {
722 case aoHidd_PCIDevice_isBridge:
723 *msg->storage = dev->isBridge;
724 break;
725
726 case aoHidd_PCIDevice_SubBus:
727 *msg->storage = dev->subbus;
728 break;
729
730 case aoHidd_PCIDevice_MemoryBase:
731 *msg->storage = getWord(cl, o, PCIBR_MEMBASE) << 16;
732 break;
733
734 case aoHidd_PCIDevice_MemoryLimit:
735 *msg->storage = getWord(cl, o, PCIBR_MEMLIMIT) << 16;
736 break;
737
738 case aoHidd_PCIDevice_PrefetchableBase:
739 *msg->storage = getWord(cl, o, PCIBR_PREFETCHBASE) << 16;
740 break;
741
742 case aoHidd_PCIDevice_PrefetchableLimit:
743 *msg->storage = getWord(cl, o, PCIBR_PREFETCHLIMIT) << 16;
744 break;
745
746 case aoHidd_PCIDevice_IOBase:
747 *msg->storage = getByte(cl, o, PCIBR_IOBASE) << 8;
748 break;
749
750 case aoHidd_PCIDevice_IOLimit:
751 *msg->storage = getByte(cl, o, PCIBR_IOLIMIT) << 8;
752 break;
753
754 case aoHidd_PCIDevice_ISAEnable:
755 *msg->storage = (control & PCICTRLF_ISAENABLE) == PCICTRLF_ISAENABLE;
756 break;
757
758 case aoHidd_PCIDevice_VGAEnable:
759 *msg->storage = (control & PCICTRLF_VGAENABLE) == PCICTRLF_VGAENABLE;
760 break;
761 }
762 }
763
764 static void dispatch_capability(OOP_Class *cl, OOP_Object *o, struct pRoot_Get *msg)
765 {
766 ULONG idx;
767 UBYTE capability = 0;
768 //tDeviceData *dev = (tDeviceData *)OOP_INST_DATA(cl,o);
769
770 idx = msg->attrID - HiddPCIDeviceAttrBase;
771
772 switch(idx)
773 {
774 case aoHidd_PCIDevice_CapabilityPowerManagement: capability = PCICAP_POWER_MANAGEMENT;break;
775 case aoHidd_PCIDevice_CapabilityAGP: capability = PCICAP_AGP;break;
776 case aoHidd_PCIDevice_CapabilityVitalProductData: capability = PCICAP_VITAL_PRODUCT_DATA;break;
777 case aoHidd_PCIDevice_CapabilitySlotID: capability = PCICAP_SLOT_ID;break;
778 case aoHidd_PCIDevice_CapabilityMSI: capability = PCICAP_MSI;break;
779 case aoHidd_PCIDevice_CapabilityCPCIHotSwap: capability = PCICAP_CPCI_HOT_SWAP;break;
780 case aoHidd_PCIDevice_CapabilityPCIX: capability = PCICAP_PCIX;break;
781 case aoHidd_PCIDevice_CapabilityHyperTransport: capability = PCICAP_HYPER_TRANSPORT;break;
782 case aoHidd_PCIDevice_CapabilityVendorSpecific: capability = PCICAP_VENDOR_SPECIFIC;break;
783 case aoHidd_PCIDevice_CapabilityDebugPort: capability = PCICAP_DEBUG_PORT;break;
784 case aoHidd_PCIDevice_CapabilityCPCICRC: capability = PCICAP_CPCI_CR;break;
785 case aoHidd_PCIDevice_CapabilityHotPlugController: capability = PCICAP_HOT_PLUG_CONTROLLER;break;
786 case aoHidd_PCIDevice_CapabilitySSVPID: capability = PCICAP_SSVPID;break;
787 case aoHidd_PCIDevice_CapabilityAGP3: capability = PCICAP_AGP3;break;
788 case aoHidd_PCIDevice_CapabilityPCIE: capability = PCICAP_PCIE;break;
789 case aoHidd_PCIDevice_CapabilityMSIX: capability = PCICAP_MSIX;break;
790 case aoHidd_PCIDevice_CapabilityAdvancedFeatures: capability = PCICAP_ADVANCED_FEATURES;break;
791 }
792
793 *msg->storage = findCapabilityOffset(cl, o, capability);
794 }
795
796 static void dispatch_extendedcapability(OOP_Class *cl, OOP_Object *o, struct pRoot_Get *msg)
797 {
798 ULONG idx;
799 UWORD capability = 0;
800
801 if(!hasExtendedConfig(cl, o))
802 {
803 D(bug("[PCIDevice] HasExtendedConfig = NULL\n"));
804 *msg->storage = 0;
805 return;
806 }
807
808 D(bug("[PCIDevice] HasExtendedConfig != NULL!\n"));
809
810 idx = msg->attrID - HiddPCIDeviceAttrBase;
811
812 switch(idx)
813 {
814 case aoHidd_PCIDevice_ExtendedCapabilityAER: capability = PCIEECAP_AER;break;
815 case aoHidd_PCIDevice_ExtendedCapabilityVC: capability = PCIEECAP_VC ;break;
816 case aoHidd_PCIDevice_ExtendedCapabilitySerialNumber: capability = PCIEECAP_SER;break;
817 case aoHidd_PCIDevice_ExtendedCapabilityPowerBudgeting: capability = PCIEECAP_PWR_BUDGET;break;
818 }
819
820 *msg->storage = findExpressExtendedCapabilityOffset(cl, o, capability);
821
822 return;
823 }
824
825 typedef void (*dispatcher_t)(OOP_Class *, OOP_Object *, struct pRoot_Get *);
826
827 static const dispatcher_t Dispatcher[num_Hidd_PCIDevice_Attrs] =
828 {
829 [aoHidd_PCIDevice_Driver] = dispatch_generic,
830 [aoHidd_PCIDevice_Bus] = dispatch_generic,
831 [aoHidd_PCIDevice_Dev] = dispatch_generic,
832 [aoHidd_PCIDevice_Sub] = dispatch_generic,
833 [aoHidd_PCIDevice_VendorID] = dispatch_generic,
834 [aoHidd_PCIDevice_ProductID] = dispatch_generic,
835 [aoHidd_PCIDevice_RevisionID] = dispatch_generic,
836 [aoHidd_PCIDevice_Interface] = dispatch_generic,
837 [aoHidd_PCIDevice_Class] = dispatch_generic,
838 [aoHidd_PCIDevice_SubClass] = dispatch_generic,
839 [aoHidd_PCIDevice_SubsystemVendorID] = dispatch_generic,
840 [aoHidd_PCIDevice_SubsystemID] = dispatch_generic,
841 [aoHidd_PCIDevice_IRQLine] = dispatch_generic,
842 [aoHidd_PCIDevice_RomBase] = dispatch_generic,
843 [aoHidd_PCIDevice_RomSize] = dispatch_generic,
844 [aoHidd_PCIDevice_ExtendedConfig] = dispatch_generic,
845 [aoHidd_PCIDevice_ConfigSize] = dispatch_generic,
846 [aoHidd_PCIDevice_Base0] = dispatch_base,
847 [aoHidd_PCIDevice_Base1] = dispatch_base,
848 [aoHidd_PCIDevice_Base2] = dispatch_base,
849 [aoHidd_PCIDevice_Base3] = dispatch_base,
850 [aoHidd_PCIDevice_Base4] = dispatch_base,
851 [aoHidd_PCIDevice_Base5] = dispatch_base,
852 [aoHidd_PCIDevice_Size0] = dispatch_size,
853 [aoHidd_PCIDevice_Size1] = dispatch_size,
854 [aoHidd_PCIDevice_Size2] = dispatch_size,
855 [aoHidd_PCIDevice_Size3] = dispatch_size,
856 [aoHidd_PCIDevice_Size4] = dispatch_size,
857 [aoHidd_PCIDevice_Size5] = dispatch_size,
858 [aoHidd_PCIDevice_Type0] = dispatch_type,
859 [aoHidd_PCIDevice_Type1] = dispatch_type,
860 [aoHidd_PCIDevice_Type2] = dispatch_type,
861 [aoHidd_PCIDevice_Type3] = dispatch_type,
862 [aoHidd_PCIDevice_Type4] = dispatch_type,
863 [aoHidd_PCIDevice_Type5] = dispatch_type,
864
865 /* Bridge attributes */
866 [aoHidd_PCIDevice_isBridge] = dispatch_pci2pcibridge,
867 [aoHidd_PCIDevice_SubBus] = dispatch_pci2pcibridge,
868 [aoHidd_PCIDevice_MemoryBase] = dispatch_pci2pcibridge,
869 [aoHidd_PCIDevice_MemoryLimit] = dispatch_pci2pcibridge,
870 [aoHidd_PCIDevice_PrefetchableBase] = dispatch_pci2pcibridge,
871 [aoHidd_PCIDevice_PrefetchableLimit] = dispatch_pci2pcibridge,
872 [aoHidd_PCIDevice_IOBase] = dispatch_pci2pcibridge,
873 [aoHidd_PCIDevice_IOLimit] = dispatch_pci2pcibridge,
874 [aoHidd_PCIDevice_ISAEnable] = dispatch_pci2pcibridge,
875 [aoHidd_PCIDevice_VGAEnable] = dispatch_pci2pcibridge,
876
877 /* Capabilities */
878 [aoHidd_PCIDevice_CapabilityPowerManagement] = dispatch_capability,
879 [aoHidd_PCIDevice_CapabilityAGP] = dispatch_capability,
880 [aoHidd_PCIDevice_CapabilityVitalProductData] = dispatch_capability,
881 [aoHidd_PCIDevice_CapabilitySlotID] = dispatch_capability,
882 [aoHidd_PCIDevice_CapabilityMSI] = dispatch_capability,
883 [aoHidd_PCIDevice_CapabilityCPCIHotSwap] = dispatch_capability,
884 [aoHidd_PCIDevice_CapabilityPCIX] = dispatch_capability,
885 [aoHidd_PCIDevice_CapabilityHyperTransport] = dispatch_capability,
886 [aoHidd_PCIDevice_CapabilityVendorSpecific] = dispatch_capability,
887 [aoHidd_PCIDevice_CapabilityDebugPort] = dispatch_capability,
888 [aoHidd_PCIDevice_CapabilityCPCICRC] = dispatch_capability,
889 [aoHidd_PCIDevice_CapabilityHotPlugController] = dispatch_capability,
890 [aoHidd_PCIDevice_CapabilitySSVPID] = dispatch_capability,
891 [aoHidd_PCIDevice_CapabilityAGP3] = dispatch_capability,
892 [aoHidd_PCIDevice_CapabilityPCIE] = dispatch_capability,
893 [aoHidd_PCIDevice_CapabilityMSIX] = dispatch_capability,
894 [aoHidd_PCIDevice_CapabilityAdvancedFeatures] = dispatch_capability,
895
896 /* Extended capabilities */
897 [aoHidd_PCIDevice_ExtendedCapabilityAER] = dispatch_extendedcapability,
898 [aoHidd_PCIDevice_ExtendedCapabilityVC] = dispatch_extendedcapability,
899 [aoHidd_PCIDevice_ExtendedCapabilitySerialNumber] = dispatch_extendedcapability,
900 [aoHidd_PCIDevice_ExtendedCapabilityPowerBudgeting] = dispatch_extendedcapability,
901 };
902
903 void PCIDev__Root__Get(OOP_Class *cl, OOP_Object *o, struct pRoot_Get *msg)
904 {
905 ULONG idx;
906 tDeviceData *dev = (tDeviceData *)OOP_INST_DATA(cl,o);
907
908 if (IS_PCIDEV_ATTR(msg->attrID, idx))
909 {
910 if (Dispatcher[idx] != NULL)
911 Dispatcher[idx](cl, o, msg);
912 else switch(idx)
913 {
914 case aoHidd_PCIDevice_isMEM:
915 *msg->storage = (
916 (getWord(cl, o, PCICS_COMMAND) &
917 PCICMF_MEMDECODE)
918 == PCICMF_MEMDECODE);
919 break;
920
921 case aoHidd_PCIDevice_isIO:
922 *msg->storage = (
923 (getWord(cl, o, PCICS_COMMAND) &
924 PCICMF_IODECODE)
925 == PCICMF_IODECODE);
926 break;
927
928 case aoHidd_PCIDevice_isMaster:
929 *msg->storage = (
930 (getWord(cl, o, PCICS_COMMAND) &
931 PCICMF_BUSMASTER)
932 == PCICMF_BUSMASTER);
933 break;
934
935 case aoHidd_PCIDevice_paletteSnoop:
936 *msg->storage = (
937 (getWord(cl, o, PCICS_COMMAND) &
938 PCICMF_VGASNOOP)
939 == PCICMF_VGASNOOP);
940 break;
941
942 case aoHidd_PCIDevice_is66MHz:
943 *msg->storage = (
944 (getWord(cl, o, PCICS_STATUS) &
945 PCISTF_66MHZ)
946 == PCISTF_66MHZ);
947 break;
948
949 case aoHidd_PCIDevice_ClassDesc:
950 *msg->storage = (IPTR)dev->strClass;
951 break;
952
953 case aoHidd_PCIDevice_SubClassDesc:
954 *msg->storage = (IPTR)dev->strSubClass;
955 break;
956
957 case aoHidd_PCIDevice_InterfaceDesc:
958 *msg->storage = (IPTR)dev->strInterface;
959 break;
960
961 case aoHidd_PCIDevice_INTLine:
962 *msg->storage = getByte(cl, o, PCICS_INT_LINE);
963 break;
964
965 case aoHidd_PCIDevice_IRQStatus:
966 *msg->storage = (
967 (getWord(cl, o, PCICS_STATUS) &
968 PCISTF_INTERRUPT_STATUS)
969 == PCISTF_INTERRUPT_STATUS);
970 break;
971
972 case aoHidd_PCIDevice_CapabilitiesPresent:
973 *msg->storage = (
974 (getWord(cl, o, PCICS_STATUS) &
975 PCISTF_CAPABILITIES)
976 == PCISTF_CAPABILITIES);
977 break;
978
979 case aoHidd_PCIDevice_Owner:
980 *msg->storage = (IPTR)dev->ownerLock.ss_Link.ln_Name;
981 break;
982
983 default:
984 OOP_DoSuperMethod(cl, o, (OOP_Msg) msg);
985 break;
986 }
987 }
988 else
989 {
990 OOP_DoSuperMethod(cl, o, (OOP_Msg) msg);
991 }
992 }
993
994 void PCIDev__Root__Set(OOP_Class *cl, OOP_Object *o, struct pRoot_Set *msg)
995 {
996 ULONG idx;
997 tDeviceData *dev = (tDeviceData *)OOP_INST_DATA(cl,o);
998 struct TagItem *tag, *tags;
999
1000 tags = (struct TagItem *)msg->attrList;
1001
1002 while ((tag = NextTagItem(&tags)))
1003 {
1004 if (IS_PCIDEV_ATTR(tag->ti_Tag, idx))
1005 {
1006 switch(idx)
1007 {
1008 case aoHidd_PCIDevice_Base0:
1009 setLong(cl, o, PCICS_BAR0, tag->ti_Data);
1010 dev->BaseReg[0].addr = getLong(cl, o, PCICS_BAR0);
1011 break;
1012
1013 case aoHidd_PCIDevice_Base1:
1014 setLong(cl, o, PCICS_BAR1, tag->ti_Data);
1015 dev->BaseReg[1].addr = getLong(cl, o, PCICS_BAR1);
1016 break;
1017
1018 case aoHidd_PCIDevice_Base2:
1019 if (!dev->isBridge)
1020 {
1021 setLong(cl, o, PCICS_BAR2, tag->ti_Data);
1022 dev->BaseReg[2].addr = getLong(cl, o, PCICS_BAR2);
1023 }
1024 break;
1025
1026 case aoHidd_PCIDevice_Base3:
1027 if (!dev->isBridge)
1028 {
1029 setLong(cl, o, PCICS_BAR3, tag->ti_Data);
1030 dev->BaseReg[3].addr = getLong(cl, o, PCICS_BAR3);
1031 }
1032 break;
1033
1034 case aoHidd_PCIDevice_Base4:
1035 if (!dev->isBridge)
1036 {
1037 setLong(cl, o, PCICS_BAR4, tag->ti_Data);
1038 dev->BaseReg[4].addr = getLong(cl, o, PCICS_BAR4);
1039 }
1040 break;
1041
1042 case aoHidd_PCIDevice_Base5:
1043 if (!dev->isBridge)
1044 {
1045 setLong(cl, o, PCICS_BAR5, tag->ti_Data);
1046 dev->BaseReg[5].addr = getLong(cl, o, PCICS_BAR5);
1047 }
1048 break;
1049
1050 case aoHidd_PCIDevice_RomBase:
1051 setLong(cl, o, PCICS_EXPROM_BASE, tag->ti_Data);
1052 dev->RomBase = getLong(cl, o, PCICS_EXPROM_BASE);
1053 break;
1054
1055 case aoHidd_PCIDevice_MemoryBase:
1056 if (dev->isBridge) setWord(cl, o, PCIBR_MEMBASE, tag->ti_Data >> 16);
1057 break;
1058
1059 case aoHidd_PCIDevice_MemoryLimit:
1060 if (dev->isBridge) setWord(cl, o, PCIBR_MEMLIMIT, tag->ti_Data >> 16);
1061 break;
1062
1063 case aoHidd_PCIDevice_PrefetchableBase:
1064 if (dev->isBridge) setWord(cl, o, PCIBR_PREFETCHBASE, tag->ti_Data >> 16);
1065 break;
1066
1067 case aoHidd_PCIDevice_PrefetchableLimit:
1068 if (dev->isBridge) setWord(cl, o, PCIBR_PREFETCHLIMIT, tag->ti_Data >> 16);
1069 break;
1070
1071 case aoHidd_PCIDevice_IOBase:
1072 if (dev->isBridge) setByte(cl, o, PCIBR_IOBASE, tag->ti_Data >> 8);
1073 break;
1074
1075 case aoHidd_PCIDevice_IOLimit:
1076 if (dev->isBridge) setByte(cl, o, PCIBR_IOLIMIT, tag->ti_Data >> 8);
1077 break;
1078
1079 case aoHidd_PCIDevice_isIO:
1080 {
1081 UWORD command = getWord(cl, o, PCICS_COMMAND) & ~PCICMF_IODECODE;
1082 if (tag->ti_Data)
1083 command |= PCICMF_IODECODE;
1084 setWord(cl, o, PCICS_COMMAND, command);
1085 }
1086 break;
1087
1088 case aoHidd_PCIDevice_isMEM:
1089 {
1090 UWORD command = getWord(cl, o, PCICS_COMMAND) & ~PCICMF_MEMDECODE;
1091 if (tag->ti_Data)
1092 command |= PCICMF_MEMDECODE;
1093 setWord(cl, o, PCICS_COMMAND, command);
1094 }
1095 break;
1096
1097 case aoHidd_PCIDevice_isMaster:
1098 {
1099 UWORD command = getWord(cl, o, PCICS_COMMAND) & ~PCICMF_BUSMASTER;
1100 if (tag->ti_Data)
1101 command |= PCICMF_BUSMASTER;
1102 setWord(cl, o, PCICS_COMMAND, command);
1103 }
1104 break;
1105
1106 case aoHidd_PCIDevice_paletteSnoop:
1107 {
1108 UWORD command = getWord(cl, o, PCICS_COMMAND) & ~PCICMF_VGASNOOP;
1109 if (tag->ti_Data)
1110 command |= PCICMF_VGASNOOP;
1111 setWord(cl, o, PCICS_COMMAND, command);
1112 }
1113 break;
1114
1115 case aoHidd_PCIDevice_ISAEnable:
1116 if (dev->isBridge)
1117 {
1118 UWORD control = getWord(cl, o, PCIBR_CONTROL) & ~PCICTRLF_ISAENABLE;
1119 if (tag->ti_Data)
1120 control |= PCICTRLF_ISAENABLE;
1121 setWord(cl, o, PCIBR_CONTROL, control);
1122 }
1123 break;
1124
1125 case aoHidd_PCIDevice_VGAEnable:
1126 if (dev->isBridge)
1127 {
1128 UWORD control = getWord(cl, o, PCIBR_CONTROL) & ~PCICTRLF_VGAENABLE;
1129 if (tag->ti_Data)
1130 control |= PCICTRLF_VGAENABLE;
1131 setWord(cl, o, PCIBR_CONTROL, control);
1132 }
1133 break;
1134
1135 default:
1136 bug("[PCIDevice] Trying to set nonsettable attribute %d!\n", idx);
1137 break;
1138 }
1139 }
1140 }
1141 }
Mirror of AROS' svn.