arch/all-darwin/kernel/cpu_ppc.h

   1 /*
   2     Copyright © 1995-2010, The AROS Development Team. All rights reserved.
   3     $Id$
   4 */
   5
   6 #include <exec/types.h>
   7 #include <aros/ppc/cpucontext.h>
   8
   9 #ifdef __AROS_EXEC_LIBRARY__
  10
  11 /* regs_t is a black box here */
  12 struct ucontext;
  13 typedef struct ucontext *regs_t;
  14
  15 #else
  16
  17 #include <sys/ucontext.h>
  18
  19 #define SIGCORE_NEED_SA_SIGINFO
  20
  21 typedef ucontext_t regs_t;
  22
  23 #define SIGHANDLER      bsd_sighandler
  24 typedef void (*SIGHANDLER_T)(int);
  25
  26 #define SC_DISABLE(sc)   sc->uc_sigmask = KernelBase->kb_PlatformData->sig_int_mask
  27 #define SC_ENABLE(sc)    pd->iface->SigEmptySet(&(sc)->uc_sigmask)
  28
  29 /* work around silly renaming of struct members in OS X 10.5 */
  30 #if __DARWIN_UNIX03
  31
  32 #define DAR(context)     ((context)->uc_mcontext->__es.__dar)
  33 #define DSISR(context)   ((context)->uc_mcontext->__es.__dsisr)
  34
  35 #define PC(context)      ((context)->uc_mcontext->__ss.__srr0)
  36 #define SRR1(context)    ((context)->uc_mcontext->__ss.__srr1)
  37 #define R0(context)      ((context)->uc_mcontext->__ss.__r0)
  38 #define SP(context)      ((context)->uc_mcontext->__ss.__r1)
  39 #define R2(context)      ((context)->uc_mcontext->__ss.__r2)
  40 #define R3(context)      ((context)->uc_mcontext->__ss.__r3)
  41 #define R4(context)      ((context)->uc_mcontext->__ss.__r4)
  42 #define R5(context)      ((context)->uc_mcontext->__ss.__r5)
  43 #define R6(context)      ((context)->uc_mcontext->__ss.__r6)
  44 #define R7(context)      ((context)->uc_mcontext->__ss.__r7)
  45 #define R8(context)      ((context)->uc_mcontext->__ss.__r8)
  46 #define R9(context)      ((context)->uc_mcontext->__ss.__r9)
  47 #define R10(context)     ((context)->uc_mcontext->__ss.__r10)
  48 #define R11(context)     ((context)->uc_mcontext->__ss.__r11)
  49 #define R12(context)     ((context)->uc_mcontext->__ss.__r12)
  50 #define CR(context)      ((context)->uc_mcontext->__ss.__cr)
  51 #define XER(context)     ((context)->uc_mcontext->__ss.__xer)
  52 #define CTR(context)     ((context)->uc_mcontext->__ss.__ctr)
  53 #define LR(context)      ((context)->uc_mcontext->__ss.__lr)
  54 #define VRSAVE(context)  ((context)->uc_mcontext->__ss.__vrsave)
  55
  56 #define FPSCR(context)   ((context)->uc_mcontext->__fs.__fpscr)
  57
  58 #define VR(context)      ((context)->uc_mcontext->__vs.__save_vr)
  59 #define VSCR(context)    ((context)->uc_mcontext->__vs.__save_vscr)
  60 #define VRVALID(context) ((context)->uc_mcontext->__vs.__save_vrvalid)
  61
  62 #define FPSTATE(context) ((context)->uc_mcontext->__fs)
  63
  64 #else
  65
  66 #define DAR(context)     ((context)->uc_mcontext->es.dar)
  67 #define DSISR(context)   ((context)->uc_mcontext->es.dsisr)
  68
  69 #define PC(context)      ((context)->uc_mcontext->ss.srr0)
  70 #define SRR1(context)    ((context)->uc_mcontext->ss.srr1)
  71 #define R0(context)      ((context)->uc_mcontext->ss.r0)
  72 #define SP(context)      ((context)->uc_mcontext->ss.r1)
  73 #define R2(context)      ((context)->uc_mcontext->ss.r2)
  74 #define R3(context)      ((context)->uc_mcontext->ss.r3)
  75 #define R4(context)      ((context)->uc_mcontext->ss.r4)
  76 #define R5(context)      ((context)->uc_mcontext->ss.r5)
  77 #define R6(context)      ((context)->uc_mcontext->ss.r6)
  78 #define R7(context)      ((context)->uc_mcontext->ss.r7)
  79 #define R8(context)      ((context)->uc_mcontext->ss.r8)
  80 #define R9(context)      ((context)->uc_mcontext->ss.r9)
  81 #define R10(context)     ((context)->uc_mcontext->ss.r10)
  82 #define R11(context)     ((context)->uc_mcontext->ss.r11)
  83 #define R12(context)     ((context)->uc_mcontext->ss.r12)
  84 #define CR(context)      ((context)->uc_mcontext->ss.cr)
  85 #define XER(context)     ((context)->uc_mcontext->ss.xer)
  86 #define CTR(context)     ((context)->uc_mcontext->ss.ctr)
  87 #define LR(context)      ((context)->uc_mcontext->ss.lr)
  88 #define VRSAVE(context)  ((context)->uc_mcontext->ss.vrsave)
  89
  90 #define FPSCR(context)   ((context)->uc_mcontext->fs.fpscr)
  91
  92 #define VR(context)      ((context)->uc_mcontext->vs.save_vr)
  93 #define VSCR(context)    ((context)->uc_mcontext->vs.save_vscr)
  94 #define VRVALID(context) ((context)->uc_mcontext->vs.save_vrvalid)
  95
  96 #define FPSTATE(context) ((context)->uc_mcontext->fs)
  97
  98 #endif
  99
 100 #define GLOBAL_SIGNAL_INIT(sighandler) \
 101         static void sighandler ## _gate (int sig, int code, ucontext_t *sc) \
 102         {                                                    \
 103             sighandler(sig, sc);                             \
 104         }
 105
 106 /*
 107  * SAVEREGS and RESTOREREGS rely on the fact that layout of some parts of
 108  * struct ExceptionContext (r0 - xer and FPU state) is the same as layout
 109  * of these parts in Darwin's context.
 110  */
 111 #define SAVEREGS(cc, sc)                                                        \
 112     (cc)->regs.Flags  = ECF_FULL_GPRS|ECF_FPU|ECF_FULL_FPU|ECF_VRSAVE;          \
 113     (cc)->regs.msr    = SRR1(sc);                                               \
 114     (cc)->regs.ip     = PC(sc);                                                 \
 115     CopyMemQuick(&R0(sc), (cc)->regs.gpr, 34 * sizeof(ULONG));                  \
 116     (cc)->regs.ctr    = CTR(sc);                                                \
 117     (cc)->regs.lr     = LR(sc);                                                 \
 118     (cc)->regs.dsisr  = DSISR(sc);                                              \
 119     (cc)->regs.dar    = DAR(sc);                                                \
 120     CopyMemQuick(&FPSTATE(sc), (cc)->regs.fpr, sizeof(_STRUCT_PPC_FLOAT_STATE)); \
 121     (cc)->regs.vrsave = VRSAVE(sc);                                             \
 122     if (VRVALID(sc))                                                            \
 123     {                                                                           \
 124         (cc)->regs.Flags |= ECF_VECTOR;                                         \
 125         CopyMemQuick(VR(sc), (cc)->regs.vr, 512);                               \
 126         CopyMemQuick(VSCR(sc), (cc)->regs.vscr, 16);                            \
 127     }
 128
 129 #define RESTOREREGS(cc, sc)                                                     \
 130 {                                                                               \
 131     ULONG n    = ((cc)->regs.Flags & ECF_FULL_GPRS) ? 32 : 14;                  \
 132     SRR1(sc)   = (cc)->regs.msr;                                                \
 133     PC(sc)     = (cc)->regs.ip;                                                 \
 134     CopyMemQuick((cc)->regs.gpr, &R0(sc), n * sizeof(ULONG));                   \
 135     CR(sc)     = (cc)->regs.cr;                                                 \
 136     XER(sc)    = (cc)->regs.xer;                                                \
 137     CTR(sc)    = (cc)->regs.ctr;                                                \
 138     LR(sc)     = (cc)->regs.lr;                                                 \
 139     DSISR(sc)  = (cc)->regs.dsisr;                                              \
 140     DAR(sc)    = (cc)->regs.dar;                                                \
 141     if ((cc)->regs.Flags & ECF_FPU)                                             \
 142         CopyMemQuick(&FPSTATE(sc), (cc)->regs.fpr, 32 * sizeof(double));        \
 143     if ((cc)->regs.Flags & ECF_FULL_FPU)                                        \
 144         FPSCR(sc)  = (cc)->regs.fpscr;                                          \
 145     if ((cc)->regs.Flags & ECF_VRSAVE)                                          \
 146         VRSAVE(sc) = (cc)->regs.vrsave;                                         \
 147     if ((cc)->regs.Flags & ECF_VECTOR)                                          \
 148     {                                                                           \
 149         CopyMemQuick((cc)->regs.vr, VR(sc), 512);                               \
 150         CopyMemQuick((cc)->regs.vscr, VSCR(sc), 16);                            \
 151     }                                                                           \
 152 }
 153
 154 /* Print signal context. Used in crash handler */
 155 #define PRINT_SC(sc)                                    \
 156     bug ("    R0 =%08X  R1=%08X  R2 =%08X  R3 =%08X\n"  \
 157          "    R4 =%08X  R5=%08X  R6 =%08X  R7 =%08X\n"  \
 158          "    R8 =%08X  R9=%08X  R10=%08X  R11=%08X\n"  \
 159          "    R12=%08X  LR=%08X  MSR=%08X  IP =%08X\n"  \
 160             , R0(sc), SP(sc), R2(sc), R3(sc)            \
 161             , R4(sc), R5(sc), R6(sc), R7(sc)            \
 162             , R8(sc), R9(sc), R10(sc), R11(sc)          \
 163             , R12(sc), LR(sc), SRR1(sc), PC(sc) \
 164         )
 165
 166 #endif /* __AROS_EXEC_LIBRARY__ */
 167
 168 #define EXCEPTIONS_COUNT 14
 169
 170 struct AROSCPUContext
 171 {
 172     struct ExceptionContext regs;
 173     int errno_backup;
 174 };