arch/all-darwin/kernel/cpu_x86_64.h

   1 /*
   2     Copyright © 1995-2010, The AROS Development Team. All rights reserved.
   3     $Id$
   4 */
   5
   6 #include <sys/types.h>
   7
   8 #include <aros/x86_64/cpucontext.h>
   9
  10 #ifdef __AROS_EXEC_LIBRARY__
  11
  12 /* regs_t is a black box here */
  13 struct ucontext;
  14 typedef struct ucontext *regs_t;
  15
  16 #else
  17
  18 #include <sys/ucontext.h>
  19
  20 #define SIGCORE_NEED_SA_SIGINFO
  21
  22 typedef ucontext_t regs_t;
  23
  24 #define SIGHANDLER      bsd_sighandler
  25 typedef void (*SIGHANDLER_T)(int);
  26
  27 #define SC_DISABLE(sc)   sc->uc_sigmask = KernelBase->kb_PlatformData->sig_int_mask
  28 #define SC_ENABLE(sc)    pd->iface->SigEmptySet(&(sc)->uc_sigmask)
  29
  30 /* work around silly renaming of struct members in OS X 10.5 */
  31 #if __DARWIN_UNIX03 && defined(_STRUCT_X86_EXCEPTION_STATE32)
  32
  33 #define R0(context)     ((context)->uc_mcontext->__ss.__rax)
  34 #define R1(context)     ((context)->uc_mcontext->__ss.__rbx)
  35 #define R2(context)     ((context)->uc_mcontext->__ss.__rcx)
  36 #define R3(context)     ((context)->uc_mcontext->__ss.__rdx)
  37 #define R4(context)     ((context)->uc_mcontext->__ss.__rdi)
  38 #define R5(context)     ((context)->uc_mcontext->__ss.__rsi)
  39 #define R6(context)     ((context)->uc_mcontext->__ss.__rflags)
  40 #define R8(context)     ((context)->uc_mcontext->__ss.__r8)
  41 #define R9(context)     ((context)->uc_mcontext->__ss.__r9)
  42 #define R10(context)    ((context)->uc_mcontext->__ss.__r10)
  43 #define R11(context)    ((context)->uc_mcontext->__ss.__r11)
  44 #define R12(context)    ((context)->uc_mcontext->__ss.__r12)
  45 #define R13(context)    ((context)->uc_mcontext->__ss.__r13)
  46 #define R14(context)    ((context)->uc_mcontext->__ss.__r14)
  47 #define R15(context)    ((context)->uc_mcontext->__ss.__r15)
  48
  49 #define FP(context)     ((context)->uc_mcontext->__ss.__rbp)
  50 #define PC(context)     ((context)->uc_mcontext->__ss.__rip)
  51 #define SP(context)     ((context)->uc_mcontext->__ss.__rsp)
  52
  53 #define CS(context)     ((context)->uc_mcontext->__ss.__cs)
  54 #define FS(context)     ((context)->uc_mcontext->__ss.__fs)
  55 #define GS(context)     ((context)->uc_mcontext->__ss.__gs)
  56
  57 #define FPSTATE(context) ((context)->uc_mcontext->__fs.__fpu_fcw)
  58
  59 #else
  60
  61 #define R0(context)     ((context)->uc_mcontext->ss.eax)
  62 #define R1(context)     ((context)->uc_mcontext->ss.ebx)
  63 #define R2(context)     ((context)->uc_mcontext->ss.ecx)
  64 #define R3(context)     ((context)->uc_mcontext->ss.edx)
  65 #define R4(context)     ((context)->uc_mcontext->ss.edi)
  66 #define R5(context)     ((context)->uc_mcontext->ss.esi)
  67 #define R6(context)     ((context)->uc_mcontext->ss.eflags)
  68 #define R8(context)     ((context)->uc_mcontext->ss.r8)
  69 #define R9(context)     ((context)->uc_mcontext->ss.r9)
  70 #define R10(context)    ((context)->uc_mcontext->ss.r10)
  71 #define R11(context)    ((context)->uc_mcontext->ss.r11)
  72 #define R12(context)    ((context)->uc_mcontext->ss.r12)
  73 #define R13(context)    ((context)->uc_mcontext->ss.r13)
  74 #define R14(context)    ((context)->uc_mcontext->ss.r14)
  75 #define R15(context)    ((context)->uc_mcontext->ss.r15)
  76
  77 #define FP(context)     ((context)->uc_mcontext->ss.ebp)
  78 #define PC(context)     ((context)->uc_mcontext->ss.eip)
  79 #define SP(context)     ((context)->uc_mcontext->ss.esp)
  80
  81 #define CS(context)     ((context)->uc_mcontext->ss.cs)
  82 #define FS(context)     ((context)->uc_mcontext->ss.fs)
  83 #define GS(context)     ((context)->uc_mcontext->ss.gs)
  84
  85 #define FPSTATE(context) ((context)->uc_mcontext->fs.fpu_fcw)
  86
  87 #endif
  88
  89 #define GLOBAL_SIGNAL_INIT(sighandler) \
  90         static void sighandler ## _gate (int sig, int code, ucontext_t *sc) \
  91         {                                                    \
  92             sighandler(sig, sc);                             \
  93         }
  94
  95 /*
  96  * Save CPU registers.
  97  * Unfortunately Darwin doesn't provide us with values of all segment registers.
  98  * We can't do anything with it.
  99  */
 100 #define SAVE_CPU(cc, sc)        \
 101     cc.Flags = ECF_SEGMENTS;    \
 102     cc.rax    = R0(sc);         \
 103     cc.rbx    = R1(sc);         \
 104     cc.rcx    = R2(sc);         \
 105     cc.rdx    = R3(sc);         \
 106     cc.rdi    = R4(sc);         \
 107     cc.rsi    = R5(sc);         \
 108     cc.rflags = R6(sc);         \
 109     cc.r8     = R8(sc);         \
 110     cc.r9     = R9(sc);         \
 111     cc.r10    = R10(sc);        \
 112     cc.r11    = R11(sc);        \
 113     cc.r12    = R12(sc);        \
 114     cc.r13    = R13(sc);        \
 115     cc.r14    = R14(sc);        \
 116     cc.r15    = R15(sc);        \
 117     cc.rbp    = FP(sc);         \
 118     cc.rip    = PC(sc);         \
 119     cc.rsp    = SP(sc);         \
 120     cc.cs     = CS(sc);         \
 121     cc.fs     = FS(sc);         \
 122     cc.gs     = GS(sc);
 123
 124 /*
 125  * Restore CPU registers.
 126  * Note that we do not restore segment registers because they
 127  * are of own use by Darwin.
 128  */
 129 #define RESTORE_CPU(cc, sc) \
 130     R0(sc)  = cc.rax;       \
 131     R1(sc)  = cc.rbx;       \
 132     R2(sc)  = cc.rcx;       \
 133     R3(sc)  = cc.rdx;       \
 134     R4(sc)  = cc.rdi;       \
 135     R5(sc)  = cc.rsi;       \
 136     R6(sc)  = cc.rflags;    \
 137     R8(sc)  = cc.r8;        \
 138     R9(sc)  = cc.r9;        \
 139     R10(sc) = cc.r10;       \
 140     R11(sc) = cc.r11;       \
 141     R12(sc) = cc.r12;       \
 142     R13(sc) = cc.r13;       \
 143     R14(sc) = cc.r14;       \
 144     R15(sc) = cc.r15;       \
 145     FP(sc)  = cc.rbp;       \
 146     PC(sc)  = cc.rip;       \
 147     SP(sc)  = cc.rsp;
 148
 149 /*
 150  * Save all registers from UNIX signal context to AROS context.
 151  * Save also SSE state if the context has buffer. ECF_FPX will be set
 152  * if SSE state was copied.
 153  */
 154 #define SAVEREGS(cc, sc)                                                                \
 155     SAVE_CPU((cc)->regs, sc);                                                           \
 156     if ((cc)->regs.FXData)                                                              \
 157     {                                                                                   \
 158         (cc)->regs.Flags |= ECF_FPX;                                                    \
 159         CopyMemQuick(&FPSTATE(sc), (cc)->regs.FXData, sizeof(struct FPXContext));       \
 160     }
 161
 162 /*
 163  * Restore all registers from AROS context to UNIX signal context.
 164  * Check context flags to decide whether to restore SSE or not.
 165  */
 166 #define RESTOREREGS(cc, sc)                                                             \
 167     RESTORE_CPU((cc)->regs, sc);                                                        \
 168     if ((cc)->regs.Flags & ECF_FPX)                                                     \
 169         CopyMemQuick((cc)->regs.FXData, &FPSTATE(sc), sizeof(struct FPXContext));
 170
 171 /* Print signal context. Used in crash handler. */
 172 #define PRINT_SC(sc)                                            \
 173     bug ("    RSP=%016lx  RBP=%016lx  RIP=%016lx\n"             \
 174          "    RAX=%016lx  RBX=%016lx  RCX=%016lx  RDX=%016lx\n" \
 175          "    RDI=%016lx  RSI=%016lx  RFLAGS=%016lx\n"          \
 176          "    R8 =%016lx  R9 =%016lx  R10=%016lx  R11=%016lx\n" \
 177          "    R12=%016lx  R13=%016lx  R14=%016lx  R15=%016lx\n" \
 178          , SP(sc), FP(sc), PC(sc)                               \
 179          , R0(sc), R1(sc), R2(sc), R3(sc)                       \
 180          , R4(sc), R5(sc), R6(sc), R8(sc), R9(sc)               \
 181          , R10(sc), R11(sc), R12(sc), R13(sc), R14(sc), R15(sc) \
 182         )
 183
 184 #endif /* __AROS_EXEC_LIBRARY__ */
 185
 186 #define EXCEPTIONS_COUNT 17
 187
 188 struct AROSCPUContext
 189 {
 190     struct ExceptionContext regs;
 191     int errno_backup;
 192 };