| blob | 0c9ff9fafedbad228e767fce758fe294f0e7d971 |
1 /*
2 Copyright © 1995-2001, The AROS Development Team. All rights reserved.
3 $Id$
4 */
6 #ifndef REGISTERS_H
7 #define REGISTERS_H
9 #ifdef __PILOT_CODE__
10 #define WREG_L(addr) *(Long *)(addr)
11 #define RREG_L(addr) *(Long *)(addr)
12 #define WREG_W(addr) *(Word *)(addr)
13 #define RREG_W(addr) *(Word *)(addr)
14 #define WREG_B(addr) *(Byte *)(addr)
15 #define RREG_B(addr) *(Byte *)(addr)
16 #else
17 #include <exec/types.h>
18 #define WREG_L(addr) *(ULONG *)(addr)
19 #define RREG_L(addr) *(ULONG *)(addr)
20 #define WREG_W(addr) *(UWORD *)(addr)
21 #define RREG_W(addr) *(UWORD *)(addr)
22 #define WREG_B(addr) *(UBYTE *)(addr)
23 #define RREG_B(addr) *(UBYTE *)(addr)
24 #endif
27 /*
28 * System Controler Registers
29 */
31 #define SCR 0xfffff000
32 #define PCR 0xfffff003
33 #define IDR 0xfffff004
34 #define IODCR 0xfffff008
36 /*
37 * Some Flags for the System Control registers
38 */
39 #define BETO_F (1<<7)
40 #define WPV_F (1<<6)
41 #define PRV_F (1<<5)
42 #define BETEN_F (1<<4)
43 #define SO_F (1<<3)
44 #define DMAP_F (1<<2)
45 #define WDTH_F (1<<0)
48 /*
49 * Whatever is in chapter 6 in the downloadable
50 * dragonball documentation seems to be wrong.
51 * Found the correct register description in the
52 * xcopilot source.
53 */
54 #if 0
56 #define CSGBA 0xfffff100
57 #define CSGBB 0xfffff102
58 #define CSGBC 0xfffff104
59 #define CSGBD 0xfffff106
60 #define CSUGBA 0xfffff108
61 #define CSCR 0xfffff10A
62 #define CSA 0xfffff110
63 #define CSB 0xfffff112
64 #define CSC 0xfffff114
65 #define CSD 0xfffff116
67 #else
69 #define GRPBASEA 0xfffff100
70 #define GRPBASEB 0xfffff102
71 #define GRPBASEC 0xfffff104
72 #define GRPBASED 0xfffff100
74 #define GRPMASKA 0xfffff108
75 #define GRPMASKB 0xfffff10A
76 #define GRPMASKC 0xfffff10C
77 #define GRPMASKD 0xfffff10E
79 #define CSA0 0xfffff110
80 #define CSA1 0xfffff114
81 #define CSA2 0xfffff118
82 #define CSA3 0xfffff11c
84 #define CSC0 0xfffff130
85 #define CSC1 0xfffff134
86 #define CSC2 0xfffff138
87 #define CSC3 0xfffff13c
89 /*
90 * CSA0-3, CSC0-3:
91 *
92 * Bit 0-2 : Wait states
93 * Bit 3 : Read only (if '1')
94 * Bit 4-7 : reserved
95 * Bit 8-15 : AM (???)
96 * Bit 16 : bus width
97 * Bit 17-23: reserved
98 * Bit 24-31: AC (???)
99 */
100 #endif
102 #define PCTLR 0xfffff207
104 /*
105 * Interrupt Controller Registers
106 */
107 #define IVR 0xfffff300
108 #define ICR 0xfffff302
109 #define IMR 0xfffff304
110 #define IWR 0xfffff308
111 #define ISR 0xfffff30c
112 #define IPR 0xfffff310
113 #define ILCR 0xfffff314
115 /*
116 * Port A:
117 */
118 /*
119 * Port B:
120 */
121 /*
122 * Port C:
123 */
124 /*
125 * Port D:
126 */
127 #define PDDIR 0xfffff418
128 #define PDDATA 0xfffff419
129 #define PDPUEN 0xfffff41a
130 #define PDSEL 0xfffff41b
131 #define PDPOL 0xfffff41c
132 #define PDIRQEN 0xfffff41d
133 #define PDKBEN 0xfffff41e
134 #define PDIRQEG 0xfffff41f
135 /*
136 * Port E:
137 */
138 #define PEDIR 0xfffff420
139 #define PEDATA 0xfffff421
140 #define PEPUN 0xfffff422
141 #define PESEL 0xfffff423
143 /*
144 * Port F: Turn LCD display on/off, ...
145 */
146 #define PFDIR 0xfffff428
147 #define PFDATA 0xfffff429
148 #define PFPUEN 0xfffff42a
149 #define PFSEL 0xfffff42b
151 /*
152 * General Purpose Timers Registers
153 */
154 #define TCTL1 0xfffff600
155 #define TPRER1 0xfffff602
156 #define TCMP1 0xfffff604
157 #define TCR1 0xfffff606
158 #define TCN1 0xfffff608
159 #define TSTAT1 0xfffff60a
161 #define TCTL2 0xfffff60c
162 #define TPRER2 0xfffff60e
163 #define TCMP2 0xfffff610
164 #define TCR2 0xfffff612
165 #define TCN2 0xfffff614
166 #define TSTAT2 0xfffff616
169 #define FRR_F (1<<8)
170 #define CAP_M (1<<7|1<<6)
171 #define OM_F (1<<5)
172 #define IRQEN (1<<4)
173 #define CLKSOURCE_M (1<<3|1<<2|1<<1)
174 #define TEN_F (1<<0)
176 #define CAPT_F (1<<1)
177 #define COMP_F (1<<0)
180 /*
181 * Serial Peripheral Interface 1 and 2
182 */
183 #define SPIRXD 0xfffff700
184 #define SPITXD 0xfffff702
185 #define SPICONT1 0xfffff704
186 #define SPIINTCS 0xfffff706
187 #define SPITEST 0xfffff708
188 #define SPISPC 0xfffff70a
190 #define SPIDATA2 0xfffff800
191 #define SPICONT2 0xfffff802
193 /*
194 * Some flags for SPI 2
195 */
196 #define SPI_ENABLE_F (1<<9)
197 #define SPI_XCH_F (1<<8)
198 #define SPI_IRQ_F (1<<7)
199 #define SPI_IRQEN_F (1<<6)
200 #define SPI_PHA_F (1<<5)
201 #define SPI_POL_F (1<<4)
203 /*
204 * UART 1 & 2
205 */
207 #define USTCNT1 0xfffff900
208 #define UBAUD1 0xfffff902
209 #define URX1 0xfffff904
210 #define UTX1 0xfffff906
211 #define UMISC1 0xfffff908
212 #define NIPR1 0xfffff90a
214 #define USTCNT2 0xfffff910
215 #define UBAUD2 0xfffff912
216 #define URX2 0xfffff914
217 #define UTX2 0xfffff916
218 #define UMISC2 0xfffff918
219 #define NIPR2 0xfffff91a
221 /*
222 * Flags for USTCNT1/2 register
223 */
224 #define UEN_F (1 << 15)
225 #define RXEN_F (1 << 14)
226 #define TXEN_F (1 << 13)
227 #define CLKM_F (1 << 12)
228 #define PARITY_EN_F (1 << 11)
229 #define ODD_F (1 << 10)
230 #define STOP_F (1 << 9)
231 #define EITHER8OR7_F (1 << 8)
232 #define ODEN_F (1 << 7)
233 #define CTSD_F (1 << 6)
234 #define RXFE_F (1 << 5)
235 #define RXHE_F (1 << 4)
236 #define RXRE_F (1 << 3)
237 #define TXEE_F (1 << 2)
238 #define TXHE_F (1 << 1)
239 #define TXAE_F (1 << 0)
241 /*
242 * Flags for UBAUD1/2 register
243 */
244 #define UCLKDIR_F (1 << 13)
245 #define BAUD_SRC_F (1 << 11)
247 /*
248 * Flagss for URX1/2 register
249 */
250 #define FIFO_FULL_F (1 << 15)
251 #define FIFO_HALF_F (1 << 14)
252 #define DATA_READY_F (1 << 13)
253 #define OLD_DATA_F (1 << 12)
254 #define OVRUN_F (1 << 11)
255 #define FRAME_ERROR_F (1 << 10)
256 #define BREAK_F (1 << 9)
257 #define PARITY_ERROR_F (1 << 8)
259 /*
260 * Flags for URX1/2 register
261 */
262 #define FIFO_EMPTY_F (1 << 15)
263 #define FIFO_HALF_F (1 << 14)
264 #define TX_AVAIL_F (1 << 13)
265 #define SEND_BREAK_F (1 << 12)
266 #define NOCTS1_F (1 << 11)
267 #define BUSY_F (1 << 10)
268 #define CTS1_STAT_F (1 << 9)
269 #define CTS1_DELTA_F (1 << 8)
271 /*
272 * Flags for the UMISC1/2 register
273 */
274 #define BAUD_TEST_F (1 << 15)
275 #define CLKSRC_F (1 << 14)
276 #define FORCE_PERR_F (1 << 13)
277 #define LOOP_F (1 << 12)
278 #define BAUD_RESET_F (1 << 11)
279 #define IRTEST_F (1 << 10)
280 #define RTS1_CONT_F (1 << 7)
281 #define RTS1_F (1 << 6)
282 #define IRDAEN_F (1 << 5)
283 #define IRDA_LOOP_F (1 << 4)
284 #define RXPOL_F (1 << 3)
285 #define TXPOL_F (1 << 2)
288 /*
289 * Offsets
290 */
291 #define O_USTCNT 0
292 #define O_UBAUD 2
293 #define O_URX 4
294 #define O_UTX 6
295 #define O_UMISC 8
296 #define O_NIPR 10
298 /*
299 * LCD Controller Registers
300 */
301 #define LSSA 0xfffffa00
302 #define LVPW 0xfffffa05
303 #define LXMAX 0xfffffa08
304 #define LYMAX 0xfffffa0a
305 #define LCXP 0xfffffa18
306 #define LCYP 0xfffffa1a
308 #define LCWCH 0xfffffa1c
309 #define LBLKC 0xfffffa1f
310 #define LPICF 0xfffffa20
311 #define LPOLCF 0xfffffa21
312 #define LACDRC 0xfffffa23
313 #define LPXCD 0xfffffa25
314 #define LCKCON 0xfffffa27
315 #define LRRA 0xfffffa28
316 #define LOTCR 0xfffffa2b
317 #define LPOSR 0xfffffa2d
318 #define LFRCM 0xfffffa31
319 #define LGPMR 0xfffffa33
320 #define PWMR 0xfffffa36
321 #define RMCR 0xfffffa38
324 /*
325 * Real time clock registers
326 */
328 #define RTCTIME 0xfffffb00
329 #define RTCAKRM 0xfffffb04
330 #define WATCHDOG 0xfffffb0a
331 #define RTCCTL 0xfffffb0c
332 #define RTCISR 0xfffffb0e
333 #define RTCIENR 0xfffffb10
334 #define STPWCH 0xfffffb12
335 #define DAYR 0xfffffb1a
336 #define DAYALARM 0xfffffb1c
338 #define HOURS_M (1<<28|1<<27|1<<26|1<<25|1<<24)
339 #define MINUTES_M (1<<21|1<<20|1<<19|1<<18|1<<17|1<<16)
340 #define SECONDS_M (1<<5|1<<4|1<<3|1<<2|1<<1|1<<0)
342 #define DAYSAL_M 0x01ff
344 #define CNTR_M (0x03 << 8)
345 #define INTF_F (0x01 << 7)
346 #define ISEL_F (0x01 << 1)
347 #define EN_F (0x01 << 0)
349 #define RTCEN_F (0x01 << 7)
350 #define REFREQ_F (0x01 << 5)
352 #define DRAMMC 0xfffffc00
353 #define DRAMC 0xfffffc00
354 #define SDCTRL 0xfffffc00
355 #define SDPWDN 0xfffffc00
357 /*
358 * Flags used by the Interrupt controller - again the dragonball
359 * doc is all wrong - have a look at the xcopilot sources.
360 */
362 /* Flags for IMR, ISR, IPR */
363 #define SPI2_F (0x01 << 0)
364 #define TMR2_F (0x01 << 1)
365 #define UART1_F (0x01 << 2)
366 #define WDT_F (0x01 << 3)
367 #define RTC_F (0x01 << 4)
368 #define LCDC_F (0x01 << 5)
369 #define KB_F (0x01 << 6)
370 #define PWM1_F (0x01 << 7)
371 #define INT0_F (0x01 << 8)
372 #define INT1_F (0x01 << 9)
373 #define INT2_F (0x01 << 10)
374 #define INT3_F (0x01 << 11)
375 #define INT4_F (0x01 << 12)
376 #define INT5_F (0x01 << 13)
377 #define INT6_F (0x01 << 14)
378 #define INT7_F (0x01 << 15)
379 #define IRQ1_F (0x01 << 16)
380 #define IRQ2_F (0x01 << 17)
381 #define IRQ3_F (0x01 << 18)
382 #define IRQ6_F (0x01 << 19)
383 #define PEN_F (0x01 << 20)
384 #define SPIS_F (0x01 << 21)
385 #define TMR1_F (0x01 << 22)
386 #define IRQ7_F (0x01 << 23)
388 /* Flags for ICR */
389 #define POL5_F (0x01 << 7)
390 #define ET6_F (0x01 << 8)
391 #define ET3_F (0x01 << 9)
392 #define ET2_F (0x01 << 10)
393 #define ET1_F (0x01 << 11)
394 #define POL6_F (0x01 << 12)
395 #define POL3_F (0x01 << 13)
396 #define POL2_F (0x01 << 14)
397 #define POL1_F (0x01 << 15)
398 #define POL1_F (0x01 << 15)
399 #define POL1_F (0x01 << 15)
400 #define POL1_F (0x01 << 15)
401 #define POL1_F (0x01 << 15)
402 #define POL1_F (0x01 << 15)
403 #define POL1_F (0x01 << 15)
404 #define POL1_F (0x01 << 15)
406 #endif