workbench/devs/AHI/Drivers/Envy24/regs.h

   1 /*
   2     Copyright � 2004-2014, Davy Wentzler. All rights reserved.
   3     $Id$
   4 */
   5
   6 #ifndef _REGS_H
   7 #define _REGS_H
   8
   9 #define CCS_CTRL                0x0000
  10     #define CCS_RESET_ALL           0x80
  11     #define CCS_NATIVE_MODE         0x01
  12
  13 #define CCS_INTR_MASK           0x0001
  14     #define CCS_ENABLE_MIDI1        0x80
  15     #define CCS_ENABLE_TIMER        0x40
  16     #define CCS_ENABLE_MIDI2        0x20
  17     #define CCS_ENABLE_PRO_MACRO    0x10
  18     #define CCS_ENABLE_FM           0x08
  19     #define CCS_ENABLE_PLAY_DS      0x04
  20     #define CCS_ENABLE_CONS_REC     0x02
  21     #define CCS_ENABLE_CONS_PLAY    0x01
  22
  23 #define CCS_INTR_STATUS         0x0002
  24     #define CCS_INTR_MIDI1          0x80
  25     #define CCS_INTR_TIMER          0x40
  26     #define CCS_INTR_MIDI2          0x20
  27     #define CCS_INTR_PRO_MACRO      0x10
  28     #define CCS_INTR_FM             0x08
  29     #define CCS_INTR_PLAY_DS        0x04
  30     #define CCS_INTR_CONS_REC       0x02
  31     #define CCS_INTR_CONS_PLAY      0x01
  32
  33 #define CCS_ENVY_INDEX          0x0003 // CCI registers
  34 #define CCS_ENVY_DATA           0x0004
  35
  36 #define CCS_MIDI1_DATA          0x000C
  37 #define CCS_MIDI1_CMD_STATUS    0x000D
  38
  39 #define CCS_I2C_DEV_ADDRESS     0x0010   // check CCS13 before accessing
  40     #define CCS_ADDRESS_MASK        0xFE // I2C device address (bit 7:1)
  41     #define CCS_ADDRESS_SHIFT       1
  42     #define CCS_ADDRESS_WRITE       0x01 // 0: read, 1:write
  43
  44
  45 #define CCS_I2C_ADDR            0x0011   // byte address to read/write
  46 #define CCS_I2C_DATA            0x0012
  47 #define CCS_I2C_STATUS          0X0013
  48     #define CCS_I2C_EPROM           0x80 // 1: E2PROM connected
  49     #define CCS_I2C_BUSY            0x01 // 0: idle, 1: busy
  50
  51
  52 #define CCS_CONS_REC_ADDRESS    0x0014
  53 #define CCS_CONS_REC_LENGTH     0x0018
  54
  55
  56 #define CCS_MIDI2_DATA          0x001C
  57 #define CCS_MIDI2_CMD_STATUS    0x001D
  58
  59 #define CCS_TIMER               0x001E // word
  60     #define CCS_TIMER_ENABLE        0x8000
  61     #define CCS_TIMER_MASK          0x7FFF // bits 0 - 14: write to set up the period for the internal 15 bits timer to generate an interrupt
  62
  63
  64 #define CCI_GPIO_DATA           0x20
  65 #define CCI_GPIO_MASK           0x21 // 0 in mask means CCI_GPIO_DATA register bit can be written
  66 #define CCI_GPIO_DIR            0x22 // 1 = output
  67
  68 #define CCI_CONS_POWER_DOWN     0x30
  69 #define CCI_PRO_POWER_DOWN      0x31
  70
  71
  72
  73
  74 // ----------MT regs-------------------
  75
  76 #define MT_INTR_MASK_STATUS     0x0000
  77     #define MT_REC_MASK             0x80
  78     #define MT_PLAY_MASK            0x40
  79     #define MT_REC_STATUS           0x02
  80     #define MT_PLAY_STATUS          0x01
  81
  82 #define MT_SAMPLERATE           0x0001   // in slave mode (SPDIF is master): 256X master clock alone selects rate
  83     #define MT_SPDIF_MASTER         0x10 //
  84     #define MT_RATE_MASK            0x0F // ignored if MT_SPDIF_MASTER =
  85
  86 #define MT_I2S_FORMAT           0x0002
  87     #define MT_CLOCK_128x           0x08 // 0: 256x (default), 1: 128x
  88     #define MT_CLOCK_48bpf          0x04 // 0: 256x (default), 1: 128x
  89
  90 #define MT_AC97_REG             0x0004 // AC'97 register index
  91 #define MT_AC97_CMD_STATUS      0x0005 // valid when CCS_ACLINK_TYPE == 0
  92     #define MT_AC97_RESET           0x80 // cold reset (alone will put it into master mode)
  93     #define MT_AC97_WARM_RESET      0X40 // when used together with MT_AC97_RESET, will set external VIA AC'97 to slave mode
  94     #define MT_AC97_WRITE           0X20 // write 1 for write mode, reading a 1 is WIP
  95     #define MT_AC97_READ            0x10 // write 1 for read mode, reading a 1 is RIP
  96     #define MT_AC97_READY           0x08 // codec ready status
  97     #define MT_AC97_ID_MASK         0x03 // bit 0:1 is ID mode when is split mode.
  98 #define MT_AC97_DATA            0x0006
  99
 100
 101 #define MT_DMA_PB_ADDRESS       0x0010 // long: start address of interleaved playback buffer (long boundary), in long units
 102 #define MT_DMA_PB_LENGTH        0x0014 // word: DMA size - 1, read: counter
 103 #define MT_DMA_PB_INTLEN        0x0016
 104
 105 #define MT_DMA_CONTROL          0x0018 // start/stop (use read-modify-write)
 106     #define MT_REC_START             0x04
 107     #define MT_PAUSE                 0x02
 108     #define MT_PLAY_START            0x01
 109
 110
 111 // record pair registers
 112 #define MT_DMA_REC_ADDRESS      0x0020
 113 #define MT_DMA_REC_LENGTH       0x0024
 114 #define MT_DMA_REC_INTLEN       0x0026
 115
 116
 117 #define ICE1712_DELTA_DFS 0x01          /* fast/slow sample rate mode */
 118 #define ICE1712_DELTA_AP_CCLK   0x02    /* SPI clock */
 119                                         /* (clocking on rising edge - 0->1) */
 120 #define ICE1712_DELTA_AP_DIN    0x04    /* data input */
 121 #define ICE1712_DELTA_AP_DOUT   0x08    /* data output */
 122 #define ICE1712_DELTA_AP_CS_DIGITAL 0x10 /* CS8427 chip select */
 123                                         /* low signal = select */
 124 #define ICE1712_DELTA_AP_CS_CODEC 0x20  /* AK4528 (audiophile), AK4529 (Delta410) chip select */
 125                                         /* low signal = select */
 126
 127
 128 /* 0x01 = DFS */
 129 #define ICE1712_DELTA_1010LT_CCLK       0x02    /* SPI clock (AK4524 + CS8427) */
 130 #define ICE1712_DELTA_1010LT_DIN        0x04    /* data input (CS8427) */
 131 #define ICE1712_DELTA_1010LT_DOUT       0x08    /* data output (AK4524 + CS8427) */
 132 #define ICE1712_DELTA_1010LT_CS         0x70    /* mask for CS address */
 133 #define ICE1712_DELTA_1010LT_CS_CHIP_A  0x00    /* AK4524 #0 */
 134 #define ICE1712_DELTA_1010LT_CS_CHIP_B  0x10    /* AK4524 #1 */
 135 #define ICE1712_DELTA_1010LT_CS_CHIP_C  0x20    /* AK4524 #2 */
 136 #define ICE1712_DELTA_1010LT_CS_CHIP_D  0x30    /* AK4524 #3 */
 137 #define ICE1712_DELTA_1010LT_CS_CS8427  0x40    /* CS8427 */
 138 #define ICE1712_DELTA_1010LT_CS_NONE    0x50    /* nothing */
 139 #define ICE1712_DELTA_1010LT_WORDCLOCK 0x80     /* sample clock source: 0 = Word Clock Input, 1 = S/PDIF Input ??? */
 140
 141
 142
 143
 144 #endif /* _REGS_H */