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Check for SYS/GL during library init. Reason is that
[AROS.git] / workbench / devs / networks / atheros5000 / hal / ah_internal.h
blobe07727ee5a138bb984366abb58652bcd75c172fa
1 /*
2 * Copyright (c) 2002-2008 Sam Leffler, Errno Consulting
3 * Copyright (c) 2002-2008 Atheros Communications, Inc.
4 *
5 * Permission to use, copy, modify, and/or distribute this software for any
6 * purpose with or without fee is hereby granted, provided that the above
7 * copyright notice and this permission notice appear in all copies.
8 *
9 * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
10 * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
11 * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
12 * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
13 * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
14 * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF
15 * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
16 *
17 * $Id$
18 */
19 #ifndef _ATH_AH_INTERAL_H_
20 #define _ATH_AH_INTERAL_H_
21 /*
22 * Atheros Device Hardware Access Layer (HAL).
23 *
24 * Internal definitions.
25 */
26 #define AH_NULL 0
27 #define AH_MIN(a,b) ((a)<(b)?(a):(b))
28 #define AH_MAX(a,b) ((a)>(b)?(a):(b))
29
30 #ifndef NBBY
31 #define NBBY 8 /* number of bits/byte */
32 #endif
33
34 #ifndef roundup
35 #define roundup(x, y) ((((x)+((y)-1))/(y))*(y)) /* to any y */
36 #endif
37 #ifndef howmany
38 #define howmany(x, y) (((x)+((y)-1))/(y))
39 #endif
40
41 #ifndef offsetof
42 #define offsetof(type, field) ((size_t)(&((type *)0)->field))
43 #endif
44
45 /*
46 * Remove const in a way that keeps the compiler happy.
47 * This works for gcc but may require other magic for
48 * other compilers (not sure where this should reside).
49 * Note that uintptr_t is C99.
50 */
51 #ifndef __DECONST
52 #ifndef _UINTPTR_T
53 #if AH_WORDSIZE == 64
54 typedef unsigned long int uintptr_t;
55 #else
56 typedef unsigned int uintptr_t;
57 #endif
58 #endif
59 #define __DECONST(type, var) ((type)(uintptr_t)(const void *)(var))
60 #endif
61
62 typedef struct {
63 uint16_t start; /* first register */
64 uint16_t end; /* ending register or zero */
65 } HAL_REGRANGE;
66
67 /*
68 * Transmit power scale factor.
69 */
70 typedef enum {
71 HAL_TP_SCALE_MAX = 0, /* no scaling (default) */
72 HAL_TP_SCALE_50 = 1, /* 50% of max (-3 dBm) */
73 HAL_TP_SCALE_25 = 2, /* 25% of max (-6 dBm) */
74 HAL_TP_SCALE_12 = 3, /* 12% of max (-9 dBm) */
75 HAL_TP_SCALE_MIN = 4, /* min, but still on */
76 } HAL_TP_SCALE;
77
78 typedef enum {
79 HAL_CAP_RADAR = 0, /* Radar capability */
80 HAL_CAP_AR = 1, /* AR capability */
81 } HAL_PHYDIAG_CAPS;
82
83
84 /*
85 * Internal form of a HAL_CHANNEL. Note that the structure
86 * must be defined such that you can cast references to a
87 * HAL_CHANNEL so don't shuffle the first two members.
88 */
89 typedef struct {
90 uint32_t channelFlags;
91 uint16_t channel; /* NB: must be first for casting */
92 uint8_t privFlags;
93 int8_t maxRegTxPower;
94 int8_t maxTxPower;
95 int8_t minTxPower; /* as above... */
96
97 HAL_BOOL bssSendHere;
98 uint8_t gainI;
99 HAL_BOOL iqCalValid;
100 uint8_t calValid; /* bitmask of cal types */
101 int8_t iCoff;
102 int8_t qCoff;
103 int16_t rawNoiseFloor;
104 int16_t noiseFloorAdjust;
105 int8_t antennaMax;
106 uint32_t regDmnFlags; /* Flags for channel use in reg */
107 uint32_t conformanceTestLimit; /* conformance test limit from reg domain */
108 uint16_t mainSpur; /* cached spur value for this cahnnel */
109 } HAL_CHANNEL_INTERNAL;
110
111 typedef struct {
112 uint32_t halChanSpreadSupport : 1,
113 halSleepAfterBeaconBroken : 1,
114 halCompressSupport : 1,
115 halBurstSupport : 1,
116 halFastFramesSupport : 1,
117 halChapTuningSupport : 1,
118 halTurboGSupport : 1,
119 halTurboPrimeSupport : 1,
120 halMicAesCcmSupport : 1,
121 halMicCkipSupport : 1,
122 halMicTkipSupport : 1,
123 halTkipMicTxRxKeySupport : 1,
124 halCipherAesCcmSupport : 1,
125 halCipherCkipSupport : 1,
126 halCipherTkipSupport : 1,
127 halPSPollBroken : 1,
128 halVEOLSupport : 1,
129 halBssIdMaskSupport : 1,
130 halMcastKeySrchSupport : 1,
131 halTsfAddSupport : 1,
132 halChanHalfRate : 1,
133 halChanQuarterRate : 1,
134 halHTSupport : 1,
135 halRfSilentSupport : 1,
136 halHwPhyCounterSupport : 1,
137 halWowSupport : 1,
138 halWowMatchPatternExact : 1,
139 halAutoSleepSupport : 1,
140 halFastCCSupport : 1,
141 halBtCoexSupport : 1;
142 uint32_t halRxStbcSupport : 1,
143 halTxStbcSupport : 1,
144 halGTTSupport : 1,
145 halCSTSupport : 1,
146 halRifsRxSupport : 1,
147 halRifsTxSupport : 1,
148 halExtChanDfsSupport : 1,
149 halForcePpmSupport : 1,
150 halEnhancedPmSupport : 1,
151 halMbssidAggrSupport : 1;
152 uint32_t halWirelessModes;
153 uint16_t halTotalQueues;
154 uint16_t halKeyCacheSize;
155 uint16_t halLow5GhzChan, halHigh5GhzChan;
156 uint16_t halLow2GhzChan, halHigh2GhzChan;
157 int halTstampPrecision;
158 int halRtsAggrLimit;
159 uint8_t halTxChainMask;
160 uint8_t halRxChainMask;
161 uint8_t halNumGpioPins;
162 uint8_t halNumAntCfg2GHz;
163 uint8_t halNumAntCfg5GHz;
164 } HAL_CAPABILITIES;
165
166 /*
167 * The ``private area'' follows immediately after the ``public area''
168 * in the data structure returned by ath_hal_attach.
169 */
170 struct ath_hal_private {
171 struct ath_hal h; /* public area */
172
173 /* NB: all methods go first to simplify initialization */
174 HAL_BOOL (*ah_getChannelEdges)(struct ath_hal*,
175 uint16_t channelFlags,
176 uint16_t *lowChannel, uint16_t *highChannel);
177 u_int (*ah_getWirelessModes)(struct ath_hal*);
178 HAL_BOOL (*ah_eepromRead)(struct ath_hal *, u_int off,
179 uint16_t *data);
180 HAL_BOOL (*ah_eepromWrite)(struct ath_hal *, u_int off,
181 uint16_t data);
182 HAL_BOOL (*ah_gpioCfgOutput)(struct ath_hal *, uint32_t gpio);
183 HAL_BOOL (*ah_gpioCfgInput)(struct ath_hal *, uint32_t gpio);
184 uint32_t (*ah_gpioGet)(struct ath_hal *, uint32_t gpio);
185 HAL_BOOL (*ah_gpioSet)(struct ath_hal *,
186 uint32_t gpio, uint32_t val);
187 void (*ah_gpioSetIntr)(struct ath_hal*, u_int, uint32_t);
188 HAL_BOOL (*ah_getChipPowerLimits)(struct ath_hal *,
189 HAL_CHANNEL *, uint32_t);
190 int16_t (*ah_getNfAdjust)(struct ath_hal *,
191 const HAL_CHANNEL_INTERNAL*);
192
193 void *ah_eeprom; /* opaque EEPROM state */
194 uint16_t ah_eeversion; /* EEPROM version */
195 void (*ah_eepromDetach)(struct ath_hal *);
196 HAL_STATUS (*ah_eepromGet)(struct ath_hal *, int, void *);
197 HAL_BOOL (*ah_eepromSet)(struct ath_hal *, int, int);
198 uint16_t (*ah_getSpurChan)(struct ath_hal *, int, HAL_BOOL);
199 HAL_BOOL (*ah_eepromDiag)(struct ath_hal *, int request,
200 const void *args, uint32_t argsize,
201 void **result, uint32_t *resultsize);
202
203 /*
204 * Device revision information.
205 */
206 uint16_t ah_devid; /* PCI device ID */
207 uint16_t ah_subvendorid; /* PCI subvendor ID */
208 uint32_t ah_macVersion; /* MAC version id */
209 uint16_t ah_macRev; /* MAC revision */
210 uint16_t ah_phyRev; /* PHY revision */
211 uint16_t ah_analog5GhzRev; /* 2GHz radio revision */
212 uint16_t ah_analog2GhzRev; /* 5GHz radio revision */
213
214
215 HAL_OPMODE ah_opmode; /* operating mode from reset */
216 HAL_CAPABILITIES ah_caps; /* device capabilities */
217 uint32_t ah_diagreg; /* user-specified AR_DIAG_SW */
218 int16_t ah_powerLimit; /* tx power cap */
219 uint16_t ah_maxPowerLevel; /* calculated max tx power */
220 u_int ah_tpScale; /* tx power scale factor */
221 uint32_t ah_11nCompat; /* 11n compat controls */
222
223 /*
224 * State for regulatory domain handling.
225 */
226 HAL_REG_DOMAIN ah_currentRD; /* Current regulatory domain */
227 HAL_CTRY_CODE ah_countryCode; /* current country code */
228 HAL_CHANNEL_INTERNAL ah_channels[256]; /* calculated channel list */
229 u_int ah_nchan; /* valid channels in list */
230 HAL_CHANNEL_INTERNAL *ah_curchan; /* current channel */
231
232 uint8_t ah_coverageClass; /* coverage class */
233 HAL_BOOL ah_regdomainUpdate; /* regdomain is updated? */
234 /*
235 * RF Silent handling; setup according to the EEPROM.
236 */
237 uint16_t ah_rfsilent; /* GPIO pin + polarity */
238 HAL_BOOL ah_rfkillEnabled; /* enable/disable RfKill */
239 /*
240 * Diagnostic support for discriminating HIUERR reports.
241 */
242 uint32_t ah_fatalState[6]; /* AR_ISR+shadow regs */
243 int ah_rxornIsFatal; /* how to treat HAL_INT_RXORN */
244 };
245
246 #define AH_PRIVATE(_ah) ((struct ath_hal_private *)(_ah))
247
248 #define ath_hal_getChannelEdges(_ah, _cf, _lc, _hc) \
249 AH_PRIVATE(_ah)->ah_getChannelEdges(_ah, _cf, _lc, _hc)
250 #define ath_hal_getWirelessModes(_ah) \
251 AH_PRIVATE(_ah)->ah_getWirelessModes(_ah)
252 #define ath_hal_eepromRead(_ah, _off, _data) \
253 AH_PRIVATE(_ah)->ah_eepromRead(_ah, _off, _data)
254 #define ath_hal_eepromWrite(_ah, _off, _data) \
255 AH_PRIVATE(_ah)->ah_eepromWrite(_ah, _off, _data)
256 #define ath_hal_gpioCfgOutput(_ah, _gpio) \
257 AH_PRIVATE(_ah)->ah_gpioCfgOutput(_ah, _gpio)
258 #define ath_hal_gpioCfgInput(_ah, _gpio) \
259 AH_PRIVATE(_ah)->ah_gpioCfgInput(_ah, _gpio)
260 #define ath_hal_gpioGet(_ah, _gpio) \
261 AH_PRIVATE(_ah)->ah_gpioGet(_ah, _gpio)
262 #define ath_hal_gpioSet(_ah, _gpio, _val) \
263 AH_PRIVATE(_ah)->ah_gpioGet(_ah, _gpio, _val)
264 #define ath_hal_gpioSetIntr(_ah, _gpio, _ilevel) \
265 AH_PRIVATE(_ah)->ah_gpioSetIntr(_ah, _gpio, _ilevel)
266 #define ath_hal_getpowerlimits(_ah, _chans, _nchan) \
267 AH_PRIVATE(_ah)->ah_getChipPowerLimits(_ah, _chans, _nchan)
268 #define ath_hal_getNfAdjust(_ah, _c) \
269 AH_PRIVATE(_ah)->ah_getNfAdjust(_ah, _c)
270
271 #define ath_hal_eepromDetach(_ah) \
272 AH_PRIVATE(_ah)->ah_eepromDetach(_ah)
273 #define ath_hal_eepromGet(_ah, _param, _val) \
274 AH_PRIVATE(_ah)->ah_eepromGet(_ah, _param, _val)
275 #define ath_hal_eepromSet(_ah, _param, _val) \
276 AH_PRIVATE(_ah)->ah_eepromSet(_ah, _param, _val)
277 #define ath_hal_eepromGetFlag(_ah, _param) \
278 (AH_PRIVATE(_ah)->ah_eepromGet(_ah, _param, AH_NULL) == HAL_OK)
279 #define ath_hal_getSpurChan(_ah, _ix, _is2G) \
280 AH_PRIVATE(_ah)->ah_getSpurChan(_ah, _ix, _is2G)
281 #define ath_hal_eepromDiag(_ah, _request, _a, _asize, _r, _rsize) \
282 AH_PRIVATE(_ah)->ah_eepromDiag(_ah, _request, _a, _asize, _r, _rsize)
283
284 #if !defined(_NET_IF_IEEE80211_H_) && !defined(_NET80211__IEEE80211_H_)
285 /*
286 * Stuff that would naturally come from _ieee80211.h
287 */
288 #define IEEE80211_ADDR_LEN 6
289
290 #define IEEE80211_WEP_KEYLEN 5 /* 40bit */
291 #define IEEE80211_WEP_IVLEN 3 /* 24bit */
292 #define IEEE80211_WEP_KIDLEN 1 /* 1 octet */
293 #define IEEE80211_WEP_CRCLEN 4 /* CRC-32 */
294
295 #define IEEE80211_CRC_LEN 4
296
297 #define IEEE80211_MTU 1500
298 #define IEEE80211_MAX_LEN (2300 + IEEE80211_CRC_LEN + \
299 (IEEE80211_WEP_IVLEN + IEEE80211_WEP_KIDLEN + IEEE80211_WEP_CRCLEN))
300
301 enum {
302 IEEE80211_T_DS, /* direct sequence spread spectrum */
303 IEEE80211_T_FH, /* frequency hopping */
304 IEEE80211_T_OFDM, /* frequency division multiplexing */
305 IEEE80211_T_TURBO, /* high rate DS */
306 IEEE80211_T_HT, /* HT - full GI */
307 };
308 #define IEEE80211_T_CCK IEEE80211_T_DS /* more common nomenclatur */
309 #endif /* _NET_IF_IEEE80211_H_ */
310
311 /* NB: these are defined privately until XR support is announced */
312 enum {
313 ATHEROS_T_XR = IEEE80211_T_HT+1, /* extended range */
314 };
315
316 #define HAL_TXQ_USE_LOCKOUT_BKOFF_DIS 0x00000001
317
318 #define INIT_AIFS 2
319 #define INIT_CWMIN 15
320 #define INIT_CWMIN_11B 31
321 #define INIT_CWMAX 1023
322 #define INIT_SH_RETRY 10
323 #define INIT_LG_RETRY 10
324 #define INIT_SSH_RETRY 32
325 #define INIT_SLG_RETRY 32
326
327 typedef struct {
328 uint32_t tqi_ver; /* HAL TXQ verson */
329 HAL_TX_QUEUE tqi_type; /* hw queue type*/
330 HAL_TX_QUEUE_SUBTYPE tqi_subtype; /* queue subtype, if applicable */
331 HAL_TX_QUEUE_FLAGS tqi_qflags; /* queue flags */
332 uint32_t tqi_priority;
333 uint32_t tqi_aifs; /* aifs */
334 uint32_t tqi_cwmin; /* cwMin */
335 uint32_t tqi_cwmax; /* cwMax */
336 uint16_t tqi_shretry; /* frame short retry limit */
337 uint16_t tqi_lgretry; /* frame long retry limit */
338 uint32_t tqi_cbrPeriod;
339 uint32_t tqi_cbrOverflowLimit;
340 uint32_t tqi_burstTime;
341 uint32_t tqi_readyTime;
342 uint32_t tqi_physCompBuf;
343 uint32_t tqi_intFlags; /* flags for internal use */
344 } HAL_TX_QUEUE_INFO;
345
346 extern HAL_BOOL ath_hal_setTxQProps(struct ath_hal *ah,
347 HAL_TX_QUEUE_INFO *qi, const HAL_TXQ_INFO *qInfo);
348 extern HAL_BOOL ath_hal_getTxQProps(struct ath_hal *ah,
349 HAL_TXQ_INFO *qInfo, const HAL_TX_QUEUE_INFO *qi);
350
351 typedef enum {
352 HAL_ANI_PRESENT, /* is ANI support present */
353 HAL_ANI_NOISE_IMMUNITY_LEVEL, /* set level */
354 HAL_ANI_OFDM_WEAK_SIGNAL_DETECTION, /* enable/disable */
355 HAL_ANI_CCK_WEAK_SIGNAL_THR, /* enable/disable */
356 HAL_ANI_FIRSTEP_LEVEL, /* set level */
357 HAL_ANI_SPUR_IMMUNITY_LEVEL, /* set level */
358 HAL_ANI_MODE = 6, /* 0 => manual, 1 => auto (XXX do not change) */
359 HAL_ANI_PHYERR_RESET, /* reset phy error stats */
360 } HAL_ANI_CMD;
361
362 #define HAL_SPUR_VAL_MASK 0x3FFF
363 #define HAL_SPUR_CHAN_WIDTH 87
364 #define HAL_BIN_WIDTH_BASE_100HZ 3125
365 #define HAL_BIN_WIDTH_TURBO_100HZ 6250
366 #define HAL_MAX_BINS_ALLOWED 28
367
368 /*
369 * A = 5GHZ|OFDM
370 * T = 5GHZ|OFDM|TURBO
371 *
372 * IS_CHAN_A(T) will return TRUE. This is probably
373 * not the default behavior we want. We should migrate to a better mask --
374 * perhaps CHANNEL_ALL.
375 *
376 * For now, IS_CHAN_G() masks itself with CHANNEL_108G.
377 *
378 */
379
380 #define IS_CHAN_A(_c) (((_c)->channelFlags & CHANNEL_A) == CHANNEL_A)
381 #define IS_CHAN_B(_c) (((_c)->channelFlags & CHANNEL_B) == CHANNEL_B)
382 #define IS_CHAN_G(_c) (((_c)->channelFlags & (CHANNEL_108G|CHANNEL_G)) == CHANNEL_G)
383 #define IS_CHAN_108G(_c)(((_c)->channelFlags & CHANNEL_108G) == CHANNEL_108G)
384 #define IS_CHAN_T(_c) (((_c)->channelFlags & CHANNEL_T) == CHANNEL_T)
385 #define IS_CHAN_PUREG(_c) \
386 (((_c)->channelFlags & CHANNEL_PUREG) == CHANNEL_PUREG)
387
388 #define IS_CHAN_TURBO(_c) (((_c)->channelFlags & CHANNEL_TURBO) != 0)
389 #define IS_CHAN_CCK(_c) (((_c)->channelFlags & CHANNEL_CCK) != 0)
390 #define IS_CHAN_OFDM(_c) (((_c)->channelFlags & CHANNEL_OFDM) != 0)
391 #define IS_CHAN_5GHZ(_c) (((_c)->channelFlags & CHANNEL_5GHZ) != 0)
392 #define IS_CHAN_2GHZ(_c) (((_c)->channelFlags & CHANNEL_2GHZ) != 0)
393 #define IS_CHAN_PASSIVE(_c) (((_c)->channelFlags & CHANNEL_PASSIVE) != 0)
394 #define IS_CHAN_HALF_RATE(_c) (((_c)->channelFlags & CHANNEL_HALF) != 0)
395 #define IS_CHAN_QUARTER_RATE(_c) (((_c)->channelFlags & CHANNEL_QUARTER) != 0)
396
397 #define IS_CHAN_IN_PUBLIC_SAFETY_BAND(_c) ((_c) > 4940 && (_c) < 4990)
398
399 #define CHANNEL_HT40 (CHANNEL_HT40PLUS | CHANNEL_HT40MINUS)
400 #define CHANNEL_HT (CHANNEL_HT20 | CHANNEL_HT40)
401 #define IS_CHAN_HT(_c) (((_c)->channelFlags & CHANNEL_HT) != 0)
402 #define IS_CHAN_HT20(_c) (((_c)->channelFlags & CHANNEL_HT) == CHANNEL_HT20)
403 #define IS_CHAN_HT40(_c) (((_c)->channelFlags & CHANNEL_HT40) != 0)
404
405 /*
406 * Deduce if the host cpu has big- or litt-endian byte order.
407 */
408 static __inline__ int
409 isBigEndian(void)
410 {
411 union {
412 int32_t i;
413 char c[4];
414 } u;
415 u.i = 1;
416 return (u.c[0] == 0);
417 }
418
419 /* unalligned little endian access */
420 #define LE_READ_2(p) \
421 ((uint16_t) \
422 ((((const uint8_t *)(p))[0] ) | (((const uint8_t *)(p))[1]<< 8)))
423 #define LE_READ_4(p) \
424 ((uint32_t) \
425 ((((const uint8_t *)(p))[0] ) | (((const uint8_t *)(p))[1]<< 8) |\
426 (((const uint8_t *)(p))[2]<<16) | (((const uint8_t *)(p))[3]<<24)))
427
428 /*
429 * Register manipulation macros that expect bit field defines
430 * to follow the convention that an _S suffix is appended for
431 * a shift count, while the field mask has no suffix.
432 */
433 #define SM(_v, _f) (((_v) << _f##_S) & (_f))
434 #define MS(_v, _f) (((_v) & (_f)) >> _f##_S)
435 #define OS_REG_RMW_FIELD(_a, _r, _f, _v) \
436 OS_REG_WRITE(_a, _r, \
437 (OS_REG_READ(_a, _r) &~ (_f)) | (((_v) << _f##_S) & (_f)))
438 #define OS_REG_SET_BIT(_a, _r, _f) \
439 OS_REG_WRITE(_a, _r, OS_REG_READ(_a, _r) | (_f))
440 #define OS_REG_CLR_BIT(_a, _r, _f) \
441 OS_REG_WRITE(_a, _r, OS_REG_READ(_a, _r) &~ (_f))
442
443 /*
444 * Regulatory domain support.
445 */
446
447 /*
448 * Return the max allowed antenna gain based on the current
449 * regulatory domain.
450 */
451 extern u_int ath_hal_getantennareduction(struct ath_hal *,
452 HAL_CHANNEL *, u_int twiceGain);
453 /*
454 * Return the test group for the specific channel based on
455 * the current regulator domain.
456 */
457 extern u_int ath_hal_getctl(struct ath_hal *, HAL_CHANNEL *);
458 /*
459 * Return whether or not a noise floor check is required
460 * based on the current regulatory domain for the specified
461 * channel.
462 */
463 extern u_int ath_hal_getnfcheckrequired(struct ath_hal *, HAL_CHANNEL *);
464
465 /*
466 * Map a public channel definition to the corresponding
467 * internal data structure. This implicitly specifies
468 * whether or not the specified channel is ok to use
469 * based on the current regulatory domain constraints.
470 */
471 extern HAL_CHANNEL_INTERNAL *ath_hal_checkchannel(struct ath_hal *,
472 const HAL_CHANNEL *);
473
474 /* system-configurable parameters */
475 extern int ath_hal_dma_beacon_response_time; /* in TU's */
476 extern int ath_hal_sw_beacon_response_time; /* in TU's */
477 extern int ath_hal_additional_swba_backoff; /* in TU's */
478
479 /* wait for the register contents to have the specified value */
480 extern HAL_BOOL ath_hal_wait(struct ath_hal *, u_int reg,
481 uint32_t mask, uint32_t val);
482
483 /* return the first n bits in val reversed */
484 extern uint32_t ath_hal_reverseBits(uint32_t val, uint32_t n);
485
486 /* printf interfaces */
487 extern void ath_hal_printf(struct ath_hal *, const char*, ...)
488 __printflike(2,3);
489 extern void ath_hal_vprintf(struct ath_hal *, const char*, __va_list)
490 __printflike(2, 0);
491 extern const char* ath_hal_ether_sprintf(const uint8_t *mac);
492
493 /* allocate and free memory */
494 extern void *ath_hal_malloc(size_t);
495 extern void ath_hal_free(void *);
496
497 /* common debugging interfaces */
498 #ifdef AH_DEBUG
499 #include "ah_debug.h"
500 extern int ath_hal_debug;
501 extern void HALDEBUG(struct ath_hal *ah, u_int mask, const char* fmt, ...)
502 __printflike(3,4);
503 #else
504 #define HALDEBUG(_ah, __m, _fmt, ...)
505 #endif /* AH_DEBUG */
506
507 /*
508 * Register logging definitions shared with ardecode.
509 */
510 #include "ah_decode.h"
511
512 /*
513 * Common assertion interface. Note: it is a bad idea to generate
514 * an assertion failure for any recoverable event. Instead catch
515 * the violation and, if possible, fix it up or recover from it; either
516 * with an error return value or a diagnostic messages. System software
517 * does not panic unless the situation is hopeless.
518 */
519 #ifdef AH_ASSERT
520 extern void ath_hal_assert_failed(const char* filename,
521 int lineno, const char* msg);
522
523 #define HALASSERT(_x) do { \
524 if (!(_x)) { \
525 ath_hal_assert_failed(__FILE__, __LINE__, #_x); \
526 } \
527 } while (0)
528 #else
529 #define HALASSERT(_x)
530 #endif /* AH_ASSERT */
531
532 /*
533 * Convert between microseconds and core system clocks.
534 */
535 extern u_int ath_hal_mac_clks(struct ath_hal *ah, u_int usecs);
536 extern u_int ath_hal_mac_usec(struct ath_hal *ah, u_int clks);
537
538 /*
539 * Generic get/set capability support. Each chip overrides
540 * this routine to support chip-specific capabilities.
541 */
542 extern HAL_STATUS ath_hal_getcapability(struct ath_hal *ah,
543 HAL_CAPABILITY_TYPE type, uint32_t capability,
544 uint32_t *result);
545 extern HAL_BOOL ath_hal_setcapability(struct ath_hal *ah,
546 HAL_CAPABILITY_TYPE type, uint32_t capability,
547 uint32_t setting, HAL_STATUS *status);
548
549 /*
550 * Diagnostic interface. This is an open-ended interface that
551 * is opaque to applications. Diagnostic programs use this to
552 * retrieve internal data structures, etc. There is no guarantee
553 * that calling conventions for calls other than HAL_DIAG_REVS
554 * are stable between HAL releases; a diagnostic application must
555 * use the HAL revision information to deal with ABI/API differences.
556 *
557 * NB: do not renumber these, certain codes are publicly used.
558 */
559 enum {
560 HAL_DIAG_REVS = 0, /* MAC/PHY/Radio revs */
561 HAL_DIAG_EEPROM = 1, /* EEPROM contents */
562 HAL_DIAG_EEPROM_EXP_11A = 2, /* EEPROM 5112 power exp for 11a */
563 HAL_DIAG_EEPROM_EXP_11B = 3, /* EEPROM 5112 power exp for 11b */
564 HAL_DIAG_EEPROM_EXP_11G = 4, /* EEPROM 5112 power exp for 11g */
565 HAL_DIAG_ANI_CURRENT = 5, /* ANI current channel state */
566 HAL_DIAG_ANI_OFDM = 6, /* ANI OFDM timing error stats */
567 HAL_DIAG_ANI_CCK = 7, /* ANI CCK timing error stats */
568 HAL_DIAG_ANI_STATS = 8, /* ANI statistics */
569 HAL_DIAG_RFGAIN = 9, /* RfGain GAIN_VALUES */
570 HAL_DIAG_RFGAIN_CURSTEP = 10, /* RfGain GAIN_OPTIMIZATION_STEP */
571 HAL_DIAG_PCDAC = 11, /* PCDAC table */
572 HAL_DIAG_TXRATES = 12, /* Transmit rate table */
573 HAL_DIAG_REGS = 13, /* Registers */
574 HAL_DIAG_ANI_CMD = 14, /* ANI issue command (XXX do not change!) */
575 HAL_DIAG_SETKEY = 15, /* Set keycache backdoor */
576 HAL_DIAG_RESETKEY = 16, /* Reset keycache backdoor */
577 HAL_DIAG_EEREAD = 17, /* Read EEPROM word */
578 HAL_DIAG_EEWRITE = 18, /* Write EEPROM word */
579 /* 19 was HAL_DIAG_TXCONT, 20-23 were for radar */
580 HAL_DIAG_REGREAD = 24, /* Reg reads */
581 HAL_DIAG_REGWRITE = 25, /* Reg writes */
582 HAL_DIAG_GET_REGBASE = 26, /* Get register base */
583 HAL_DIAG_RDWRITE = 27, /* Write regulatory domain */
584 HAL_DIAG_RDREAD = 28, /* Get regulatory domain */
585 HAL_DIAG_FATALERR = 29, /* Read cached interrupt state */
586 HAL_DIAG_11NCOMPAT = 30, /* 11n compatibility tweaks */
587 HAL_DIAG_ANI_PARAMS = 31, /* ANI noise immunity parameters */
588 HAL_DIAG_CHECK_HANGS = 32, /* check h/w hangs */
589 };
590
591 enum {
592 HAL_BB_HANG_DFS = 0x0001,
593 HAL_BB_HANG_RIFS = 0x0002,
594 HAL_BB_HANG_RX_CLEAR = 0x0004,
595 HAL_BB_HANG_UNKNOWN = 0x0080,
596
597 HAL_MAC_HANG_SIG1 = 0x0100,
598 HAL_MAC_HANG_SIG2 = 0x0200,
599 HAL_MAC_HANG_UNKNOWN = 0x8000,
600
601 HAL_BB_HANGS = HAL_BB_HANG_DFS
602 | HAL_BB_HANG_RIFS
603 | HAL_BB_HANG_RX_CLEAR
604 | HAL_BB_HANG_UNKNOWN,
605 HAL_MAC_HANGS = HAL_MAC_HANG_SIG1
606 | HAL_MAC_HANG_SIG2
607 | HAL_MAC_HANG_UNKNOWN,
608 };
609
610 /*
611 * Device revision information.
612 */
613 typedef struct {
614 uint16_t ah_devid; /* PCI device ID */
615 uint16_t ah_subvendorid; /* PCI subvendor ID */
616 uint32_t ah_macVersion; /* MAC version id */
617 uint16_t ah_macRev; /* MAC revision */
618 uint16_t ah_phyRev; /* PHY revision */
619 uint16_t ah_analog5GhzRev; /* 2GHz radio revision */
620 uint16_t ah_analog2GhzRev; /* 5GHz radio revision */
621 } HAL_REVS;
622
623 /*
624 * Argument payload for HAL_DIAG_SETKEY.
625 */
626 typedef struct {
627 HAL_KEYVAL dk_keyval;
628 uint16_t dk_keyix; /* key index */
629 uint8_t dk_mac[IEEE80211_ADDR_LEN];
630 int dk_xor; /* XOR key data */
631 } HAL_DIAG_KEYVAL;
632
633 /*
634 * Argument payload for HAL_DIAG_EEWRITE.
635 */
636 typedef struct {
637 uint16_t ee_off; /* eeprom offset */
638 uint16_t ee_data; /* write data */
639 } HAL_DIAG_EEVAL;
640
641
642 typedef struct {
643 u_int offset; /* reg offset */
644 uint32_t val; /* reg value */
645 } HAL_DIAG_REGVAL;
646
647 /*
648 * 11n compatibility tweaks.
649 */
650 #define HAL_DIAG_11N_SERVICES 0x00000003
651 #define HAL_DIAG_11N_SERVICES_S 0
652 #define HAL_DIAG_11N_TXSTOMP 0x0000000c
653 #define HAL_DIAG_11N_TXSTOMP_S 2
654
655 typedef struct {
656 int maxNoiseImmunityLevel; /* [0..4] */
657 int totalSizeDesired[5];
658 int coarseHigh[5];
659 int coarseLow[5];
660 int firpwr[5];
661
662 int maxSpurImmunityLevel; /* [0..7] */
663 int cycPwrThr1[8];
664
665 int maxFirstepLevel; /* [0..2] */
666 int firstep[3];
667
668 uint32_t ofdmTrigHigh;
669 uint32_t ofdmTrigLow;
670 int32_t cckTrigHigh;
671 int32_t cckTrigLow;
672 int32_t rssiThrLow;
673 int32_t rssiThrHigh;
674
675 int period; /* update listen period */
676 } HAL_ANI_PARAMS;
677
678 extern HAL_BOOL ath_hal_getdiagstate(struct ath_hal *ah, int request,
679 const void *args, uint32_t argsize,
680 void **result, uint32_t *resultsize);
681
682 /*
683 * Setup a h/w rate table for use.
684 */
685 extern void ath_hal_setupratetable(struct ath_hal *ah, HAL_RATE_TABLE *rt);
686
687 /*
688 * Common routine for implementing getChanNoise api.
689 */
690 extern int16_t ath_hal_getChanNoise(struct ath_hal *ah, HAL_CHANNEL *chan);
691
692 /*
693 * Initialization support.
694 */
695 typedef struct {
696 const uint32_t *data;
697 int rows, cols;
698 } HAL_INI_ARRAY;
699
700 #define HAL_INI_INIT(_ia, _data, _cols) do { \
701 (_ia)->data = (const uint32_t *)(_data); \
702 (_ia)->rows = sizeof(_data) / sizeof((_data)[0]); \
703 (_ia)->cols = (_cols); \
704 } while (0)
705 #define HAL_INI_VAL(_ia, _r, _c) \
706 ((_ia)->data[((_r)*(_ia)->cols) + (_c)])
707
708 /*
709 * OS_DELAY() does a PIO READ on the PCI bus which allows
710 * other cards' DMA reads to complete in the middle of our reset.
711 */
712 #define DMA_YIELD(x) do { \
713 if ((++(x) % 64) == 0) \
714 OS_DELAY(1); \
715 } while (0)
716
717 #define HAL_INI_WRITE_ARRAY(ah, regArray, col, regWr) do { \
718 int r; \
719 for (r = 0; r < N(regArray); r++) { \
720 OS_REG_WRITE(ah, (regArray)[r][0], (regArray)[r][col]); \
721 DMA_YIELD(regWr); \
722 } \
723 } while (0)
724
725 #define HAL_INI_WRITE_BANK(ah, regArray, bankData, regWr) do { \
726 int r; \
727 for (r = 0; r < N(regArray); r++) { \
728 OS_REG_WRITE(ah, (regArray)[r][0], (bankData)[r]); \
729 DMA_YIELD(regWr); \
730 } \
731 } while (0)
732
733 extern int ath_hal_ini_write(struct ath_hal *ah, const HAL_INI_ARRAY *ia,
734 int col, int regWr);
735 extern void ath_hal_ini_bank_setup(uint32_t data[], const HAL_INI_ARRAY *ia,
736 int col);
737 extern int ath_hal_ini_bank_write(struct ath_hal *ah, const HAL_INI_ARRAY *ia,
738 const uint32_t data[], int regWr);
739
740 #define WLAN_CTRL_FRAME_SIZE (2+2+6+4) /* ACK+FCS */
741 #endif /* _ATH_AH_INTERAL_H_ */
Mirror of AROS' svn.