workbench/devs/networks/atheros5000/hal/ah_osdep.h

   1 /*
   2  * Copyright (c) 2002-2008 Sam Leffler, Errno Consulting
   3  * Copyright (c) 2002-2008 Atheros Communications, Inc.
   4  *
   5  * Permission to use, copy, modify, and/or distribute this software for any
   6  * purpose with or without fee is hereby granted, provided that the above
   7  * copyright notice and this permission notice appear in all copies.
   8  *
   9  * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
  10  * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
  11  * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
  12  * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
  13  * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
  14  * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF
  15  * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
  16  *
  17  * $Id$
  18  */
  19 #ifndef _ATH_AH_OSDEP_H_
  20 #define _ATH_AH_OSDEP_H_
  21 /*
  22  * Atheros Hardware Access Layer (HAL) OS Dependent Definitions.
  23  */
  24
  25 /*
  26  * Starting with 2.6.4 the kernel supports a configuration option
  27  * to pass parameters in registers.  If this is enabled we must
  28  * mark all function interfaces in+out of the HAL to pass parameters
  29  * on the stack as this is the convention used internally (for
  30  * maximum portability).
  31  */
  32 #define __ahdecl
  33 #ifndef __packed
  34 #define __packed        __attribute__((__packed__))
  35 #endif
  36
  37 /*
  38  * Beware of these being mismatched against the contents of <linux/types.h>
  39  */
  40 #include <stdarg.h>
  41 #include <stdlib.h>
  42 #ifndef _LINUX_TYPES_H
  43 /* NB: arm defaults to unsigned so be explicit */
  44 typedef signed char int8_t;
  45 typedef short int16_t;
  46 typedef int int32_t;
  47 typedef long long int64_t;
  48
  49 typedef unsigned char uint8_t;
  50 typedef unsigned short uint16_t;
  51 typedef unsigned int uint32_t;
  52 typedef unsigned long long uint64_t;
  53
  54 //typedef unsigned int size_t;
  55 typedef unsigned int u_int;
  56 //typedef       void *va_list;
  57 #endif
  58
  59 /*
  60  * Linux/BSD gcc compatibility shims.
  61  */
  62 #define __printflike(_a,_b) \
  63         __attribute__ ((__format__ (__printf__, _a, _b)))
  64 #define __va_list       va_list
  65 #define OS_INLINE       __inline
  66
  67 /*
  68  * Delay n microseconds.
  69  */
  70 extern  void __ahdecl ath_hal_delay(int);
  71 #define OS_DELAY(_n)    ath_hal_delay(_n)
  72
  73 #define OS_MEMZERO(_a, _n)      ath_hal_memzero((_a), (_n))
  74 extern void __ahdecl ath_hal_memzero(void *, size_t);
  75 #define OS_MEMCPY(_d, _s, _n)   ath_hal_memcpy(_d,_s,_n)
  76 extern void * __ahdecl ath_hal_memcpy(void *, const void *, size_t);
  77
  78 #ifndef abs
  79 #define abs(_a)         __builtin_abs(_a)
  80 #endif
  81
  82 struct ath_hal;
  83 extern  uint32_t __ahdecl ath_hal_getuptime(struct ath_hal *);
  84 #define OS_GETUPTIME(_ah)       ath_hal_getuptime(_ah)
  85
  86 /*
  87  * Byte order/swapping support.
  88  */
  89 #define AH_LITTLE_ENDIAN        1234
  90 #define AH_BIG_ENDIAN           4321
  91
  92 #ifndef AH_BYTE_ORDER
  93 /*
  94  * When the .inc file is not available (e.g. when building
  95  * in a kernel source tree); look for some other way to
  96  * setup the host byte order.
  97  */
  98 #ifdef __LITTLE_ENDIAN
  99 #define AH_BYTE_ORDER   AH_LITTLE_ENDIAN
 100 #endif
 101 #ifdef __BIG_ENDIAN
 102 #define AH_BYTE_ORDER   AH_BIG_ENDIAN
 103 #endif
 104 #define AH_BYTE_ORDER   AH_BIG_ENDIAN // !!!
 105 #ifndef AH_BYTE_ORDER
 106 #error "Do not know host byte order"
 107 #endif
 108 #endif /* AH_BYTE_ORDER */
 109
 110 #if AH_BYTE_ORDER == AH_BIG_ENDIAN
 111 /*
 112  * This could be optimized but since we only use it for
 113  * a few registers there's little reason to do so.
 114  */
 115 static __inline__ uint32_t
 116 __bswap32(uint32_t _x)
 117 {
 118         return ((uint32_t)(
 119               (((const uint8_t *)(&_x))[0]    ) |
 120               (((const uint8_t *)(&_x))[1]<< 8) |
 121               (((const uint8_t *)(&_x))[2]<<16) |
 122               (((const uint8_t *)(&_x))[3]<<24))
 123         );
 124 }
 125 #else
 126 #define __bswap32(_x)   (_x)
 127 #endif
 128
 129 /*
 130  * Register read/write; we assume the registers will always
 131  * be memory-mapped.  Note that register accesses are done
 132  * using target-specific functions when debugging is enabled
 133  * (AH_DEBUG) or we are explicitly configured this way.  The
 134  * latter is used on some platforms where the full i/o space
 135  * cannot be directly mapped.
 136  *
 137  * The hardware registers are native little-endian byte order.
 138  * Big-endian hosts are handled by enabling hardware byte-swap
 139  * of register reads and writes at reset.  But the PCI clock
 140  * domain registers are not byte swapped!  Thus, on big-endian
 141  * platforms we have to byte-swap those registers specifically.
 142  * Most of this code is collapsed at compile time because the
 143  * register values are constants.
 144  */
 145 #if AH_BYTE_ORDER == AH_BIG_ENDIAN
 146 #define OS_REG_UNSWAPPED(_reg) \
 147         (((_reg) >= 0x4000 && (_reg) < 0x5000) || \
 148          ((_reg) >= 0x7000 && (_reg) < 0x8000))
 149 #define _OS_REG_WRITE(_ah, _reg, _val) do {                                 \
 150         if (OS_REG_UNSWAPPED(_reg))                                         \
 151                 *((volatile uint32_t *)((_ah)->ah_sh + (_reg))) =           \
 152                         __bswap32((_val));                                  \
 153         else                                                                \
 154                 *((volatile uint32_t *)((_ah)->ah_sh + (_reg))) = (_val);  \
 155 } while (0)
 156 #define _OS_REG_READ(_ah, _reg) \
 157         (OS_REG_UNSWAPPED(_reg) ? \
 158                 __bswap32(*((volatile uint32_t *)((_ah)->ah_sh + (_reg)))) : \
 159                 *((volatile uint32_t *)((_ah)->ah_sh + (_reg))))
 160 #else /* AH_LITTLE_ENDIAN */
 161 #define OS_REG_UNSWAPPED(_reg)  (0)
 162 #define _OS_REG_WRITE(_ah, _reg, _val) do { \
 163         *((volatile uint32_t *)((_ah)->ah_sh + (_reg))) = (_val); \
 164 } while (0)
 165 #define _OS_REG_READ(_ah, _reg) \
 166         *((volatile uint32_t *)((_ah)->ah_sh + (_reg)))
 167 #endif /* AH_BYTE_ORDER */
 168
 169 #if 0 && defined(AH_DEBUG) || defined(AH_REGOPS_FUNC) || defined(AH_DEBUG_ALQ)
 170 /* use functions to do register operations */
 171 #define OS_REG_WRITE(_ah, _reg, _val)   ath_hal_reg_write(_ah, _reg, _val)
 172 #define OS_REG_READ(_ah, _reg)          ath_hal_reg_read(_ah, _reg)
 173
 174 extern  void __ahdecl ath_hal_reg_write(struct ath_hal *ah,
 175                 u_int reg, uint32_t val);
 176 extern  uint32_t __ahdecl ath_hal_reg_read(struct ath_hal *ah, u_int reg);
 177 #else
 178 /* inline register operations */
 179 #define OS_REG_WRITE(_ah, _reg, _val)   _OS_REG_WRITE(_ah, _reg, _val)
 180 #define OS_REG_READ(_ah, _reg)          _OS_REG_READ(_ah, _reg)
 181 #endif /* AH_DEBUG || AH_REGFUNC || AH_DEBUG_ALQ */
 182
 183 #ifdef AH_DEBUG_ALQ
 184 extern  void __ahdecl OS_MARK(struct ath_hal *, u_int id, uint32_t value);
 185 #else
 186 #define OS_MARK(_ah, _id, _v)
 187 #endif
 188
 189 #endif /* _ATH_AH_OSDEP_H_ */