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Check for SYS/GL during library init. Reason is that
[AROS.git] / workbench / devs / networks / atheros5000 / hal / ar5210 / ar5210.h
blob4e13c60f973f2a5796155a7c54f5aa1e27cca511
1 /*
2 * Copyright (c) 2002-2008 Sam Leffler, Errno Consulting
3 * Copyright (c) 2002-2004 Atheros Communications, Inc.
4 *
5 * Permission to use, copy, modify, and/or distribute this software for any
6 * purpose with or without fee is hereby granted, provided that the above
7 * copyright notice and this permission notice appear in all copies.
8 *
9 * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
10 * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
11 * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
12 * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
13 * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
14 * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF
15 * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
16 *
17 * $Id$
18 */
19 #ifndef _ATH_AR5210_H_
20 #define _ATH_AR5210_H_
21
22 #define AR5210_MAGIC 0x19980124
23
24 #if 0
25 /*
26 * RTS_ENABLE includes LONG_PKT because they essentially
27 * imply the same thing, and are set or not set together
28 * for this chip
29 */
30 #define AR5210_TXD_CTRL_A_HDR_LEN(_val) (((_val) ) & 0x0003f)
31 #define AR5210_TXD_CTRL_A_TX_RATE(_val) (((_val) << 6) & 0x003c0)
32 #define AR5210_TXD_CTRL_A_RTS_ENABLE ( 0x00c00)
33 #define AR5210_TXD_CTRL_A_CLEAR_DEST_MASK(_val) (((_val) << 12) & 0x01000)
34 #define AR5210_TXD_CTRL_A_ANT_MODE(_val) (((_val) << 13) & 0x02000)
35 #define AR5210_TXD_CTRL_A_PKT_TYPE(_val) (((_val) << 14) & 0x1c000)
36 #define AR5210_TXD_CTRL_A_INT_REQ ( 0x20000)
37 #define AR5210_TXD_CTRL_A_KEY_VALID ( 0x40000)
38 #define AR5210_TXD_CTRL_B_KEY_ID(_val) (((_val) ) & 0x0003f)
39 #define AR5210_TXD_CTRL_B_RTS_DURATION(_val) (((_val) << 6) & 0x7ffc0)
40 #endif
41
42 #define INIT_CONFIG_STATUS 0x00000000
43 #define INIT_ACKTOPS 0x00000008
44 #define INIT_BCON_CNTRL_REG 0x00000000
45 #define INIT_SLOT_TIME 0x00000168
46 #define INIT_SLOT_TIME_TURBO 0x000001e0 /* More aggressive turbo slot timing = 6 us */
47 #define INIT_ACK_CTS_TIMEOUT 0x04000400
48 #define INIT_ACK_CTS_TIMEOUT_TURBO 0x08000800
49
50 #define INIT_USEC 0x27
51 #define INIT_USEC_TURBO 0x4f
52 #define INIT_USEC_32 0x1f
53 #define INIT_TX_LATENCY 0x36
54 #define INIT_RX_LATENCY 0x1D
55 #define INIT_TRANSMIT_LATENCY \
56 ((INIT_RX_LATENCY << AR_USEC_RX_LATENCY_S) | \
57 (INIT_TX_LATENCY << AR_USEC_TX_LATENCY_S) | \
58 (INIT_USEC_32 << 7) | INIT_USEC )
59 #define INIT_TRANSMIT_LATENCY_TURBO \
60 ((INIT_RX_LATENCY << AR_USEC_RX_LATENCY_S) | \
61 (INIT_TX_LATENCY << AR_USEC_TX_LATENCY_S) | \
62 (INIT_USEC_32 << 7) | INIT_USEC_TURBO)
63
64 #define INIT_SIFS 0x230 /* = 16 us - 2 us */
65 #define INIT_SIFS_TURBO 0x1E0 /* More aggressive turbo SIFS timing - 8 us - 2 us */
66
67 /*
68 * Various fifo fill before Tx start, in 64-byte units
69 * i.e. put the frame in the air while still DMAing
70 */
71 #define MIN_TX_FIFO_THRESHOLD 0x1
72 #define MAX_TX_FIFO_THRESHOLD ((IEEE80211_MAX_LEN / 64) + 1)
73
74 #define INIT_NEXT_CFP_START 0xffffffff
75
76 #define INIT_BEACON_PERIOD 0xffff
77 #define INIT_BEACON_EN 0 /* this should be set by AP only when it's ready */
78 #define INIT_BEACON_CONTROL \
79 ((INIT_RESET_TSF << 24) | (INIT_BEACON_EN << 23) | \
80 (INIT_TIM_OFFSET<<16) | INIT_BEACON_PERIOD)
81
82 #define INIT_RSSI_THR 0x00000700 /* Missed beacon counter initialized to max value of 7 */
83 #define INIT_ProgIFS 0x398 /* PIFS - 2us */
84 #define INIT_ProgIFS_TURBO 0x3C0
85 #define INIT_EIFS 0xd70
86 #define INIT_EIFS_TURBO 0x1ae0
87 #define INIT_CARR_SENSE_EN 1
88 #define INIT_PROTO_TIME_CNTRL ( (INIT_CARR_SENSE_EN << 26) | (INIT_EIFS << 12) | \
89 (INIT_ProgIFS) )
90 #define INIT_PROTO_TIME_CNTRL_TURBO ( (INIT_CARR_SENSE_EN << 26) | (INIT_EIFS_TURBO << 12) | \
91 (INIT_ProgIFS_TURBO) )
92
93 /*
94 * EEPROM defines for Version 1 Crete EEPROM.
95 *
96 * The EEPROM is segmented into three sections:
97 *
98 * PCI/Cardbus default configuration settings
99 * Cardbus CIS tuples and vendor-specific data
100 * Atheros-specific data
101 *
102 * EEPROM entries are read 32-bits at a time through the PCI bus
103 * interface but are all 16-bit values.
104 *
105 * Access to the Atheros-specific data is controlled by protection
106 * bits and the data is checksum'd. The driver reads the Atheros
107 * data from the EEPROM at attach and caches it in its private state.
108 * This data includes the local regulatory domain, channel calibration
109 * settings, and phy-related configuration settings.
110 */
111 #define AR_EEPROM_MAC(i) (0x1f-(i))/* MAC address word */
112 #define AR_EEPROM_MAGIC 0x3d /* magic number */
113 #define AR_EEPROM_PROTECT 0x3f /* Atheros segment protect register */
114 #define AR_EEPROM_PROTOTECT_WP_128_191 0x80
115 #define AR_EEPROM_REG_DOMAIN 0xbf /* Current regulatory domain register */
116 #define AR_EEPROM_ATHEROS_BASE 0xc0 /* Base of Atheros-specific data */
117 #define AR_EEPROM_ATHEROS_MAX 64 /* 64x2=128 bytes of EEPROM settings */
118 #define AR_EEPROM_ATHEROS(n) (AR_EEPROM_ATHEROS_BASE+(n))
119 #define AR_EEPROM_VERSION AR_EEPROM_ATHEROS(1)
120 #define AR_EEPROM_ATHEROS_TP_SETTINGS 0x09 /* Transmit power settings */
121 #define AR_REG_DOMAINS_MAX 4 /* # of Regulatory Domains */
122 #define AR_CHANNELS_MAX 5 /* # of Channel calibration groups */
123 #define AR_TP_SETTINGS_SIZE 11 /* # locations/Channel group */
124 #define AR_TP_SCALING_ENTRIES 11 /* # entries in transmit power dBm->pcdac */
125
126 /*
127 * NB: we store the rfsilent select+polarity data packed
128 * with the encoding used in later parts so values
129 * returned to applications are consistent.
130 */
131 #define AR_EEPROM_RFSILENT_GPIO_SEL 0x001c
132 #define AR_EEPROM_RFSILENT_GPIO_SEL_S 2
133 #define AR_EEPROM_RFSILENT_POLARITY 0x0002
134 #define AR_EEPROM_RFSILENT_POLARITY_S 1
135
136 #define AR_I2DBM(x) ((uint8_t)((x * 2) + 3))
137
138 /*
139 * Transmit power and channel calibration settings.
140 */
141 struct tpcMap {
142 uint8_t pcdac[AR_TP_SCALING_ENTRIES];
143 uint8_t gainF[AR_TP_SCALING_ENTRIES];
144 uint8_t rate36;
145 uint8_t rate48;
146 uint8_t rate54;
147 uint8_t regdmn[AR_REG_DOMAINS_MAX];
148 };
149
150 /* NB: this is in ah_eeprom.h which isn't used for 5210 support */
151 #ifndef MAX_RATE_POWER
152 #define MAX_RATE_POWER 60
153 #endif
154
155 #undef HAL_NUM_TX_QUEUES /* from ah.h */
156 #define HAL_NUM_TX_QUEUES 3
157
158 struct ath_hal_5210 {
159 struct ath_hal_private ah_priv; /* base definitions */
160
161 /*
162 * Information retrieved from EEPROM
163 */
164 uint16_t ah_eeversion; /* EEPROM Version field */
165 uint16_t ah_eeprotect; /* EEPROM protection settings */
166 uint16_t ah_antenna; /* Antenna Settings */
167 uint16_t ah_biasCurrents; /* OB, DB */
168 uint8_t ah_thresh62; /* thresh62 */
169 uint8_t ah_xlnaOn; /* External LNA timing */
170 uint8_t ah_xpaOff; /* Extern output stage timing */
171 uint8_t ah_xpaOn; /* Extern output stage timing */
172 uint8_t ah_rfKill; /* Single low bit signalling if RF Kill is implemented */
173 uint8_t ah_devType; /* Type: PCI, miniPCI, CB */
174 uint8_t ah_regDomain[AR_REG_DOMAINS_MAX];
175 /* calibrated reg domains */
176 struct tpcMap ah_tpc[AR_CHANNELS_MAX];
177 uint8_t ah_macaddr[IEEE80211_ADDR_LEN];
178 /*
179 * Runtime state.
180 */
181 uint32_t ah_maskReg; /* shadow of IMR+IER regs */
182 uint32_t ah_txOkInterruptMask;
183 uint32_t ah_txErrInterruptMask;
184 uint32_t ah_txDescInterruptMask;
185 uint32_t ah_txEolInterruptMask;
186 uint32_t ah_txUrnInterruptMask;
187 HAL_POWER_MODE ah_powerMode;
188 uint8_t ah_bssid[IEEE80211_ADDR_LEN];
189 HAL_TX_QUEUE_INFO ah_txq[HAL_NUM_TX_QUEUES]; /* beacon+cab+data */
190 /*
191 * Station mode support.
192 */
193 uint32_t ah_staId1Defaults; /* STA_ID1 default settings */
194 uint32_t ah_rssiThr; /* RSSI_THR settings */
195
196 u_int ah_sifstime; /* user-specified sifs time */
197 u_int ah_slottime; /* user-specified slot time */
198 u_int ah_acktimeout; /* user-specified ack timeout */
199 u_int ah_ctstimeout; /* user-specified cts timeout */
200 };
201 #define AH5210(ah) ((struct ath_hal_5210 *)(ah))
202
203 struct ath_hal;
204
205 extern struct ath_hal *ar5210Attach(uint16_t, HAL_SOFTC,
206 HAL_BUS_TAG, HAL_BUS_HANDLE, HAL_STATUS *);
207 extern void ar5210Detach(struct ath_hal *);
208
209 extern HAL_BOOL ar5210Reset(struct ath_hal *, HAL_OPMODE,
210 HAL_CHANNEL *, HAL_BOOL bChannelChange, HAL_STATUS *);
211 extern void ar5210SetPCUConfig(struct ath_hal *);
212 extern HAL_BOOL ar5210PhyDisable(struct ath_hal *);
213 extern HAL_BOOL ar5210Disable(struct ath_hal *);
214 extern HAL_BOOL ar5210ChipReset(struct ath_hal *, HAL_CHANNEL *);
215 extern HAL_BOOL ar5210PerCalibration(struct ath_hal *, HAL_CHANNEL *, HAL_BOOL *);
216 extern int16_t ar5210GetNoiseFloor(struct ath_hal *);
217 extern int16_t ar5210GetNfAdjust(struct ath_hal *,
218 const HAL_CHANNEL_INTERNAL *);
219 extern HAL_BOOL ar5210SetTxPowerLimit(struct ath_hal *, uint32_t limit);
220 extern HAL_BOOL ar5210SetTransmitPower(struct ath_hal *, HAL_CHANNEL *);
221 extern HAL_BOOL ar5210CalNoiseFloor(struct ath_hal *, HAL_CHANNEL_INTERNAL *);
222 extern HAL_BOOL ar5210ResetDma(struct ath_hal *, HAL_OPMODE);
223
224 extern HAL_BOOL ar5210SetTxQueueProps(struct ath_hal *ah, int q,
225 const HAL_TXQ_INFO *qInfo);
226 extern HAL_BOOL ar5210GetTxQueueProps(struct ath_hal *ah, int q,
227 HAL_TXQ_INFO *qInfo);
228 extern int ar5210SetupTxQueue(struct ath_hal *ah, HAL_TX_QUEUE type,
229 const HAL_TXQ_INFO *qInfo);
230 extern HAL_BOOL ar5210ReleaseTxQueue(struct ath_hal *ah, u_int q);
231 extern HAL_BOOL ar5210ResetTxQueue(struct ath_hal *ah, u_int q);
232 extern uint32_t ar5210GetTxDP(struct ath_hal *, u_int);
233 extern HAL_BOOL ar5210SetTxDP(struct ath_hal *, u_int, uint32_t txdp);
234 extern HAL_BOOL ar5210UpdateTxTrigLevel(struct ath_hal *, HAL_BOOL);
235 extern uint32_t ar5210NumTxPending(struct ath_hal *, u_int);
236 extern HAL_BOOL ar5210StartTxDma(struct ath_hal *, u_int);
237 extern HAL_BOOL ar5210StopTxDma(struct ath_hal *, u_int);
238 extern HAL_BOOL ar5210SetupTxDesc(struct ath_hal *, struct ath_desc *,
239 u_int pktLen, u_int hdrLen, HAL_PKT_TYPE type, u_int txPower,
240 u_int txRate0, u_int txRetries0,
241 u_int keyIx, u_int antMode, u_int flags,
242 u_int rtsctsRate, u_int rtsctsDuration,
243 u_int compicvLen, u_int compivLen, u_int comp);
244 extern HAL_BOOL ar5210SetupXTxDesc(struct ath_hal *, struct ath_desc *,
245 u_int txRate1, u_int txRetries1,
246 u_int txRate2, u_int txRetries2,
247 u_int txRate3, u_int txRetries3);
248 extern HAL_BOOL ar5210FillTxDesc(struct ath_hal *, struct ath_desc *,
249 u_int segLen, HAL_BOOL firstSeg, HAL_BOOL lastSeg,
250 const struct ath_desc *ds0);
251 extern HAL_STATUS ar5210ProcTxDesc(struct ath_hal *,
252 struct ath_desc *, struct ath_tx_status *);
253 extern void ar5210GetTxIntrQueue(struct ath_hal *ah, uint32_t *);
254 extern void ar5210IntrReqTxDesc(struct ath_hal *ah, struct ath_desc *);
255
256 extern uint32_t ar5210GetRxDP(struct ath_hal *);
257 extern void ar5210SetRxDP(struct ath_hal *, uint32_t rxdp);
258 extern void ar5210EnableReceive(struct ath_hal *);
259 extern HAL_BOOL ar5210StopDmaReceive(struct ath_hal *);
260 extern void ar5210StartPcuReceive(struct ath_hal *);
261 extern void ar5210StopPcuReceive(struct ath_hal *);
262 extern void ar5210SetMulticastFilter(struct ath_hal *,
263 uint32_t filter0, uint32_t filter1);
264 extern HAL_BOOL ar5210ClrMulticastFilterIndex(struct ath_hal *, uint32_t);
265 extern HAL_BOOL ar5210SetMulticastFilterIndex(struct ath_hal *, uint32_t);
266 extern uint32_t ar5210GetRxFilter(struct ath_hal *);
267 extern void ar5210SetRxFilter(struct ath_hal *, uint32_t);
268 extern HAL_BOOL ar5210SetupRxDesc(struct ath_hal *, struct ath_desc *,
269 uint32_t, u_int flags);
270 extern HAL_STATUS ar5210ProcRxDesc(struct ath_hal *, struct ath_desc *,
271 uint32_t, struct ath_desc *, uint64_t,
272 struct ath_rx_status *);
273
274 extern void ar5210GetMacAddress(struct ath_hal *, uint8_t *);
275 extern HAL_BOOL ar5210SetMacAddress(struct ath_hal *ah, const uint8_t *);
276 extern void ar5210GetBssIdMask(struct ath_hal *, uint8_t *);
277 extern HAL_BOOL ar5210SetBssIdMask(struct ath_hal *, const uint8_t *);
278 extern HAL_BOOL ar5210EepromRead(struct ath_hal *, u_int off, uint16_t *data);
279 extern HAL_BOOL ar5210EepromWrite(struct ath_hal *, u_int off, uint16_t data);
280 extern HAL_BOOL ar5210SetRegulatoryDomain(struct ath_hal *,
281 uint16_t, HAL_STATUS *);
282 extern u_int ar5210GetWirelessModes(struct ath_hal *ah);
283 extern void ar5210EnableRfKill(struct ath_hal *);
284 extern HAL_BOOL ar5210GpioCfgInput(struct ath_hal *, uint32_t gpio);
285 extern HAL_BOOL ar5210GpioCfgOutput(struct ath_hal *, uint32_t gpio);
286 extern uint32_t ar5210GpioGet(struct ath_hal *, uint32_t gpio);
287 extern HAL_BOOL ar5210GpioSet(struct ath_hal *, uint32_t gpio, uint32_t);
288 extern void ar5210Gpio0SetIntr(struct ath_hal *, u_int, uint32_t ilevel);
289 extern void ar5210SetLedState(struct ath_hal *, HAL_LED_STATE);
290 extern u_int ar5210GetDefAntenna(struct ath_hal *);
291 extern void ar5210SetDefAntenna(struct ath_hal *, u_int);
292 extern HAL_ANT_SETTING ar5210GetAntennaSwitch(struct ath_hal *);
293 extern HAL_BOOL ar5210SetAntennaSwitch(struct ath_hal *, HAL_ANT_SETTING);
294 extern void ar5210WriteAssocid(struct ath_hal *,
295 const uint8_t *bssid, uint16_t assocId);
296 extern uint32_t ar5210GetTsf32(struct ath_hal *);
297 extern uint64_t ar5210GetTsf64(struct ath_hal *);
298 extern void ar5210ResetTsf(struct ath_hal *);
299 extern uint32_t ar5210GetRandomSeed(struct ath_hal *);
300 extern HAL_BOOL ar5210DetectCardPresent(struct ath_hal *);
301 extern void ar5210UpdateMibCounters(struct ath_hal *, HAL_MIB_STATS *);
302 extern void ar5210EnableHwEncryption(struct ath_hal *);
303 extern void ar5210DisableHwEncryption(struct ath_hal *);
304 extern HAL_RFGAIN ar5210GetRfgain(struct ath_hal *);
305 extern HAL_BOOL ar5210SetSifsTime(struct ath_hal *, u_int);
306 extern u_int ar5210GetSifsTime(struct ath_hal *);
307 extern HAL_BOOL ar5210SetSlotTime(struct ath_hal *, u_int);
308 extern u_int ar5210GetSlotTime(struct ath_hal *);
309 extern HAL_BOOL ar5210SetAckTimeout(struct ath_hal *, u_int);
310 extern u_int ar5210GetAckTimeout(struct ath_hal *);
311 extern HAL_BOOL ar5210SetAckCTSRate(struct ath_hal *, u_int);
312 extern u_int ar5210GetAckCTSRate(struct ath_hal *);
313 extern HAL_BOOL ar5210SetCTSTimeout(struct ath_hal *, u_int);
314 extern u_int ar5210GetCTSTimeout(struct ath_hal *);
315 extern HAL_BOOL ar5210SetDecompMask(struct ath_hal *, uint16_t, int);
316 void ar5210SetCoverageClass(struct ath_hal *, uint8_t, int);
317 extern HAL_STATUS ar5210GetCapability(struct ath_hal *, HAL_CAPABILITY_TYPE,
318 uint32_t, uint32_t *);
319 extern HAL_BOOL ar5210SetCapability(struct ath_hal *, HAL_CAPABILITY_TYPE,
320 uint32_t, uint32_t, HAL_STATUS *);
321 extern HAL_BOOL ar5210GetDiagState(struct ath_hal *ah, int request,
322 const void *args, uint32_t argsize,
323 void **result, uint32_t *resultsize);
324
325 extern u_int ar5210GetKeyCacheSize(struct ath_hal *);
326 extern HAL_BOOL ar5210IsKeyCacheEntryValid(struct ath_hal *, uint16_t);
327 extern HAL_BOOL ar5210ResetKeyCacheEntry(struct ath_hal *, uint16_t entry);
328 extern HAL_BOOL ar5210SetKeyCacheEntry(struct ath_hal *, uint16_t entry,
329 const HAL_KEYVAL *, const uint8_t *mac, int xorKey);
330 extern HAL_BOOL ar5210SetKeyCacheEntryMac(struct ath_hal *,
331 uint16_t, const uint8_t *);
332
333 extern HAL_BOOL ar5210SetPowerMode(struct ath_hal *, uint32_t powerRequest,
334 int setChip);
335 extern HAL_POWER_MODE ar5210GetPowerMode(struct ath_hal *);
336
337 extern void ar5210SetBeaconTimers(struct ath_hal *,
338 const HAL_BEACON_TIMERS *);
339 extern void ar5210BeaconInit(struct ath_hal *, uint32_t, uint32_t);
340 extern void ar5210SetStaBeaconTimers(struct ath_hal *,
341 const HAL_BEACON_STATE *);
342 extern void ar5210ResetStaBeaconTimers(struct ath_hal *);
343
344 extern HAL_BOOL ar5210IsInterruptPending(struct ath_hal *);
345 extern HAL_BOOL ar5210GetPendingInterrupts(struct ath_hal *, HAL_INT *);
346 extern HAL_INT ar5210GetInterrupts(struct ath_hal *);
347 extern HAL_INT ar5210SetInterrupts(struct ath_hal *, HAL_INT ints);
348
349 extern const HAL_RATE_TABLE *ar5210GetRateTable(struct ath_hal *, u_int mode);
350
351 extern HAL_BOOL ar5210AniControl(struct ath_hal *, HAL_ANI_CMD, int );
352 extern void ar5210AniPoll(struct ath_hal *, const HAL_NODE_STATS *, HAL_CHANNEL *);
353 extern void ar5210MibEvent(struct ath_hal *, const HAL_NODE_STATS *);
354 #endif /* _ATH_AR5210_H_ */
Mirror of AROS' svn.