workbench/devs/networks/atheros5000/hal/ar5210/ar5210_recv.c

   1 /*
   2  * Copyright (c) 2002-2008 Sam Leffler, Errno Consulting
   3  * Copyright (c) 2002-2004 Atheros Communications, Inc.
   4  *
   5  * Permission to use, copy, modify, and/or distribute this software for any
   6  * purpose with or without fee is hereby granted, provided that the above
   7  * copyright notice and this permission notice appear in all copies.
   8  *
   9  * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
  10  * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
  11  * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
  12  * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
  13  * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
  14  * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF
  15  * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
  16  *
  17  * $Id$
  18  */
  19 #include "opt_ah.h"
  20
  21 #ifdef AH_SUPPORT_AR5210
  22
  23 #include "ah.h"
  24 #include "ah_internal.h"
  25 #include "ah_desc.h"
  26
  27 #include "ar5210/ar5210.h"
  28 #include "ar5210/ar5210reg.h"
  29 #include "ar5210/ar5210desc.h"
  30
  31 /*
  32  * Get the RXDP.
  33  */
  34 uint32_t
  35 ar5210GetRxDP(struct ath_hal *ah)
  36 {
  37         return OS_REG_READ(ah, AR_RXDP);
  38 }
  39
  40 /*
  41  * Set the RxDP.
  42  */
  43 void
  44 ar5210SetRxDP(struct ath_hal *ah, uint32_t rxdp)
  45 {
  46         OS_REG_WRITE(ah, AR_RXDP, rxdp);
  47 }
  48
  49
  50 /*
  51  * Set Receive Enable bits.
  52  */
  53 void
  54 ar5210EnableReceive(struct ath_hal *ah)
  55 {
  56         OS_REG_WRITE(ah, AR_CR, AR_CR_RXE);
  57 }
  58
  59 /*
  60  * Stop Receive at the DMA engine
  61  */
  62 HAL_BOOL
  63 ar5210StopDmaReceive(struct ath_hal *ah)
  64 {
  65         int i;
  66
  67         OS_REG_WRITE(ah, AR_CR, AR_CR_RXD);     /* Set receive disable bit */
  68         for (i = 0; i < 1000; i++) {
  69                 if ((OS_REG_READ(ah, AR_CR) & AR_CR_RXE) == 0)
  70                         return AH_TRUE;
  71                 OS_DELAY(10);
  72         }
  73 #ifdef AH_DEBUG
  74         ath_hal_printf(ah, "ar5210: dma receive failed to stop in 10ms\n");
  75         ath_hal_printf(ah, "AR_CR=0x%x\n", OS_REG_READ(ah, AR_CR));
  76         ath_hal_printf(ah, "AR_DIAG_SW=0x%x\n", OS_REG_READ(ah, AR_DIAG_SW));
  77 #endif
  78         return AH_FALSE;
  79 }
  80
  81 /*
  82  * Start Transmit at the PCU engine (unpause receive)
  83  */
  84 void
  85 ar5210StartPcuReceive(struct ath_hal *ah)
  86 {
  87         OS_REG_WRITE(ah, AR_DIAG_SW,
  88                 OS_REG_READ(ah, AR_DIAG_SW) & ~(AR_DIAG_SW_DIS_RX));
  89 }
  90
  91 /*
  92  * Stop Transmit at the PCU engine (pause receive)
  93  */
  94 void
  95 ar5210StopPcuReceive(struct ath_hal *ah)
  96 {
  97         OS_REG_WRITE(ah, AR_DIAG_SW,
  98                 OS_REG_READ(ah, AR_DIAG_SW) | AR_DIAG_SW_DIS_RX);
  99 }
 100
 101 /*
 102  * Set multicast filter 0 (lower 32-bits)
 103  *                         filter 1 (upper 32-bits)
 104  */
 105 void
 106 ar5210SetMulticastFilter(struct ath_hal *ah, uint32_t filter0, uint32_t filter1)
 107 {
 108         OS_REG_WRITE(ah, AR_MCAST_FIL0, filter0);
 109         OS_REG_WRITE(ah, AR_MCAST_FIL1, filter1);
 110 }
 111
 112 /*
 113  * Clear multicast filter by index
 114  */
 115 HAL_BOOL
 116 ar5210ClrMulticastFilterIndex(struct ath_hal *ah, uint32_t ix)
 117 {
 118         uint32_t val;
 119
 120         if (ix >= 64)
 121                 return AH_FALSE;
 122         if (ix >= 32) {
 123                 val = OS_REG_READ(ah, AR_MCAST_FIL1);
 124                 OS_REG_WRITE(ah, AR_MCAST_FIL1, (val &~ (1<<(ix-32))));
 125         } else {
 126                 val = OS_REG_READ(ah, AR_MCAST_FIL0);
 127                 OS_REG_WRITE(ah, AR_MCAST_FIL0, (val &~ (1<<ix)));
 128         }
 129         return AH_TRUE;
 130 }
 131
 132 /*
 133  * Set multicast filter by index
 134  */
 135 HAL_BOOL
 136 ar5210SetMulticastFilterIndex(struct ath_hal *ah, uint32_t ix)
 137 {
 138         uint32_t val;
 139
 140         if (ix >= 64)
 141                 return AH_FALSE;
 142         if (ix >= 32) {
 143                 val = OS_REG_READ(ah, AR_MCAST_FIL1);
 144                 OS_REG_WRITE(ah, AR_MCAST_FIL1, (val | (1<<(ix-32))));
 145         } else {
 146                 val = OS_REG_READ(ah, AR_MCAST_FIL0);
 147                 OS_REG_WRITE(ah, AR_MCAST_FIL0, (val | (1<<ix)));
 148         }
 149         return AH_TRUE;
 150 }
 151
 152 /*
 153  * Return the receive packet filter.
 154  */
 155 uint32_t
 156 ar5210GetRxFilter(struct ath_hal *ah)
 157 {
 158         /* XXX can't be sure if promiscuous mode is set because of PHYRADAR */
 159         return OS_REG_READ(ah, AR_RX_FILTER);
 160 }
 161
 162 /*
 163  * Turn off/on bits in the receive packet filter.
 164  */
 165 void
 166 ar5210SetRxFilter(struct ath_hal *ah, uint32_t bits)
 167 {
 168         if (bits & HAL_RX_FILTER_PHYRADAR) {
 169                 /* must enable promiscuous mode to get radar */
 170                 bits = (bits &~ HAL_RX_FILTER_PHYRADAR) | AR_RX_FILTER_PROMISCUOUS;
 171         }
 172         OS_REG_WRITE(ah, AR_RX_FILTER, bits);
 173 }
 174
 175 /*
 176  * Initialize RX descriptor, by clearing the status and clearing
 177  * the size.  This is not strictly HW dependent, but we want the
 178  * control and status words to be opaque above the hal.
 179  */
 180 HAL_BOOL
 181 ar5210SetupRxDesc(struct ath_hal *ah, struct ath_desc *ds,
 182         uint32_t size, u_int flags)
 183 {
 184         struct ar5210_desc *ads = AR5210DESC(ds);
 185
 186         (void) flags;
 187
 188         ads->ds_ctl0 = 0;
 189         ads->ds_ctl1 = size & AR_BufLen;
 190         if (ads->ds_ctl1 != size) {
 191                 HALDEBUG(ah, HAL_DEBUG_ANY, "%s: buffer size %u too large\n",
 192                     __func__, size);
 193                 return AH_FALSE;
 194         }
 195         if (flags & HAL_RXDESC_INTREQ)
 196                 ads->ds_ctl1 |= AR_RxInterReq;
 197         ads->ds_status0 = ads->ds_status1 = 0;
 198
 199         return AH_TRUE;
 200 }
 201
 202 /*
 203  * Process an RX descriptor, and return the status to the caller.
 204  * Copy some hardware specific items into the software portion
 205  * of the descriptor.
 206  *
 207  * NB: the caller is responsible for validating the memory contents
 208  *     of the descriptor (e.g. flushing any cached copy).
 209  */
 210 HAL_STATUS
 211 ar5210ProcRxDesc(struct ath_hal *ah, struct ath_desc *ds,
 212         uint32_t pa, struct ath_desc *nds, uint64_t tsf,
 213         struct ath_rx_status *rs)
 214 {
 215         struct ar5210_desc *ads = AR5210DESC(ds);
 216         struct ar5210_desc *ands = AR5210DESC(nds);
 217         uint32_t now, rstamp;
 218
 219         if ((ads->ds_status1 & AR_Done) == 0)
 220                 return HAL_EINPROGRESS;
 221         /*
 222          * Given the use of a self-linked tail be very sure that the hw is
 223          * done with this descriptor; the hw may have done this descriptor
 224          * once and picked it up again...make sure the hw has moved on.
 225          */
 226         if ((ands->ds_status1 & AR_Done) == 0 && OS_REG_READ(ah, AR_RXDP) == pa)
 227                 return HAL_EINPROGRESS;
 228
 229         rs->rs_datalen = ads->ds_status0 & AR_DataLen;
 230         rstamp = MS(ads->ds_status1, AR_RcvTimestamp);
 231         /*
 232          * Convert timestamp.  The value in the
 233          * descriptor is bits [10..22] of the TSF.
 234          */
 235         now = (OS_REG_READ(ah, AR_TSF_L32) >> 10) & 0xffff;
 236         if ((now & 0x1fff) < rstamp)
 237                 rstamp |= (now - 0x2000) & 0xffff;
 238         else
 239                 rstamp |= now;
 240         /* NB: keep only 15 bits for consistency w/ other chips */
 241         rs->rs_tstamp = rstamp & 0x7fff;
 242         rs->rs_status = 0;
 243         if ((ads->ds_status1 & AR_FrmRcvOK) == 0) {
 244                 if (ads->ds_status1 & AR_CRCErr)
 245                         rs->rs_status |= HAL_RXERR_CRC;
 246                 else if (ads->ds_status1 & AR_DecryptCRCErr)
 247                         rs->rs_status |= HAL_RXERR_DECRYPT;
 248                 else if (ads->ds_status1 & AR_FIFOOverrun)
 249                         rs->rs_status |= HAL_RXERR_FIFO;
 250                 else {
 251                         rs->rs_status |= HAL_RXERR_PHY;
 252                         rs->rs_phyerr =
 253                                 (ads->ds_status1 & AR_PHYErr) >> AR_PHYErr_S;
 254                 }
 255         }
 256         /* XXX what about KeyCacheMiss? */
 257         rs->rs_rssi = MS(ads->ds_status0, AR_RcvSigStrength);
 258         if (ads->ds_status1 & AR_KeyIdxValid)
 259                 rs->rs_keyix = MS(ads->ds_status1, AR_KeyIdx);
 260         else
 261                 rs->rs_keyix = HAL_RXKEYIX_INVALID;
 262         /* NB: caller expected to do rate table mapping */
 263         rs->rs_rate = MS(ads->ds_status0, AR_RcvRate);
 264         rs->rs_antenna  = (ads->ds_status0 & AR_RcvAntenna) ? 1 : 0;
 265         rs->rs_more = (ads->ds_status0 & AR_More) ? 1 : 0;
 266
 267         return HAL_OK;
 268 }
 269 #endif /* AH_SUPPORT_AR5210 */