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Check for SYS/GL during library init. Reason is that
[AROS.git] / workbench / devs / networks / atheros5000 / hal / ar5212 / ar5212.h
blobaa9848fbbbee59d18cac7bf08e31971ac5ac7901
1 /*
2 * Copyright (c) 2002-2008 Sam Leffler, Errno Consulting
3 * Copyright (c) 2002-2008 Atheros Communications, Inc.
4 *
5 * Permission to use, copy, modify, and/or distribute this software for any
6 * purpose with or without fee is hereby granted, provided that the above
7 * copyright notice and this permission notice appear in all copies.
8 *
9 * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
10 * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
11 * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
12 * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
13 * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
14 * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF
15 * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
16 *
17 * $Id$
18 */
19 #ifndef _ATH_AR5212_H_
20 #define _ATH_AR5212_H_
21
22 #include "ah_eeprom.h"
23
24 #define AR5212_MAGIC 0x19541014
25
26 /* DCU Transmit Filter macros */
27 #define CALC_MMR(dcu, idx) \
28 ( (4 * dcu) + (idx < 32 ? 0 : (idx < 64 ? 1 : (idx < 96 ? 2 : 3))) )
29 #define TXBLK_FROM_MMR(mmr) \
30 (AR_D_TXBLK_BASE + ((mmr & 0x1f) << 6) + ((mmr & 0x20) >> 3))
31 #define CALC_TXBLK_ADDR(dcu, idx) (TXBLK_FROM_MMR(CALC_MMR(dcu, idx)))
32 #define CALC_TXBLK_VALUE(idx) (1 << (idx & 0x1f))
33
34 /* MAC register values */
35
36 #define INIT_INTERRUPT_MASK \
37 ( AR_IMR_TXERR | AR_IMR_TXOK | AR_IMR_RXORN | \
38 AR_IMR_RXERR | AR_IMR_RXOK | AR_IMR_TXURN | \
39 AR_IMR_HIUERR )
40 #define INIT_BEACON_CONTROL \
41 ((INIT_RESET_TSF << 24) | (INIT_BEACON_EN << 23) | \
42 (INIT_TIM_OFFSET << 16) | INIT_BEACON_PERIOD)
43
44 #define INIT_CONFIG_STATUS 0x00000000
45 #define INIT_RSSI_THR 0x00000781 /* Missed beacon counter initialized to 0x7 (max is 0xff) */
46 #define INIT_IQCAL_LOG_COUNT_MAX 0xF
47 #define INIT_BCON_CNTRL_REG 0x00000000
48
49 #define INIT_USEC 40
50 #define HALF_RATE_USEC 19 /* ((40 / 2) - 1 ) */
51 #define QUARTER_RATE_USEC 9 /* ((40 / 4) - 1 ) */
52
53 #define RX_NON_FULL_RATE_LATENCY 63
54 #define TX_HALF_RATE_LATENCY 108
55 #define TX_QUARTER_RATE_LATENCY 216
56
57 #define IFS_SLOT_FULL_RATE 0x168 /* 9 us half, 40 MHz core clock (9*40) */
58 #define IFS_SLOT_HALF_RATE 0x104 /* 13 us half, 20 MHz core clock (13*20) */
59 #define IFS_SLOT_QUARTER_RATE 0xD2 /* 21 us quarter, 10 MHz core clock (21*10) */
60 #define IFS_EIFS_FULL_RATE 0xE60 /* (74 + (2 * 9)) * 40MHz core clock */
61 #define IFS_EIFS_HALF_RATE 0xDAC /* (149 + (2 * 13)) * 20MHz core clock */
62 #define IFS_EIFS_QUARTER_RATE 0xD48 /* (298 + (2 * 21)) * 10MHz core clock */
63
64 #define ACK_CTS_TIMEOUT_11A 0x3E8 /* ACK timeout in 11a core clocks */
65
66 /* Tx frame start to tx data start delay */
67 #define TX_FRAME_D_START_HALF_RATE 0xc
68 #define TX_FRAME_D_START_QUARTER_RATE 0xd
69
70 /*
71 * Various fifo fill before Tx start, in 64-byte units
72 * i.e. put the frame in the air while still DMAing
73 */
74 #define MIN_TX_FIFO_THRESHOLD 0x1
75 #define MAX_TX_FIFO_THRESHOLD ((IEEE80211_MAX_LEN / 64) + 1)
76 #define INIT_TX_FIFO_THRESHOLD MIN_TX_FIFO_THRESHOLD
77
78 #define HAL_DECOMP_MASK_SIZE 128 /* 1 byte per key */
79
80 /*
81 * Gain support.
82 */
83 #define NUM_CORNER_FIX_BITS 4
84 #define NUM_CORNER_FIX_BITS_5112 7
85 #define DYN_ADJ_UP_MARGIN 15
86 #define DYN_ADJ_LO_MARGIN 20
87 #define PHY_PROBE_CCK_CORRECTION 5
88 #define CCK_OFDM_GAIN_DELTA 15
89
90 enum GAIN_PARAMS {
91 GP_TXCLIP,
92 GP_PD90,
93 GP_PD84,
94 GP_GSEL,
95 };
96
97 enum GAIN_PARAMS_5112 {
98 GP_MIXGAIN_OVR,
99 GP_PWD_138,
100 GP_PWD_137,
101 GP_PWD_136,
102 GP_PWD_132,
103 GP_PWD_131,
104 GP_PWD_130,
105 };
106
107 typedef struct _gainOptStep {
108 int16_t paramVal[NUM_CORNER_FIX_BITS_5112];
109 int32_t stepGain;
110 int8_t stepName[16];
111 } GAIN_OPTIMIZATION_STEP;
112
113 typedef struct {
114 uint32_t numStepsInLadder;
115 uint32_t defaultStepNum;
116 GAIN_OPTIMIZATION_STEP optStep[10];
117 } GAIN_OPTIMIZATION_LADDER;
118
119 typedef struct {
120 uint32_t currStepNum;
121 uint32_t currGain;
122 uint32_t targetGain;
123 uint32_t loTrig;
124 uint32_t hiTrig;
125 uint32_t gainFCorrection;
126 uint32_t active;
127 const GAIN_OPTIMIZATION_STEP *currStep;
128 } GAIN_VALUES;
129
130 /* RF HAL structures */
131 typedef struct RfHalFuncs {
132 void *priv; /* private state */
133
134 void (*rfDetach)(struct ath_hal *ah);
135 void (*writeRegs)(struct ath_hal *,
136 u_int modeIndex, u_int freqIndex, int regWrites);
137 uint32_t *(*getRfBank)(struct ath_hal *ah, int bank);
138 HAL_BOOL (*setChannel)(struct ath_hal *, HAL_CHANNEL_INTERNAL *);
139 HAL_BOOL (*setRfRegs)(struct ath_hal *,
140 HAL_CHANNEL_INTERNAL *, uint16_t modesIndex,
141 uint16_t *rfXpdGain);
142 HAL_BOOL (*setPowerTable)(struct ath_hal *ah,
143 int16_t *minPower, int16_t *maxPower,
144 HAL_CHANNEL_INTERNAL *, uint16_t *rfXpdGain);
145 HAL_BOOL (*getChannelMaxMinPower)(struct ath_hal *ah, HAL_CHANNEL *,
146 int16_t *maxPow, int16_t *minPow);
147 int16_t (*getNfAdjust)(struct ath_hal *, const HAL_CHANNEL_INTERNAL*);
148 } RF_HAL_FUNCS;
149
150 struct ar5212AniParams {
151 int maxNoiseImmunityLevel; /* [0..4] */
152 int totalSizeDesired[5];
153 int coarseHigh[5];
154 int coarseLow[5];
155 int firpwr[5];
156
157 int maxSpurImmunityLevel; /* [0..7] */
158 int cycPwrThr1[8];
159
160 int maxFirstepLevel; /* [0..2] */
161 int firstep[3];
162
163 uint32_t ofdmTrigHigh;
164 uint32_t ofdmTrigLow;
165 uint32_t cckTrigHigh;
166 uint32_t cckTrigLow;
167 int32_t rssiThrLow;
168 uint32_t rssiThrHigh;
169
170 int period; /* update listen period */
171
172 /* NB: intentionally ordered so data exported to user space is first */
173 uint32_t ofdmPhyErrBase; /* Base value for ofdm err counter */
174 uint32_t cckPhyErrBase; /* Base value for cck err counters */
175 };
176
177 /*
178 * Per-channel ANI state private to the driver.
179 */
180 struct ar5212AniState {
181 uint8_t noiseImmunityLevel;
182 uint8_t spurImmunityLevel;
183 uint8_t firstepLevel;
184 uint8_t ofdmWeakSigDetectOff;
185 uint8_t cckWeakSigThreshold;
186 uint32_t listenTime;
187
188 /* NB: intentionally ordered so data exported to user space is first */
189 HAL_CHANNEL c;
190 HAL_BOOL isSetup; /* has state to do a restore */
191 uint32_t txFrameCount; /* Last txFrameCount */
192 uint32_t rxFrameCount; /* Last rx Frame count */
193 uint32_t cycleCount; /* Last cycleCount
194 (to detect wrap-around) */
195 uint32_t ofdmPhyErrCount;/* OFDM err count since last reset */
196 uint32_t cckPhyErrCount; /* CCK err count since last reset */
197
198 const struct ar5212AniParams *params;
199 };
200
201 #define HAL_ANI_ENA 0x00000001 /* ANI operation enabled */
202 #define HAL_RSSI_ANI_ENA 0x00000002 /* rssi-based processing ena'd*/
203
204 struct ar5212Stats {
205 uint32_t ast_ani_niup; /* ANI increased noise immunity */
206 uint32_t ast_ani_nidown; /* ANI decreased noise immunity */
207 uint32_t ast_ani_spurup; /* ANI increased spur immunity */
208 uint32_t ast_ani_spurdown;/* ANI descreased spur immunity */
209 uint32_t ast_ani_ofdmon; /* ANI OFDM weak signal detect on */
210 uint32_t ast_ani_ofdmoff;/* ANI OFDM weak signal detect off */
211 uint32_t ast_ani_cckhigh;/* ANI CCK weak signal threshold high */
212 uint32_t ast_ani_ccklow; /* ANI CCK weak signal threshold low */
213 uint32_t ast_ani_stepup; /* ANI increased first step level */
214 uint32_t ast_ani_stepdown;/* ANI decreased first step level */
215 uint32_t ast_ani_ofdmerrs;/* ANI cumulative ofdm phy err count */
216 uint32_t ast_ani_cckerrs;/* ANI cumulative cck phy err count */
217 uint32_t ast_ani_reset; /* ANI parameters zero'd for non-STA */
218 uint32_t ast_ani_lzero; /* ANI listen time forced to zero */
219 uint32_t ast_ani_lneg; /* ANI listen time calculated < 0 */
220 HAL_MIB_STATS ast_mibstats; /* MIB counter stats */
221 HAL_NODE_STATS ast_nodestats; /* Latest rssi stats from driver */
222 };
223
224 /*
225 * NF Cal history buffer
226 */
227 #define AR5212_CCA_MAX_GOOD_VALUE -95
228 #define AR5212_CCA_MAX_HIGH_VALUE -62
229 #define AR5212_CCA_MIN_BAD_VALUE -125
230
231 #define AR512_NF_CAL_HIST_MAX 5
232
233 struct ar5212NfCalHist {
234 int16_t nfCalBuffer[AR512_NF_CAL_HIST_MAX];
235 int16_t privNF;
236 uint8_t currIndex;
237 uint8_t first_run;
238 uint8_t invalidNFcount;
239 };
240
241 struct ath_hal_5212 {
242 struct ath_hal_private ah_priv; /* base class */
243
244 /*
245 * Per-chip common Initialization data.
246 * NB: RF backends have their own ini data.
247 */
248 HAL_INI_ARRAY ah_ini_modes;
249 HAL_INI_ARRAY ah_ini_common;
250
251 GAIN_VALUES ah_gainValues;
252
253 uint8_t ah_macaddr[IEEE80211_ADDR_LEN];
254 uint8_t ah_bssid[IEEE80211_ADDR_LEN];
255 uint8_t ah_bssidmask[IEEE80211_ADDR_LEN];
256
257 /*
258 * Runtime state.
259 */
260 uint32_t ah_maskReg; /* copy of AR_IMR */
261 struct ar5212Stats ah_stats; /* various statistics */
262 RF_HAL_FUNCS *ah_rfHal;
263 uint32_t ah_txDescMask; /* mask for TXDESC */
264 uint32_t ah_txOkInterruptMask;
265 uint32_t ah_txErrInterruptMask;
266 uint32_t ah_txDescInterruptMask;
267 uint32_t ah_txEolInterruptMask;
268 uint32_t ah_txUrnInterruptMask;
269 HAL_TX_QUEUE_INFO ah_txq[HAL_NUM_TX_QUEUES];
270 /* decomp mask array */
271 uint8_t ah_decompMask[HAL_DECOMP_MASK_SIZE];
272 HAL_POWER_MODE ah_powerMode;
273 HAL_ANT_SETTING ah_diversityControl; /* antenna setting */
274 enum {
275 IQ_CAL_INACTIVE,
276 IQ_CAL_RUNNING,
277 IQ_CAL_DONE
278 } ah_bIQCalibration; /* IQ calibrate state */
279 HAL_RFGAIN ah_rfgainState; /* RF gain calibrartion state */
280 uint32_t ah_tx6PowerInHalfDbm; /* power output for 6Mb tx */
281 uint32_t ah_staId1Defaults; /* STA_ID1 default settings */
282 uint32_t ah_miscMode; /* MISC_MODE settings */
283 uint32_t ah_rssiThr; /* RSSI_THR settings */
284 HAL_BOOL ah_cwCalRequire; /* for ap51 */
285 HAL_BOOL ah_tpcEnabled; /* per-packet tpc enabled */
286 uint32_t ah_macTPC; /* tpc register */
287 uint32_t ah_beaconInterval; /* XXX */
288 enum {
289 AUTO_32KHZ, /* use it if 32kHz crystal present */
290 USE_32KHZ, /* do it regardless */
291 DONT_USE_32KHZ, /* don't use it regardless */
292 } ah_enable32kHzClock; /* whether to sleep at 32kHz */
293 uint32_t ah_ofdmTxPower;
294 int16_t ah_txPowerIndexOffset;
295 /*
296 * Noise floor cal histogram support.
297 */
298 struct ar5212NfCalHist ah_nfCalHist;
299
300 u_int ah_slottime; /* user-specified slot time */
301 u_int ah_acktimeout; /* user-specified ack timeout */
302 u_int ah_ctstimeout; /* user-specified cts timeout */
303 u_int ah_sifstime; /* user-specified sifs time */
304 /*
305 * XXX
306 * 11g-specific stuff; belongs in the driver.
307 */
308 uint8_t ah_gBeaconRate; /* fixed rate for G beacons */
309 /*
310 * RF Silent handling; setup according to the EEPROM.
311 */
312 uint32_t ah_gpioSelect; /* GPIO pin to use */
313 uint32_t ah_polarity; /* polarity to disable RF */
314 uint32_t ah_gpioBit; /* after init, prev value */
315 HAL_BOOL ah_eepEnabled; /* EEPROM bit for capability */
316 /*
317 * ANI support.
318 */
319 uint32_t ah_procPhyErr; /* Process Phy errs */
320 HAL_BOOL ah_hasHwPhyCounters; /* Hardware has phy counters */
321 struct ar5212AniParams ah_aniParams24; /* 2.4GHz parameters */
322 struct ar5212AniParams ah_aniParams5; /* 5GHz parameters */
323 struct ar5212AniState *ah_curani; /* cached last reference */
324 struct ar5212AniState ah_ani[64]; /* per-channel state */
325
326 /*
327 * Transmit power state. Note these are maintained
328 * here so they can be retrieved by diagnostic tools.
329 */
330 uint16_t *ah_pcdacTable;
331 u_int ah_pcdacTableSize;
332 uint16_t ah_ratesArray[16];
333
334 /*
335 * Tx queue interrupt state.
336 */
337 uint32_t ah_intrTxqs;
338
339 HAL_BOOL ah_isHb63; /* cached HB63 check */
340 };
341 #define AH5212(_ah) ((struct ath_hal_5212 *)(_ah))
342
343 #define IS_5112(ah) \
344 ((AH_PRIVATE(ah)->ah_analog5GhzRev&0xf0) >= AR_RAD5112_SREV_MAJOR \
345 && (AH_PRIVATE(ah)->ah_analog5GhzRev&0xf0) < AR_RAD2316_SREV_MAJOR )
346 #define IS_RAD5112_REV1(ah) \
347 ((AH_PRIVATE(ah)->ah_analog5GhzRev&0x0f) < (AR_RAD5112_SREV_2_0&0x0f))
348 #define IS_RADX112_REV2(ah) \
349 (IS_5112(ah) && \
350 ((AH_PRIVATE(ah)->ah_analog5GhzRev == AR_RAD5112_SREV_2_0) || \
351 (AH_PRIVATE(ah)->ah_analog5GhzRev == AR_RAD2112_SREV_2_0) || \
352 (AH_PRIVATE(ah)->ah_analog5GhzRev == AR_RAD2112_SREV_2_1) || \
353 (AH_PRIVATE(ah)->ah_analog5GhzRev == AR_RAD5112_SREV_2_1)))
354 #define IS_5312_2_X(ah) \
355 (((AH_PRIVATE(ah)->ah_macVersion) == AR_SREV_VERSION_VENICE) && \
356 (((AH_PRIVATE(ah)->ah_macRev) == 2) || ((AH_PRIVATE(ah)->ah_macRev) == 7)))
357 #define IS_2317(ah) \
358 ((AH_PRIVATE(ah)->ah_devid == AR5212_AR2317_REV1) || \
359 (AH_PRIVATE(ah)->ah_devid == AR5212_AR2317_REV2))
360 #define IS_2316(ah) \
361 (AH_PRIVATE(ah)->ah_macVersion == AR_SREV_2415)
362 #define IS_2413(ah) \
363 (AH_PRIVATE(ah)->ah_macVersion == AR_SREV_2413 || IS_2316(ah))
364 #define IS_5424(ah) \
365 (AH_PRIVATE(ah)->ah_macVersion == AR_SREV_5424 || \
366 (AH_PRIVATE(ah)->ah_macVersion == AR_SREV_5413 && \
367 AH_PRIVATE(ah)->ah_macRev <= AR_SREV_D2PLUS_MS))
368 #define IS_5413(ah) \
369 (AH_PRIVATE(ah)->ah_macVersion == AR_SREV_5413 || IS_5424(ah))
370 #define IS_2425(ah) \
371 (AH_PRIVATE(ah)->ah_macVersion == AR_SREV_2425)
372 #define IS_2417(ah) \
373 ((AH_PRIVATE(ah)->ah_macVersion) == AR_SREV_2417)
374 #define IS_HB63(ah) (AH5212(ah)->ah_isHb63 == AH_TRUE)
375
376 #define IS_PCIE(ah) (IS_5424(ah) || IS_2425(ah))
377
378 #define ar5212RfDetach(ah) do { \
379 if (AH5212(ah)->ah_rfHal != AH_NULL) \
380 AH5212(ah)->ah_rfHal->rfDetach(ah); \
381 } while (0)
382 #define ar5212GetRfBank(ah, b) \
383 AH5212(ah)->ah_rfHal->getRfBank(ah, b)
384
385 /*
386 * Hack macros for Nala/San: 11b is handled
387 * using 11g; flip the channel flags to accomplish this.
388 */
389 #define SAVE_CCK(_ah, _chan, _flag) do { \
390 if ((IS_2425(_ah) || IS_2417(_ah)) && \
391 (((_chan)->channelFlags) & CHANNEL_CCK)) { \
392 (_chan)->channelFlags &= ~CHANNEL_CCK; \
393 (_chan)->channelFlags |= CHANNEL_OFDM; \
394 (_flag) = AH_TRUE; \
395 } \
396 } while (0)
397 #define RESTORE_CCK(_ah, _chan, _flag) do { \
398 if ((IS_2425(_ah) || IS_2417(_ah)) && (_flag) == AH_TRUE) {\
399 (_chan)->channelFlags &= ~CHANNEL_OFDM; \
400 (_chan)->channelFlags |= CHANNEL_CCK; \
401 } \
402 } while (0)
403
404 extern HAL_BOOL ar5111RfAttach(struct ath_hal *, HAL_STATUS *);
405 extern HAL_BOOL ar5112RfAttach(struct ath_hal *, HAL_STATUS *);
406 extern HAL_BOOL ar2413RfAttach(struct ath_hal *, HAL_STATUS *);
407 extern HAL_BOOL ar5413RfAttach(struct ath_hal *, HAL_STATUS *);
408 extern HAL_BOOL ar2316RfAttach(struct ath_hal *, HAL_STATUS *);
409 extern HAL_BOOL ar2317RfAttach(struct ath_hal *, HAL_STATUS *);
410 extern HAL_BOOL ar2425RfAttach(struct ath_hal *, HAL_STATUS *);
411
412 struct ath_hal;
413
414 extern uint32_t ar5212GetRadioRev(struct ath_hal *ah);
415 extern void ar5212InitState(struct ath_hal_5212 *, uint16_t devid, HAL_SOFTC,
416 HAL_BUS_TAG st, HAL_BUS_HANDLE sh, HAL_STATUS *status);
417 extern struct ath_hal * ar5212Attach(uint16_t devid, HAL_SOFTC sc,
418 HAL_BUS_TAG st, HAL_BUS_HANDLE sh, HAL_STATUS *status);
419 extern void ar5212Detach(struct ath_hal *ah);
420 extern HAL_BOOL ar5212ChipTest(struct ath_hal *ah);
421 extern HAL_BOOL ar5212GetChannelEdges(struct ath_hal *ah,
422 uint16_t flags, uint16_t *low, uint16_t *high);
423 extern HAL_BOOL ar5212FillCapabilityInfo(struct ath_hal *ah);
424
425 extern void ar5212SetBeaconTimers(struct ath_hal *ah,
426 const HAL_BEACON_TIMERS *);
427 extern void ar5212BeaconInit(struct ath_hal *ah,
428 uint32_t next_beacon, uint32_t beacon_period);
429 extern void ar5212ResetStaBeaconTimers(struct ath_hal *ah);
430 extern void ar5212SetStaBeaconTimers(struct ath_hal *ah,
431 const HAL_BEACON_STATE *);
432
433 extern HAL_BOOL ar5212IsInterruptPending(struct ath_hal *ah);
434 extern HAL_BOOL ar5212GetPendingInterrupts(struct ath_hal *ah, HAL_INT *);
435 extern HAL_INT ar5212GetInterrupts(struct ath_hal *ah);
436 extern HAL_INT ar5212SetInterrupts(struct ath_hal *ah, HAL_INT ints);
437
438 extern uint32_t ar5212GetKeyCacheSize(struct ath_hal *);
439 extern HAL_BOOL ar5212IsKeyCacheEntryValid(struct ath_hal *, uint16_t entry);
440 extern HAL_BOOL ar5212ResetKeyCacheEntry(struct ath_hal *ah, uint16_t entry);
441 extern HAL_BOOL ar5212SetKeyCacheEntryMac(struct ath_hal *,
442 uint16_t entry, const uint8_t *mac);
443 extern HAL_BOOL ar5212SetKeyCacheEntry(struct ath_hal *ah, uint16_t entry,
444 const HAL_KEYVAL *k, const uint8_t *mac, int xorKey);
445
446 extern void ar5212GetMacAddress(struct ath_hal *ah, uint8_t *mac);
447 extern HAL_BOOL ar5212SetMacAddress(struct ath_hal *ah, const uint8_t *);
448 extern void ar5212GetBssIdMask(struct ath_hal *ah, uint8_t *mac);
449 extern HAL_BOOL ar5212SetBssIdMask(struct ath_hal *, const uint8_t *);
450 extern HAL_BOOL ar5212EepromRead(struct ath_hal *, u_int off, uint16_t *data);
451 extern HAL_BOOL ar5212EepromWrite(struct ath_hal *, u_int off, uint16_t data);
452 extern HAL_BOOL ar5212SetRegulatoryDomain(struct ath_hal *ah,
453 uint16_t regDomain, HAL_STATUS *stats);
454 extern u_int ar5212GetWirelessModes(struct ath_hal *ah);
455 extern void ar5212EnableRfKill(struct ath_hal *);
456 extern HAL_BOOL ar5212GpioCfgOutput(struct ath_hal *, uint32_t gpio);
457 extern HAL_BOOL ar5212GpioCfgInput(struct ath_hal *, uint32_t gpio);
458 extern HAL_BOOL ar5212GpioSet(struct ath_hal *, uint32_t gpio, uint32_t val);
459 extern uint32_t ar5212GpioGet(struct ath_hal *ah, uint32_t gpio);
460 extern void ar5212GpioSetIntr(struct ath_hal *ah, u_int, uint32_t ilevel);
461 extern void ar5212SetLedState(struct ath_hal *ah, HAL_LED_STATE state);
462 extern void ar5212WriteAssocid(struct ath_hal *ah, const uint8_t *bssid,
463 uint16_t assocId);
464 extern uint32_t ar5212GetTsf32(struct ath_hal *ah);
465 extern uint64_t ar5212GetTsf64(struct ath_hal *ah);
466 extern void ar5212ResetTsf(struct ath_hal *ah);
467 extern void ar5212SetBasicRate(struct ath_hal *ah, HAL_RATE_SET *pSet);
468 extern uint32_t ar5212GetRandomSeed(struct ath_hal *ah);
469 extern HAL_BOOL ar5212DetectCardPresent(struct ath_hal *ah);
470 extern void ar5212EnableMibCounters(struct ath_hal *);
471 extern void ar5212DisableMibCounters(struct ath_hal *);
472 extern void ar5212UpdateMibCounters(struct ath_hal *ah, HAL_MIB_STATS* stats);
473 extern HAL_BOOL ar5212IsJapanChannelSpreadSupported(struct ath_hal *ah);
474 extern uint32_t ar5212GetCurRssi(struct ath_hal *ah);
475 extern u_int ar5212GetDefAntenna(struct ath_hal *ah);
476 extern void ar5212SetDefAntenna(struct ath_hal *ah, u_int antenna);
477 extern HAL_ANT_SETTING ar5212GetAntennaSwitch(struct ath_hal *);
478 extern HAL_BOOL ar5212SetAntennaSwitch(struct ath_hal *, HAL_ANT_SETTING);
479 extern HAL_BOOL ar5212IsSleepAfterBeaconBroken(struct ath_hal *ah);
480 extern HAL_BOOL ar5212SetSifsTime(struct ath_hal *, u_int);
481 extern u_int ar5212GetSifsTime(struct ath_hal *);
482 extern HAL_BOOL ar5212SetSlotTime(struct ath_hal *, u_int);
483 extern u_int ar5212GetSlotTime(struct ath_hal *);
484 extern HAL_BOOL ar5212SetAckTimeout(struct ath_hal *, u_int);
485 extern u_int ar5212GetAckTimeout(struct ath_hal *);
486 extern HAL_BOOL ar5212SetAckCTSRate(struct ath_hal *, u_int);
487 extern u_int ar5212GetAckCTSRate(struct ath_hal *);
488 extern HAL_BOOL ar5212SetCTSTimeout(struct ath_hal *, u_int);
489 extern u_int ar5212GetCTSTimeout(struct ath_hal *);
490 extern HAL_BOOL ar5212SetDecompMask(struct ath_hal *, uint16_t, int);
491 void ar5212SetCoverageClass(struct ath_hal *, uint8_t, int);
492 extern void ar5212SetPCUConfig(struct ath_hal *);
493 extern HAL_BOOL ar5212Use32KHzclock(struct ath_hal *ah, HAL_OPMODE opmode);
494 extern void ar5212SetupClock(struct ath_hal *ah, HAL_OPMODE opmode);
495 extern void ar5212RestoreClock(struct ath_hal *ah, HAL_OPMODE opmode);
496 extern int16_t ar5212GetNfAdjust(struct ath_hal *,
497 const HAL_CHANNEL_INTERNAL *);
498 extern void ar5212SetCompRegs(struct ath_hal *ah);
499 extern HAL_STATUS ar5212GetCapability(struct ath_hal *, HAL_CAPABILITY_TYPE,
500 uint32_t, uint32_t *);
501 extern HAL_BOOL ar5212SetCapability(struct ath_hal *, HAL_CAPABILITY_TYPE,
502 uint32_t, uint32_t, HAL_STATUS *);
503 extern HAL_BOOL ar5212GetDiagState(struct ath_hal *ah, int request,
504 const void *args, uint32_t argsize,
505 void **result, uint32_t *resultsize);
506
507 extern HAL_BOOL ar5212SetPowerMode(struct ath_hal *ah, HAL_POWER_MODE mode,
508 int setChip);
509 extern HAL_POWER_MODE ar5212GetPowerMode(struct ath_hal *ah);
510 extern HAL_BOOL ar5212GetPowerStatus(struct ath_hal *ah);
511
512 extern uint32_t ar5212GetRxDP(struct ath_hal *ath);
513 extern void ar5212SetRxDP(struct ath_hal *ah, uint32_t rxdp);
514 extern void ar5212EnableReceive(struct ath_hal *ah);
515 extern HAL_BOOL ar5212StopDmaReceive(struct ath_hal *ah);
516 extern void ar5212StartPcuReceive(struct ath_hal *ah);
517 extern void ar5212StopPcuReceive(struct ath_hal *ah);
518 extern void ar5212SetMulticastFilter(struct ath_hal *ah,
519 uint32_t filter0, uint32_t filter1);
520 extern HAL_BOOL ar5212ClrMulticastFilterIndex(struct ath_hal *, uint32_t ix);
521 extern HAL_BOOL ar5212SetMulticastFilterIndex(struct ath_hal *, uint32_t ix);
522 extern uint32_t ar5212GetRxFilter(struct ath_hal *ah);
523 extern void ar5212SetRxFilter(struct ath_hal *ah, uint32_t bits);
524 extern HAL_BOOL ar5212SetupRxDesc(struct ath_hal *,
525 struct ath_desc *, uint32_t size, u_int flags);
526 extern HAL_STATUS ar5212ProcRxDesc(struct ath_hal *ah, struct ath_desc *,
527 uint32_t, struct ath_desc *, uint64_t,
528 struct ath_rx_status *);
529
530 extern HAL_BOOL ar5212Reset(struct ath_hal *ah, HAL_OPMODE opmode,
531 HAL_CHANNEL *chan, HAL_BOOL bChannelChange, HAL_STATUS *status);
532 extern HAL_BOOL ar5212SetChannel(struct ath_hal *, HAL_CHANNEL_INTERNAL *);
533 extern void ar5212SetOperatingMode(struct ath_hal *ah, int opmode);
534 extern HAL_BOOL ar5212PhyDisable(struct ath_hal *ah);
535 extern HAL_BOOL ar5212Disable(struct ath_hal *ah);
536 extern HAL_BOOL ar5212ChipReset(struct ath_hal *ah, HAL_CHANNEL *);
537 extern HAL_BOOL ar5212PerCalibration(struct ath_hal *ah, HAL_CHANNEL *chan, HAL_BOOL *isIQdone);
538 extern int16_t ar5212GetNoiseFloor(struct ath_hal *ah);
539 extern void ar5212InitNfCalHistBuffer(struct ath_hal *);
540 extern int16_t ar5212GetNfHistMid(const int16_t calData[]);
541 extern void ar5212SetSpurMitigation(struct ath_hal *, HAL_CHANNEL_INTERNAL *);
542 extern HAL_BOOL ar5212SetAntennaSwitchInternal(struct ath_hal *ah,
543 HAL_ANT_SETTING settings, const HAL_CHANNEL_INTERNAL *ichan);
544 extern HAL_BOOL ar5212SetTxPowerLimit(struct ath_hal *ah, uint32_t limit);
545 extern HAL_BOOL ar5212GetChipPowerLimits(struct ath_hal *ah,
546 HAL_CHANNEL *chans, uint32_t nchans);
547 extern void ar5212InitializeGainValues(struct ath_hal *);
548 extern HAL_RFGAIN ar5212GetRfgain(struct ath_hal *ah);
549
550 extern HAL_BOOL ar5212UpdateTxTrigLevel(struct ath_hal *,
551 HAL_BOOL IncTrigLevel);
552 extern HAL_BOOL ar5212SetTxQueueProps(struct ath_hal *ah, int q,
553 const HAL_TXQ_INFO *qInfo);
554 extern HAL_BOOL ar5212GetTxQueueProps(struct ath_hal *ah, int q,
555 HAL_TXQ_INFO *qInfo);
556 extern int ar5212SetupTxQueue(struct ath_hal *ah, HAL_TX_QUEUE type,
557 const HAL_TXQ_INFO *qInfo);
558 extern HAL_BOOL ar5212ReleaseTxQueue(struct ath_hal *ah, u_int q);
559 extern HAL_BOOL ar5212ResetTxQueue(struct ath_hal *ah, u_int q);
560 extern uint32_t ar5212GetTxDP(struct ath_hal *ah, u_int q);
561 extern HAL_BOOL ar5212SetTxDP(struct ath_hal *ah, u_int q, uint32_t txdp);
562 extern HAL_BOOL ar5212StartTxDma(struct ath_hal *ah, u_int q);
563 extern uint32_t ar5212NumTxPending(struct ath_hal *ah, u_int q);
564 extern HAL_BOOL ar5212StopTxDma(struct ath_hal *ah, u_int q);
565 extern HAL_BOOL ar5212SetupTxDesc(struct ath_hal *ah, struct ath_desc *ds,
566 u_int pktLen, u_int hdrLen, HAL_PKT_TYPE type, u_int txPower,
567 u_int txRate0, u_int txTries0,
568 u_int keyIx, u_int antMode, u_int flags,
569 u_int rtsctsRate, u_int rtsctsDuration,
570 u_int compicvLen, u_int compivLen, u_int comp);
571 extern HAL_BOOL ar5212SetupXTxDesc(struct ath_hal *, struct ath_desc *,
572 u_int txRate1, u_int txRetries1,
573 u_int txRate2, u_int txRetries2,
574 u_int txRate3, u_int txRetries3);
575 extern HAL_BOOL ar5212FillTxDesc(struct ath_hal *ah, struct ath_desc *ds,
576 u_int segLen, HAL_BOOL firstSeg, HAL_BOOL lastSeg,
577 const struct ath_desc *ds0);
578 extern HAL_STATUS ar5212ProcTxDesc(struct ath_hal *ah,
579 struct ath_desc *, struct ath_tx_status *);
580 extern void ar5212GetTxIntrQueue(struct ath_hal *ah, uint32_t *);
581 extern void ar5212IntrReqTxDesc(struct ath_hal *ah, struct ath_desc *);
582
583 extern const HAL_RATE_TABLE *ar5212GetRateTable(struct ath_hal *, u_int mode);
584
585 extern void ar5212AniAttach(struct ath_hal *, const struct ar5212AniParams *,
586 const struct ar5212AniParams *, HAL_BOOL ena);
587 extern void ar5212AniDetach(struct ath_hal *);
588 extern struct ar5212AniState *ar5212AniGetCurrentState(struct ath_hal *);
589 extern struct ar5212Stats *ar5212AniGetCurrentStats(struct ath_hal *);
590 extern HAL_BOOL ar5212AniControl(struct ath_hal *, HAL_ANI_CMD cmd, int param);
591 extern HAL_BOOL ar5212AniSetParams(struct ath_hal *,
592 const struct ar5212AniParams *, const struct ar5212AniParams *);
593 struct ath_rx_status;
594 extern void ar5212AniPhyErrReport(struct ath_hal *ah,
595 const struct ath_rx_status *rs);
596 extern void ar5212ProcessMibIntr(struct ath_hal *, const HAL_NODE_STATS *);
597 extern void ar5212AniPoll(struct ath_hal *, const HAL_NODE_STATS *,
598 HAL_CHANNEL *);
599 extern void ar5212AniReset(struct ath_hal *, HAL_CHANNEL_INTERNAL *,
600 HAL_OPMODE, int);
601 #endif /* _ATH_AR5212_H_ */
Mirror of AROS' svn.