workbench/devs/networks/atheros5000/hal/ar5416/ar5416_interrupts.c

   1 /*
   2  * Copyright (c) 2002-2008 Sam Leffler, Errno Consulting
   3  * Copyright (c) 2002-2008 Atheros Communications, Inc.
   4  *
   5  * Permission to use, copy, modify, and/or distribute this software for any
   6  * purpose with or without fee is hereby granted, provided that the above
   7  * copyright notice and this permission notice appear in all copies.
   8  *
   9  * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
  10  * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
  11  * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
  12  * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
  13  * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
  14  * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF
  15  * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
  16  *
  17  * $Id$
  18  */
  19 #include "opt_ah.h"
  20
  21 #ifdef AH_SUPPORT_AR5416
  22
  23 #include "ah.h"
  24 #include "ah_internal.h"
  25
  26 #include "ar5416/ar5416.h"
  27 #include "ar5416/ar5416reg.h"
  28
  29 /*
  30  * Checks to see if an interrupt is pending on our NIC
  31  *
  32  * Returns: TRUE    if an interrupt is pending
  33  *          FALSE   if not
  34  */
  35 HAL_BOOL
  36 ar5416IsInterruptPending(struct ath_hal *ah)
  37 {
  38         uint32_t isr;
  39         /*
  40          * Some platforms trigger our ISR before applying power to
  41          * the card, so make sure the INTPEND is really 1, not 0xffffffff.
  42          */
  43         isr = OS_REG_READ(ah, AR_INTR_ASYNC_CAUSE);
  44         if (isr != AR_INTR_SPURIOUS && (isr & AR_INTR_MAC_IRQ) != 0)
  45                 return AH_TRUE;
  46
  47         isr = OS_REG_READ(ah, AR_INTR_SYNC_CAUSE);
  48         if (isr != AR_INTR_SPURIOUS && (isr & AR_INTR_SYNC_DEFAULT))
  49                 return AH_TRUE;
  50
  51         return AH_FALSE;
  52 }
  53
  54 /*
  55  * Reads the Interrupt Status Register value from the NIC, thus deasserting
  56  * the interrupt line, and returns both the masked and unmasked mapped ISR
  57  * values.  The value returned is mapped to abstract the hw-specific bit
  58  * locations in the Interrupt Status Register.
  59  *
  60  * Returns: A hardware-abstracted bitmap of all non-masked-out
  61  *          interrupts pending, as well as an unmasked value
  62  */
  63 HAL_BOOL
  64 ar5416GetPendingInterrupts(struct ath_hal *ah, HAL_INT *masked)
  65 {
  66         uint32_t isr, isr0, isr1, sync_cause;
  67
  68         /*
  69          * Verify there's a mac interrupt and the RTC is on.
  70          */
  71         if ((OS_REG_READ(ah, AR_INTR_ASYNC_CAUSE) & AR_INTR_MAC_IRQ) &&
  72             (OS_REG_READ(ah, AR_RTC_STATUS) & AR_RTC_STATUS_M) == AR_RTC_STATUS_ON)
  73                 isr = OS_REG_READ(ah, AR_ISR);
  74         else
  75                 isr = 0;
  76         sync_cause = OS_REG_READ(ah, AR_INTR_SYNC_CAUSE);
  77         sync_cause &= AR_INTR_SYNC_DEFAULT;
  78         if (isr == 0 && sync_cause == 0) {
  79                 *masked = 0;
  80                 return AH_FALSE;
  81         }
  82
  83         if (isr != 0) {
  84                 struct ath_hal_5212 *ahp = AH5212(ah);
  85                 uint32_t mask2;
  86
  87                 mask2 = 0;
  88                 if (isr & AR_ISR_BCNMISC) {
  89                         uint32_t isr2 = OS_REG_READ(ah, AR_ISR_S2);
  90                         if (isr2 & AR_ISR_S2_TIM)
  91                                 mask2 |= HAL_INT_TIM;
  92                         if (isr2 & AR_ISR_S2_DTIM)
  93                                 mask2 |= HAL_INT_DTIM;
  94                         if (isr2 & AR_ISR_S2_DTIMSYNC)
  95                                 mask2 |= HAL_INT_DTIMSYNC;
  96                         if (isr2 & (AR_ISR_S2_CABEND ))
  97                                 mask2 |= HAL_INT_CABEND;
  98                         if (isr2 & AR_ISR_S2_GTT)
  99                                 mask2 |= HAL_INT_GTT;
 100                         if (isr2 & AR_ISR_S2_CST)
 101                                 mask2 |= HAL_INT_CST;
 102                         if (isr2 & AR_ISR_S2_TSFOOR)
 103                                 mask2 |= HAL_INT_TSFOOR;
 104                 }
 105
 106                 isr = OS_REG_READ(ah, AR_ISR_RAC);
 107                 if (isr == 0xffffffff) {
 108                         *masked = 0;
 109                         return AH_FALSE;;
 110                 }
 111
 112                 *masked = isr & HAL_INT_COMMON;
 113                 if (isr & (AR_ISR_RXOK | AR_ISR_RXERR))
 114                         *masked |= HAL_INT_RX;
 115                 if (isr & (AR_ISR_TXOK | AR_ISR_TXDESC | AR_ISR_TXERR | AR_ISR_TXEOL)) {
 116                         *masked |= HAL_INT_TX;
 117                         isr0 = OS_REG_READ(ah, AR_ISR_S0_S);
 118                         ahp->ah_intrTxqs |= MS(isr0, AR_ISR_S0_QCU_TXOK);
 119                         ahp->ah_intrTxqs |= MS(isr0, AR_ISR_S0_QCU_TXDESC);
 120                         isr1 = OS_REG_READ(ah, AR_ISR_S1_S);
 121                         ahp->ah_intrTxqs |= MS(isr1, AR_ISR_S1_QCU_TXERR);
 122                         ahp->ah_intrTxqs |= MS(isr1, AR_ISR_S1_QCU_TXEOL);
 123                 }
 124
 125                 /* Interrupt Mitigation on AR5416 */
 126 #ifdef AR5416_INT_MITIGATION
 127                 if (isr & (AR_ISR_RXMINTR | AR_ISR_RXINTM))
 128                         *masked |= HAL_INT_RX;
 129                 if (isr & (AR_ISR_TXMINTR | AR_ISR_TXINTM))
 130                         *masked |= HAL_INT_TX;
 131 #endif
 132                 *masked |= mask2;
 133         }
 134         if (sync_cause != 0) {
 135                 if (sync_cause & (AR_INTR_SYNC_HOST1_FATAL | AR_INTR_SYNC_HOST1_PERR)) {
 136                         *masked |= HAL_INT_FATAL;
 137                 }
 138                 if (sync_cause & AR_INTR_SYNC_RADM_CPL_TIMEOUT) {
 139                         HALDEBUG(ah, HAL_DEBUG_ANY, "%s: RADM CPL timeout\n",
 140                             __func__);
 141                         OS_REG_WRITE(ah, AR_RC, AR_RC_HOSTIF);
 142                         OS_REG_WRITE(ah, AR_RC, 0);
 143                         *masked |= HAL_INT_FATAL;
 144                 }
 145                 /*
 146                  * On fatal errors collect ISR state for debugging.
 147                  */
 148                 if (*masked & HAL_INT_FATAL) {
 149                         AH_PRIVATE(ah)->ah_fatalState[0] = isr;
 150                         AH_PRIVATE(ah)->ah_fatalState[1] = sync_cause;
 151                         HALDEBUG(ah, HAL_DEBUG_ANY,
 152                             "%s: fatal error, ISR_RAC 0x%x SYNC_CAUSE 0x%x\n",
 153                             __func__, isr, sync_cause);
 154                 }
 155
 156                 OS_REG_WRITE(ah, AR_INTR_SYNC_CAUSE_CLR, sync_cause);
 157                 /* NB: flush write */
 158                 (void) OS_REG_READ(ah, AR_INTR_SYNC_CAUSE_CLR);
 159         }
 160         return AH_TRUE;
 161 }
 162
 163 /*
 164  * Atomically enables NIC interrupts.  Interrupts are passed in
 165  * via the enumerated bitmask in ints.
 166  */
 167 HAL_INT
 168 ar5416SetInterrupts(struct ath_hal *ah, HAL_INT ints)
 169 {
 170         struct ath_hal_5212 *ahp = AH5212(ah);
 171         uint32_t omask = ahp->ah_maskReg;
 172         uint32_t mask,mask2;
 173
 174         HALDEBUG(ah, HAL_DEBUG_INTERRUPT, "%s: 0x%x => 0x%x\n",
 175             __func__, omask, ints);
 176
 177         if (omask & HAL_INT_GLOBAL) {
 178                 HALDEBUG(ah, HAL_DEBUG_INTERRUPT, "%s: disable IER\n", __func__);
 179                 OS_REG_WRITE(ah, AR_IER, AR_IER_DISABLE);
 180                 (void) OS_REG_READ(ah, AR_IER);
 181
 182                 OS_REG_WRITE(ah, AR_INTR_ASYNC_ENABLE, 0);
 183                 (void) OS_REG_READ(ah, AR_INTR_ASYNC_ENABLE);
 184
 185                 OS_REG_WRITE(ah, AR_INTR_SYNC_ENABLE, 0);
 186                 (void) OS_REG_READ(ah, AR_INTR_SYNC_ENABLE);
 187         }
 188
 189         mask = ints & HAL_INT_COMMON;
 190         mask2 = 0;
 191
 192         if (ints & HAL_INT_TX) {
 193                 if (ahp->ah_txOkInterruptMask)
 194                         mask |= AR_IMR_TXOK;
 195                 if (ahp->ah_txErrInterruptMask)
 196                         mask |= AR_IMR_TXERR;
 197                 if (ahp->ah_txDescInterruptMask)
 198                         mask |= AR_IMR_TXDESC;
 199                 if (ahp->ah_txEolInterruptMask)
 200                         mask |= AR_IMR_TXEOL;
 201         }
 202         if (ints & HAL_INT_RX)
 203                 mask |= AR_IMR_RXOK | AR_IMR_RXERR | AR_IMR_RXDESC;
 204 #ifdef AR5416_INT_MITIGATION
 205         /*
 206          * Overwrite default mask if Interrupt mitigation
 207          * is specified for AR5416
 208          */
 209         mask = ints & HAL_INT_COMMON;
 210         if (ints & HAL_INT_TX)
 211                 mask |= AR_IMR_TXMINTR | AR_IMR_TXINTM;
 212         if (ints & HAL_INT_RX)
 213                 mask |= AR_IMR_RXERR | AR_IMR_RXMINTR | AR_IMR_RXINTM;
 214 #endif
 215         if (ints & (HAL_INT_BMISC)) {
 216                 mask |= AR_IMR_BCNMISC;
 217                 if (ints & HAL_INT_TIM)
 218                         mask2 |= AR_IMR_S2_TIM;
 219                 if (ints & HAL_INT_DTIM)
 220                         mask2 |= AR_IMR_S2_DTIM;
 221                 if (ints & HAL_INT_DTIMSYNC)
 222                         mask2 |= AR_IMR_S2_DTIMSYNC;
 223                 if (ints & HAL_INT_CABEND)
 224                         mask2 |= (AR_IMR_S2_CABEND );
 225                 if (ints & HAL_INT_GTT)
 226                         mask2 |= AR_IMR_S2_GTT;
 227                 if (ints & HAL_INT_CST)
 228                         mask2 |= AR_IMR_S2_CST;
 229                 if (ints & HAL_INT_TSFOOR)
 230                         mask2 |= AR_IMR_S2_TSFOOR;
 231         }
 232
 233         /* Write the new IMR and store off our SW copy. */
 234         HALDEBUG(ah, HAL_DEBUG_INTERRUPT, "%s: new IMR 0x%x\n", __func__, mask);
 235         OS_REG_WRITE(ah, AR_IMR, mask);
 236         mask = OS_REG_READ(ah, AR_IMR_S2) & ~(AR_IMR_S2_TIM |
 237                                         AR_IMR_S2_DTIM |
 238                                         AR_IMR_S2_DTIMSYNC |
 239                                         AR_IMR_S2_CABEND |
 240                                         AR_IMR_S2_CABTO  |
 241                                         AR_IMR_S2_TSFOOR |
 242                                         AR_IMR_S2_GTT |
 243                                         AR_IMR_S2_CST);
 244         OS_REG_WRITE(ah, AR_IMR_S2, mask | mask2);
 245
 246         ahp->ah_maskReg = ints;
 247
 248         /* Re-enable interrupts if they were enabled before. */
 249         if (ints & HAL_INT_GLOBAL) {
 250                 HALDEBUG(ah, HAL_DEBUG_INTERRUPT, "%s: enable IER\n", __func__);
 251                 OS_REG_WRITE(ah, AR_IER, AR_IER_ENABLE);
 252
 253                 OS_REG_WRITE(ah, AR_INTR_ASYNC_ENABLE, AR_INTR_MAC_IRQ);
 254                 OS_REG_WRITE(ah, AR_INTR_ASYNC_MASK, AR_INTR_MAC_IRQ);
 255
 256                 OS_REG_WRITE(ah, AR_INTR_SYNC_ENABLE, AR_INTR_SYNC_DEFAULT);
 257                 OS_REG_WRITE(ah, AR_INTR_SYNC_MASK, AR_INTR_SYNC_DEFAULT);
 258         }
 259
 260         return omask;
 261 }
 262 #endif /* AH_SUPPORT_AR5416 */