workbench/devs/networks/atheros5000/unit.c

   1 /*
   2
   3 Copyright (C) 2001-2012 Neil Cafferkey
   4
   5 This program is free software; you can redistribute it and/or modify
   6 it under the terms of the GNU General Public License as published by
   7 the Free Software Foundation; either version 2 of the License, or
   8 (at your option) any later version.
   9
  10 This program is distributed in the hope that it will be useful, but
  11 WITHOUT ANY WARRANTY; without even the implied warranty of
  12 MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
  13 General Public License for more details.
  14
  15 You should have received a copy of the GNU General Public License
  16 along with this program; if not, write to the Free Software
  17 Foundation, Inc., 59 Temple Place - Suite 330, Boston,
  18 MA 02111-1307, USA.
  19
  20 */
  21
  22
  23 #include <exec/memory.h>
  24 #include <exec/execbase.h>
  25 #include <exec/errors.h>
  26
  27 #include <proto/exec.h>
  28 #ifndef __amigaos4__
  29 #include <proto/alib.h>
  30 #else
  31 #include <clib/alib_protos.h>
  32 #endif
  33 #include <proto/utility.h>
  34 #include <proto/dos.h>
  35 #include <proto/timer.h>
  36
  37 #include "device.h"
  38
  39 #include "unit_protos.h"
  40 #include "request_protos.h"
  41 #include "encryption_protos.h"
  42 #include "hal/ah.h"
  43 #include "hal/ah_desc.h"
  44
  45
  46 #define TASK_PRIORITY 0
  47 #define STACK_SIZE 4096
  48 #define INT_MASK \
  49    (HAL_INT_GLOBAL | HAL_INT_TX | HAL_INT_TXDESC | HAL_INT_RX \
  50    | HAL_INT_RXEOL)
  51 #define TX_POWER (20 << 1)
  52 #define TX_TRIES 11
  53 #define G_MGMT_RATE 2000
  54 #define B_MGMT_RATE 1000
  55 #define FRAME_BUFFER_SIZE (WIFI_FRM_DATA + SNAP_HEADERSIZE \
  56    + 2 * ETH_MTU + EIV_SIZE + ICV_SIZE + MIC_SIZE + FCS_SIZE + 4)
  57 #define MAX_CHANNEL_COUNT 100
  58
  59 #ifndef AbsExecBase
  60 #define AbsExecBase sys_base
  61 #endif
  62
  63 static struct AddressRange *FindMulticastRange(struct DevUnit *unit,
  64    ULONG lower_bound_left, UWORD lower_bound_right, ULONG upper_bound_left,
  65    UWORD upper_bound_right, struct DevBase *base);
  66 static VOID SetMulticast(struct DevUnit *unit, struct DevBase *base);
  67 static BOOL StatusInt(REG(a1, struct DevUnit *unit), REG(a6, APTR int_code));
  68 static VOID RXInt(REG(a1, struct DevUnit *unit), REG(a6, APTR int_code));
  69 static UBYTE *GetRXBuffer(struct DevUnit *unit, const UBYTE *address,
  70    UWORD frag_no, UWORD *buffer_no, struct DevBase *base);
  71 static VOID DistributeRXPacket(struct DevUnit *unit, UBYTE *frame,
  72    struct DevBase *base);
  73 static VOID CopyPacket(struct DevUnit *unit, struct IOSana2Req *request,
  74    UWORD packet_size, UWORD packet_type, UBYTE *buffer,
  75    struct DevBase *base);
  76 static BOOL AddressFilter(struct DevUnit *unit, UBYTE *address,
  77    struct DevBase *base);
  78 static VOID DistributeMgmtFrame(struct DevUnit *unit, UBYTE *frame,
  79    UWORD frame_size, struct DevBase *base);
  80 static VOID TXInt(REG(a1, struct DevUnit *unit), REG(a6, APTR int_code));
  81 static VOID TXEndInt(REG(a1, struct DevUnit *unit), REG(a6, APTR int_code));
  82 static VOID MgmtTXInt(REG(a1, struct DevUnit *unit),
  83    REG(a6, APTR int_code));
  84 static VOID MgmtTXEndInt(REG(a1, struct DevUnit *unit),
  85    REG(a6, APTR int_code));
  86 static VOID ResetHandler(REG(a1, struct DevUnit *unit),
  87    REG(a6, APTR int_code));
  88 static VOID ReportEvents(struct DevUnit *unit, ULONG events,
  89    struct DevBase *base);
  90 static VOID UnitTask(struct ExecBase *sys_base);
  91
  92
  93 static const UBYTE snap_template[] = {0xaa, 0xaa, 0x03, 0x00, 0x00, 0x00};
  94 #if !defined(__AROS__)
  95 static const UBYTE broadcast_address[] = {0xff, 0xff, 0xff, 0xff, 0xff, 0xff};
  96 #endif
  97 static const ULONG g_retry_rates[] = {54000, 36000, 18000, 2000};
  98 static const ULONG b_retry_rates[] = {11000, 5500, 2000, 1000};
  99
 100
 101 #ifdef __amigaos4__
 102 #undef AddTask
 103 #define AddTask(task, initial_pc, final_pc) \
 104    IExec->AddTask(task, initial_pc, final_pc, NULL)
 105 #endif
 106 #ifdef __MORPHOS__
 107 static const struct EmulLibEntry mos_task_trap =
 108 {
 109    TRAP_LIB,
 110    0,
 111    (APTR)UnitTask
 112 };
 113 #define UnitTask &mos_task_trap
 114 #endif
 115 #ifdef __AROS__
 116 #undef AddTask
 117 #define AddTask(task, initial_pc, final_pc) \
 118    ({ \
 119       struct TagItem _task_tags[] = \
 120          {{TASKTAG_ARG1, (IPTR)SysBase}, {TAG_END, 0}}; \
 121       NewAddTask(task, initial_pc, final_pc, _task_tags); \
 122    })
 123 #endif
 124
 125
 126
 127 /****i* atheros5000.device/CreateUnit **************************************
 128 *
 129 *   NAME
 130 *       CreateUnit -- Create a unit.
 131 *
 132 *   SYNOPSIS
 133 *       unit = CreateUnit(index, io_base, id, card,
 134 *           io_tags, bus)
 135 *
 136 *       struct DevUnit *CreateUnit(ULONG, APTR, UWORD, APTR,
 137 *           struct TagItem *, UWORD);
 138 *
 139 *   FUNCTION
 140 *       Creates a new unit.
 141 *
 142 ****************************************************************************
 143 *
 144 */
 145
 146 struct DevUnit *CreateUnit(ULONG index, APTR io_base, UWORD id, APTR card,
 147    struct TagItem *io_tags, UWORD bus, struct DevBase *base)
 148 {
 149    BOOL success = TRUE;
 150    struct DevUnit *unit;
 151    struct Task *task;
 152    struct MsgPort *port;
 153    UWORD i;
 154    struct ath_desc *tx_desc, *rx_desc;
 155    ULONG dma_size;
 156    APTR stack;
 157    HAL_STATUS hal_status;
 158
 159    unit = AllocMem(sizeof(struct DevUnit), MEMF_CLEAR | MEMF_PUBLIC);
 160    if(unit == NULL)
 161       success = FALSE;
 162
 163    if(success)
 164    {
 165       /* Initialise lists etc. */
 166
 167       NewList((APTR)&unit->openers);
 168       NewList((APTR)&unit->type_trackers);
 169       NewList((APTR)&unit->multicast_ranges);
 170
 171       unit->index = index;
 172       unit->device = base;
 173       unit->card = card;
 174       unit->bus = bus;
 175
 176       /* Store DMA memory hooks */
 177
 178       unit->AllocDMAMem =
 179          (APTR)GetTagData(IOTAG_AllocDMAMem, (UPINT)NULL, io_tags);
 180       unit->FreeDMAMem =
 181          (APTR)GetTagData(IOTAG_FreeDMAMem, (UPINT)NULL, io_tags);
 182       if(unit->AllocDMAMem == NULL || unit->FreeDMAMem == NULL)
 183          success = FALSE;
 184    }
 185
 186    if(success)
 187    {
 188       /* Initialise HAL */
 189
 190       unit->hal = ath_hal_attach(id, unit, NULL, io_base, &hal_status);
 191
 192       if(unit->hal == NULL)
 193          success = FALSE;
 194    }
 195
 196    if(success)
 197    {
 198       InitSemaphore(&unit->access_lock);
 199
 200       /* Create the message ports for queuing requests */
 201
 202       for(i = 0; i < REQUEST_QUEUE_COUNT; i++)
 203       {
 204          unit->request_ports[i] = port = AllocMem(sizeof(struct MsgPort),
 205             MEMF_PUBLIC | MEMF_CLEAR);
 206          if(port == NULL)
 207             success = FALSE;
 208
 209          if(success)
 210          {
 211             NewList(&port->mp_MsgList);
 212             port->mp_Flags = PA_IGNORE;
 213          }
 214       }
 215
 216       if(success)
 217       {
 218          unit->request_ports[WRITE_QUEUE]->mp_SigTask = &unit->tx_int;
 219          unit->request_ports[MGMT_QUEUE]->mp_SigTask = &unit->mgmt_int;
 220       }
 221
 222       /* Allocate buffers and descriptors */
 223
 224       unit->tx_buffer = AllocVec(ETH_MAXPACKETSIZE, MEMF_PUBLIC);
 225       for(i = 0; i < TX_SLOT_COUNT; i++)
 226       {
 227          unit->tx_buffers[i] =
 228             unit->AllocDMAMem(unit->card, FRAME_BUFFER_SIZE, 4);
 229          if(unit->tx_buffers[i] == NULL)
 230             success = FALSE;
 231       }
 232       for(i = 0; i < MGMT_SLOT_COUNT; i++)
 233       {
 234          unit->mgmt_buffers[i] =
 235             unit->AllocDMAMem(unit->card, FRAME_BUFFER_SIZE, 4);
 236          if(unit->mgmt_buffers[i] == NULL)
 237             success = FALSE;
 238       }
 239       unit->rx_buffer = AllocVec(FRAME_BUFFER_SIZE, MEMF_PUBLIC);
 240       for(i = 0; i < RX_SLOT_COUNT; i++)
 241       {
 242          unit->rx_buffers[i] =
 243             unit->AllocDMAMem(unit->card, FRAME_BUFFER_SIZE, 4);
 244          if(unit->rx_buffers[i] == NULL)
 245             success = FALSE;
 246       }
 247       unit->rx_frames =
 248          AllocVec(FRAME_BUFFER_SIZE * FRAME_BUFFER_COUNT, MEMF_PUBLIC);
 249       for(i = 0; i < FRAME_BUFFER_COUNT; i++)
 250          unit->rx_fragment_nos[i] = -1;
 251       unit->tx_descs = unit->AllocDMAMem(unit->card,
 252          sizeof(struct ath_desc) * TX_SLOT_COUNT, 4);
 253       unit->mgmt_descs = unit->AllocDMAMem(unit->card,
 254          sizeof(struct ath_desc) * MGMT_SLOT_COUNT, 4);
 255       unit->rx_descs = unit->AllocDMAMem(unit->card,
 256          sizeof(struct ath_desc) * RX_SLOT_COUNT, 4);
 257       unit->tx_requests = AllocVec(sizeof(APTR) * TX_SLOT_COUNT,
 258          MEMF_PUBLIC);
 259       unit->mgmt_requests = AllocVec(sizeof(APTR) * MGMT_SLOT_COUNT,
 260          MEMF_PUBLIC);
 261       unit->channels = AllocVec(sizeof(HAL_CHANNEL) * MAX_CHANNEL_COUNT,
 262          MEMF_PUBLIC | MEMF_CLEAR);
 263       if(unit->tx_buffer == NULL
 264          || unit->rx_buffer == NULL
 265          || unit->rx_frames == NULL
 266          || unit->tx_descs == NULL
 267          || unit->mgmt_descs == NULL
 268          || unit->rx_descs == NULL
 269          || unit->tx_requests == NULL
 270          || unit->mgmt_requests == NULL
 271          || unit->channels == NULL)
 272          success = FALSE;
 273    }
 274
 275    if(success)
 276    {
 277       /* Initialise network adapter hardware */
 278
 279       success = InitialiseAdapter(unit, FALSE, base);
 280       unit->flags |= UNITF_HAVEADAPTER;
 281    }
 282
 283    if(success)
 284    {
 285       /* Get physical addresses of DMA structures */
 286
 287       dma_size = sizeof(struct ath_desc) * TX_SLOT_COUNT;
 288       unit->tx_descs_p =
 289          (ULONG)(UPINT)CachePreDMA(unit->tx_descs, &dma_size, 0);
 290       if(dma_size != sizeof(struct ath_desc) * TX_SLOT_COUNT)
 291          success = FALSE;
 292       CachePostDMA(unit->tx_descs, &dma_size, 0);
 293
 294       for(i = 0; i < TX_SLOT_COUNT; i++)
 295       {
 296          dma_size = FRAME_BUFFER_SIZE;
 297          unit->tx_buffers_p[i] =
 298             (ULONG)(UPINT)CachePreDMA(unit->tx_buffers[i], &dma_size, 0);
 299          if(dma_size != FRAME_BUFFER_SIZE)
 300             success = FALSE;
 301          CachePostDMA(unit->tx_buffers[i], &dma_size, 0);
 302       }
 303
 304       dma_size = sizeof(struct ath_desc) * MGMT_SLOT_COUNT;
 305       unit->mgmt_descs_p =
 306          (ULONG)(UPINT)CachePreDMA(unit->mgmt_descs, &dma_size, 0);
 307       if(dma_size != sizeof(struct ath_desc) * MGMT_SLOT_COUNT)
 308          success = FALSE;
 309       CachePostDMA(unit->mgmt_descs, &dma_size, 0);
 310
 311       for(i = 0; i < MGMT_SLOT_COUNT; i++)
 312       {
 313          dma_size = FRAME_BUFFER_SIZE;
 314          unit->mgmt_buffers_p[i] =
 315             (ULONG)(UPINT)CachePreDMA(unit->mgmt_buffers[i], &dma_size, 0);
 316          if(dma_size != FRAME_BUFFER_SIZE)
 317             success = FALSE;
 318          CachePostDMA(unit->mgmt_buffers[i], &dma_size, 0);
 319       }
 320
 321       dma_size = sizeof(struct ath_desc) * RX_SLOT_COUNT;
 322       unit->rx_descs_p =
 323          (ULONG)(UPINT)CachePreDMA(unit->rx_descs, &dma_size, 0);
 324       if(dma_size != sizeof(struct ath_desc) * RX_SLOT_COUNT)
 325          success = FALSE;
 326       CachePostDMA(unit->rx_descs, &dma_size, 0);
 327
 328       for(i = 0; i < RX_SLOT_COUNT; i++)
 329       {
 330          dma_size = FRAME_BUFFER_SIZE;
 331          unit->rx_buffers_p[i] =
 332             (ULONG)(UPINT)CachePreDMA(unit->rx_buffers[i], &dma_size, 0);
 333          if(dma_size != FRAME_BUFFER_SIZE)
 334             success = FALSE;
 335          CachePostDMA(unit->rx_buffers[i], &dma_size, 0);
 336       }
 337
 338       /* Construct TX ring */
 339
 340       for(tx_desc = unit->tx_descs, i = 0; i < TX_SLOT_COUNT; i++)
 341       {
 342          tx_desc->ds_data = unit->tx_buffers_p[i];
 343          tx_desc++;
 344       }
 345
 346       /* Construct management frame TX ring */
 347
 348       for(tx_desc = unit->mgmt_descs, i = 0; i < MGMT_SLOT_COUNT; i++)
 349       {
 350          tx_desc->ds_data = unit->mgmt_buffers_p[i];
 351          tx_desc++;
 352       }
 353
 354       /* Construct RX ring */
 355
 356       for(rx_desc = unit->rx_descs, i = 0; i < RX_SLOT_COUNT; i++)
 357       {
 358          rx_desc->ds_link = unit->rx_descs_p + ((i + 1) % RX_SLOT_COUNT)
 359             * sizeof(struct ath_desc);
 360          rx_desc->ds_data = unit->rx_buffers_p[i];
 361          unit->hal->ah_setupRxDesc(unit->hal, rx_desc, FRAME_BUFFER_SIZE,
 362             HAL_RXDESC_INTREQ);
 363          rx_desc++;
 364       }
 365
 366       dma_size = sizeof(struct ath_desc) * RX_SLOT_COUNT;
 367       CachePreDMA(unit->rx_descs, &dma_size, 0);
 368
 369       /* Record maximum speed in BPS */
 370
 371       unit->speed = 54000000;
 372
 373       /* Initialise status, transmit, receive and stats interrupts */
 374
 375       unit->status_int.is_Node.ln_Name =
 376          base->device.dd_Library.lib_Node.ln_Name;
 377       unit->status_int.is_Code = (APTR)StatusInt;
 378       unit->status_int.is_Data = unit;
 379
 380       unit->rx_int.is_Node.ln_Name =
 381          base->device.dd_Library.lib_Node.ln_Name;
 382       unit->rx_int.is_Code = (APTR)RXInt;
 383       unit->rx_int.is_Data = unit;
 384
 385       unit->tx_int.is_Node.ln_Name =
 386          base->device.dd_Library.lib_Node.ln_Name;
 387       unit->tx_int.is_Code = (APTR)TXInt;
 388       unit->tx_int.is_Data = unit;
 389
 390       unit->tx_end_int.is_Node.ln_Name =
 391          base->device.dd_Library.lib_Node.ln_Name;
 392       unit->tx_end_int.is_Code = (APTR)TXEndInt;
 393       unit->tx_end_int.is_Data = unit;
 394
 395       unit->mgmt_int.is_Node.ln_Name =
 396          base->device.dd_Library.lib_Node.ln_Name;
 397       unit->mgmt_int.is_Code = (APTR)MgmtTXInt;
 398       unit->mgmt_int.is_Data = unit;
 399
 400       unit->mgmt_end_int.is_Node.ln_Name =
 401          base->device.dd_Library.lib_Node.ln_Name;
 402       unit->mgmt_end_int.is_Code = (APTR)MgmtTXEndInt;
 403       unit->mgmt_end_int.is_Data = unit;
 404
 405       unit->reset_handler.is_Node.ln_Name =
 406          base->device.dd_Library.lib_Node.ln_Name;
 407       unit->reset_handler.is_Code = (APTR)ResetHandler;
 408       unit->reset_handler.is_Data = unit;
 409
 410       unit->request_ports[WRITE_QUEUE]->mp_Flags = PA_SOFTINT;
 411       unit->request_ports[MGMT_QUEUE]->mp_Flags = PA_SOFTINT;
 412
 413       /* Create a new task */
 414
 415       unit->task = task =
 416          AllocMem(sizeof(struct Task), MEMF_PUBLIC | MEMF_CLEAR);
 417       if(task == NULL)
 418          success = FALSE;
 419    }
 420
 421    if(success)
 422    {
 423       stack = AllocMem(STACK_SIZE, MEMF_PUBLIC);
 424       if(stack == NULL)
 425          success = FALSE;
 426    }
 427
 428    if(success)
 429    {
 430       /* Initialise and start task */
 431
 432       task->tc_Node.ln_Type = NT_TASK;
 433       task->tc_Node.ln_Pri = TASK_PRIORITY;
 434       task->tc_Node.ln_Name = base->device.dd_Library.lib_Node.ln_Name;
 435       task->tc_SPUpper = stack + STACK_SIZE;
 436       task->tc_SPLower = stack;
 437       task->tc_SPReg = stack + STACK_SIZE;
 438       NewList(&task->tc_MemEntry);
 439
 440       if(AddTask(task, UnitTask, NULL) == NULL)
 441          success = FALSE;
 442    }
 443
 444    if(success)
 445    {
 446       /* Send the unit to the new task */
 447
 448       task->tc_UserData = unit;
 449
 450       /* Set default wireless options */
 451
 452       unit->mode = S2PORT_MANAGED;
 453    }
 454
 455    if(!success)
 456    {
 457       DeleteUnit(unit, base);
 458       unit = NULL;
 459    }
 460
 461    return unit;
 462 }
 463
 464
 465
 466 /****i* atheros5000.device/DeleteUnit **************************************
 467 *
 468 *   NAME
 469 *       DeleteUnit -- Delete a unit.
 470 *
 471 *   SYNOPSIS
 472 *       DeleteUnit(unit)
 473 *
 474 *       VOID DeleteUnit(struct DevUnit *);
 475 *
 476 *   FUNCTION
 477 *       Deletes a unit.
 478 *
 479 *   INPUTS
 480 *       unit - Device unit (may be NULL).
 481 *
 482 *   RESULT
 483 *       None.
 484 *
 485 ****************************************************************************
 486 *
 487 */
 488
 489 VOID DeleteUnit(struct DevUnit *unit, struct DevBase *base)
 490 {
 491    UBYTE i;
 492    struct Task *task;
 493
 494    if(unit != NULL)
 495    {
 496       task = unit->task;
 497       if(task != NULL)
 498       {
 499          if(task->tc_UserData != NULL)
 500          {
 501             RemTask(task);
 502             FreeMem(task->tc_SPLower, STACK_SIZE);
 503             Signal(unit->task, SIGBREAKF_CTRL_C);
 504          }
 505          FreeMem(task, sizeof(struct Task));
 506       }
 507
 508       for(i = 0; i < REQUEST_QUEUE_COUNT; i++)
 509       {
 510          if(unit->request_ports[i] != NULL)
 511             FreeMem(unit->request_ports[i], sizeof(struct MsgPort));
 512       }
 513
 514       if((unit->flags & UNITF_ONLINE) != 0)   /* Needed! */
 515          GoOffline(unit, base);
 516
 517       for(i = 0; i < TX_SLOT_COUNT; i++)
 518          unit->FreeDMAMem(unit->card, unit->tx_buffers[i]);
 519       for(i = 0; i < MGMT_SLOT_COUNT; i++)
 520          unit->FreeDMAMem(unit->card, unit->mgmt_buffers[i]);
 521       for(i = 0; i < RX_SLOT_COUNT; i++)
 522          unit->FreeDMAMem(unit->card, unit->rx_buffers[i]);
 523
 524       FreeVec(unit->tx_buffer);
 525       FreeVec(unit->rx_frames);
 526       FreeVec(unit->tx_requests);
 527       FreeVec(unit->mgmt_requests);
 528       FreeVec(unit->channels);
 529       FreeVec(unit->rx_buffer);
 530
 531       if(unit->hal != NULL)
 532          unit->hal->ah_detach(unit->hal);
 533
 534       FreeMem(unit, sizeof(struct DevUnit));
 535    }
 536
 537    return;
 538 }
 539
 540
 541
 542 /****i* atheros5000.device/InitialiseAdapter *******************************
 543 *
 544 *   NAME
 545 *       InitialiseAdapter
 546 *
 547 *   SYNOPSIS
 548 *       success = InitialiseAdapter(unit, reinsertion)
 549 *
 550 *       BOOL InitialiseAdapter(struct DevUnit *, BOOL);
 551 *
 552 *   FUNCTION
 553 *
 554 *   INPUTS
 555 *       unit
 556 *       reinsertion
 557 *
 558 *   RESULT
 559 *       success - Success indicator.
 560 *
 561 ****************************************************************************
 562 *
 563 */
 564
 565 BOOL InitialiseAdapter(struct DevUnit *unit, BOOL reinsertion,
 566    struct DevBase *base)
 567 {
 568    UBYTE i, reg_class_id;
 569    BOOL success = TRUE;
 570    unsigned int channel_count, reg_class_count;
 571    HAL_TXQ_INFO queue_info = {0};
 572
 573    /* Get default MAC address */
 574
 575    unit->hal->ah_getMacAddress(unit->hal, unit->default_address);
 576
 577    /* Get default antenna */
 578
 579    unit->antenna = unit->hal->ah_getDefAntenna(unit->hal);
 580
 581    /* Reset key cache */
 582
 583    for(i = 0; i < WIFI_KEYCOUNT; i++)
 584       unit->hal->ah_resetKeyCacheEntry(unit->hal, i);
 585
 586    /* Initialise channels and rates */
 587
 588    ath_hal_init_channels(unit->hal, unit->channels,
 589       MAX_CHANNEL_COUNT, &channel_count,
 590       &reg_class_id, 1, &reg_class_count, CTRY_DEFAULT,
 591       HAL_MODE_11B | HAL_MODE_PUREG, TRUE,
 592       FALSE);
 593    unit->channel_count = channel_count;
 594
 595    unit->channel = 1;
 596    unit->band = S2BAND_B;
 597
 598    /* Check if multi-rate retries are supported */
 599
 600    if(unit->hal->ah_setupXTxDesc(unit->hal, NULL, 0, 0, 0, 0, 0, 0))
 601       unit->flags |= UNITF_SLOWRETRIES;
 602
 603    /* Set up TX queue */
 604
 605    queue_info.tqi_aifs = HAL_TXQ_USEDEFAULT;
 606    queue_info.tqi_cwmin = HAL_TXQ_USEDEFAULT;
 607    queue_info.tqi_cwmax = HAL_TXQ_USEDEFAULT;
 608    queue_info.tqi_qflags =
 609       HAL_TXQ_TXEOLINT_ENABLE | HAL_TXQ_TXDESCINT_ENABLE;
 610
 611    unit->tx_queue_no =
 612       unit->hal->ah_setupTxQueue(unit->hal, HAL_TX_QUEUE_DATA, &queue_info);
 613    unit->hal->ah_resetTxQueue(unit->hal, unit->tx_queue_no);
 614
 615    /* Set up management frame TX queue */
 616
 617    queue_info.tqi_aifs = HAL_TXQ_USEDEFAULT;
 618    queue_info.tqi_cwmin = HAL_TXQ_USEDEFAULT;
 619    queue_info.tqi_cwmax = HAL_TXQ_USEDEFAULT;
 620    queue_info.tqi_qflags =
 621       HAL_TXQ_TXEOLINT_ENABLE | HAL_TXQ_TXDESCINT_ENABLE;
 622
 623    unit->mgmt_queue_no =
 624       unit->hal->ah_setupTxQueue(unit->hal, HAL_TX_QUEUE_DATA, &queue_info);
 625    unit->hal->ah_resetTxQueue(unit->hal, unit->mgmt_queue_no);
 626
 627    /* Find out hardware encryption capabilities */
 628
 629    if(unit->hal->ah_getCapability(unit->hal, HAL_CAP_CIPHER,
 630       HAL_CIPHER_WEP, NULL) == HAL_OK)
 631       unit->flags |= UNITF_HARDWEP;
 632    if(unit->hal->ah_getCapability(unit->hal, HAL_CAP_CIPHER,
 633       HAL_CIPHER_TKIP, NULL) == HAL_OK)
 634       unit->flags |= UNITF_HARDTKIP;
 635 #if 1
 636    if(unit->hal->ah_getCapability(unit->hal, HAL_CAP_CIPHER,
 637       HAL_CIPHER_MIC, NULL) == HAL_OK)
 638    {
 639       if(unit->hal->ah_setCapability(unit->hal, HAL_CAP_TKIP_MIC,
 640 //         0, TRUE, NULL))
 641          0, 0, NULL))
 642          unit->flags |= UNITF_HARDMIC;
 643    }
 644 #else
 645    if(unit->hal->ah_setCapability(unit->hal, HAL_CAP_TKIP_MIC,
 646       0, FALSE, NULL))
 647 #endif
 648    if(unit->hal->ah_getCapability(unit->hal, HAL_CAP_TKIP_SPLIT, 0,
 649       NULL) == HAL_OK)
 650       unit->flags |= UNITF_SPLITMIC;
 651    if(unit->hal->ah_getCapability(unit->hal, HAL_CAP_CIPHER,
 652       HAL_CIPHER_AES_OCB, NULL) == HAL_OK)
 653       unit->flags |= UNITF_HARDAESOCB;
 654    if(unit->hal->ah_getCapability(unit->hal, HAL_CAP_CIPHER,
 655       HAL_CIPHER_AES_CCM, NULL) == HAL_OK)
 656       unit->flags |= UNITF_HARDCCMP;
 657
 658    /* Set IV sizes */
 659
 660    unit->iv_sizes[S2ENC_WEP] = IV_SIZE;
 661    unit->iv_sizes[S2ENC_TKIP] = EIV_SIZE;
 662    unit->iv_sizes[S2ENC_CCMP] = EIV_SIZE;
 663
 664    /* Set encryption functions */
 665
 666    unit->fragment_encrypt_functions[S2ENC_NONE] = WriteClearFragment;
 667
 668    if((unit->flags & UNITF_HARDWEP) != 0)
 669       unit->fragment_encrypt_functions[S2ENC_WEP] = WriteWEPFragment;
 670    else
 671       unit->fragment_encrypt_functions[S2ENC_WEP] = EncryptWEPFragment;
 672
 673    if((unit->flags & UNITF_HARDTKIP) != 0)
 674       unit->fragment_encrypt_functions[S2ENC_TKIP] = WriteTKIPFragment;
 675    else
 676       unit->fragment_encrypt_functions[S2ENC_TKIP] = EncryptTKIPFragment;
 677
 678    if((unit->flags & UNITF_HARDCCMP) != 0)
 679       unit->fragment_encrypt_functions[S2ENC_CCMP] = WriteCCMPFragment;
 680    else
 681       unit->fragment_encrypt_functions[S2ENC_CCMP] = EncryptCCMPFragment;
 682
 683    /* Set decryption functions */
 684
 685    unit->fragment_decrypt_functions[S2ENC_NONE] = ReadClearFragment;
 686
 687    if((unit->flags & UNITF_HARDWEP) != 0)
 688       unit->fragment_decrypt_functions[S2ENC_WEP] = ReadWEPFragment;
 689    else
 690       unit->fragment_decrypt_functions[S2ENC_WEP] = DecryptWEPFragment;
 691
 692    if((unit->flags & UNITF_HARDTKIP) != 0)
 693       unit->fragment_decrypt_functions[S2ENC_TKIP] = ReadTKIPFragment;
 694    else
 695       unit->fragment_decrypt_functions[S2ENC_TKIP] = DecryptTKIPFragment;
 696
 697    if((unit->flags & UNITF_HARDCCMP) != 0)
 698       unit->fragment_decrypt_functions[S2ENC_CCMP] = ReadCCMPFragment;
 699    else
 700       unit->fragment_decrypt_functions[S2ENC_CCMP] = DecryptCCMPFragment;
 701
 702    /* Return */
 703
 704    return success;
 705 }
 706
 707
 708
 709 /****i* atheros5000.device/ConfigureAdapter ********************************
 710 *
 711 *   NAME
 712 *       ConfigureAdapter -- Set up card for transmission/reception.
 713 *
 714 *   SYNOPSIS
 715 *       ConfigureAdapter(unit)
 716 *
 717 *       VOID ConfigureAdapter(struct DevUnit *);
 718 *
 719 ****************************************************************************
 720 *
 721 */
 722
 723 VOID ConfigureAdapter(struct DevUnit *unit, struct DevBase *base)
 724 {
 725    UWORD i, j, key_length, hal_band, key_type;
 726    const struct KeyUnion *keys;
 727    HAL_CHANNEL *channel = unit->channels, *ch;
 728    ULONG freq = 2407 + unit->channel * 5;
 729    HAL_STATUS status;
 730    HAL_KEYVAL hal_key;
 731    HAL_BOOL iq_done;
 732    const HAL_RATE_TABLE *rate_table;
 733
 734    /* Get band-specific parameters */
 735
 736    if(unit->band == S2BAND_G)
 737    {
 738       hal_band = HAL_MODE_11G;
 739       unit->band_mask = CHANNEL_G;
 740       unit->tx_rates = g_retry_rates;
 741       unit->mgmt_rate = G_MGMT_RATE;
 742    }
 743    else if(unit->band == S2BAND_B)
 744    {
 745       hal_band = HAL_MODE_11B;
 746       unit->band_mask = CHANNEL_B;
 747       unit->tx_rates = b_retry_rates;
 748       unit->mgmt_rate = B_MGMT_RATE;
 749    }
 750    unit->rate_table = unit->hal->ah_getRateTable(unit->hal, hal_band);
 751
 752    /* Find rate codes to match our optimal and retry rates */
 753
 754    rate_table = unit->rate_table;
 755    for(i = 0; i < rate_table->rateCount; i++)
 756    {
 757       for(j = 0; j < 4; j++)
 758       {
 759          if(rate_table->info[i].rateKbps == unit->tx_rates[j])
 760          {
 761             unit->tx_rate_codes[j] = rate_table->info[i].rateCode;
 762             if((unit->flags & UNITF_SHORTPREAMBLE) != 0)
 763                unit->tx_rate_codes[j] |= rate_table->info[i].shortPreamble;
 764          }
 765       }
 766       if(rate_table->info[i].rateKbps == unit->mgmt_rate)
 767       {
 768          unit->mgmt_rate_code = rate_table->info[i].rateCode;
 769          if((unit->flags & UNITF_SHORTPREAMBLE) != 0)
 770             unit->mgmt_rate_code |= rate_table->info[i].shortPreamble;
 771       }
 772    }
 773
 774    /* Find a channel that matches requirements */
 775
 776    for(i = 0, ch = unit->channels; i < unit->channel_count; i++, ch++)
 777    {
 778       if(ch->channel == freq
 779          && (ch->channelFlags & unit->band_mask) == unit->band_mask)
 780          channel = ch;
 781    }
 782
 783    /* Stop the transceiver if we're already online */
 784
 785    if((unit->flags & UNITF_ONLINE) != 0)
 786    {
 787       /* Disable frame transmission */
 788
 789       unit->hal->ah_stopTxDma(unit->hal, unit->tx_queue_no);
 790       unit->hal->ah_stopTxDma(unit->hal, unit->mgmt_queue_no);
 791       unit->hal->ah_setRxFilter(unit->hal, 0);
 792 ath_hal_delay(3000);
 793
 794       /* Disable frame reception */
 795
 796       unit->hal->ah_stopPcuReceive(unit->hal);
 797       unit->hal->ah_stopDmaReceive(unit->hal);
 798
 799       /* Disable interrupts */
 800
 801       unit->hal->ah_setInterrupts(unit->hal, 0);
 802    }
 803
 804    /* Calculate RX filter mask */
 805
 806    unit->filter_mask = HAL_RX_FILTER_UCAST | HAL_RX_FILTER_MCAST
 807       | HAL_RX_FILTER_BCAST;
 808    if((unit->flags & UNITF_PROM) != 0)
 809       unit->filter_mask |= HAL_RX_FILTER_PROM;
 810    if(unit->mode != S2PORT_MANAGED)
 811       unit->filter_mask |= HAL_RX_FILTER_PROBEREQ;
 812
 813    /* Reset card */
 814
 815    unit->hal->ah_reset(unit->hal, HAL_M_STA, channel, FALSE, &status);
 816
 817    /* Set MAC address and miscellaneous wireless parameters */
 818
 819    unit->hal->ah_setMacAddress(unit->hal, unit->address);
 820    unit->hal->ah_setPCUConfig(unit->hal);
 821    SetMulticast(unit, base);
 822    unit->hal->ah_setDefAntenna(unit->hal, unit->antenna);
 823    unit->hal->ah_perCalibration(unit->hal, channel, &iq_done);
 824    unit->hal->ah_setTxPowerLimit(unit->hal, TX_POWER);
 825
 826    /* Set association ID */
 827
 828    unit->hal->ah_writeAssocid(unit->hal, unit->bssid, unit->assoc_id);
 829
 830    /* Put on a reassuring light */
 831
 832    unit->hal->ah_setLedState(unit->hal, HAL_LED_RUN);
 833
 834    /* Set or clear default encryption keys where appropriate */
 835
 836    keys = unit->keys;
 837    for(i = 0; i < WIFI_KEYCOUNT; i++)
 838    {
 839       key_type = unit->keys[i].type;
 840       if(key_type <= S2ENC_WEP
 841          || key_type == S2ENC_TKIP && (unit->flags & UNITF_HARDTKIP) == 0
 842          || key_type == S2ENC_CCMP && (unit->flags & UNITF_HARDCCMP) == 0)
 843       {
 844          if(key_type == S2ENC_WEP && (unit->flags & UNITF_HARDWEP) != 0)
 845          {
 846             hal_key.kv_type = HAL_CIPHER_WEP;
 847             key_length = keys[i].u.wep.length;
 848             CopyMem(keys[i].u.wep.key, hal_key.kv_val, key_length);
 849          }
 850          else
 851          {
 852             hal_key.kv_type = HAL_CIPHER_CLR;
 853             key_length = 0;
 854          }
 855          hal_key.kv_len = key_length;
 856          unit->hal->ah_setKeyCacheEntry(unit->hal, i, &hal_key,
 857             unit->bssid, FALSE);
 858       }
 859    }
 860
 861    /* Set pointer to RX ring */
 862
 863    unit->hal->ah_setRxDP(unit->hal,
 864       unit->rx_descs_p + unit->rx_slot * sizeof(struct ath_desc));
 865
 866    /* Restart the transceiver if we're already online */
 867
 868    if((unit->flags & UNITF_ONLINE) != 0)
 869    {
 870       /* Enable interrupts */
 871
 872       unit->hal->ah_setInterrupts(unit->hal, INT_MASK);
 873
 874       /* Enable frame reception */
 875
 876       unit->hal->ah_enableReceive(unit->hal);
 877       unit->hal->ah_setRxFilter(unit->hal, unit->filter_mask);
 878       unit->hal->ah_startPcuReceive(unit->hal);
 879
 880 #if 0
 881       /* Reset TX queues */
 882
 883       unit->hal->ah_resetTxQueue(unit->hal, unit->tx_queue_no);
 884       unit->hal->ah_resetTxQueue(unit->hal, unit->mgmt_queue_no);
 885 #endif
 886    }
 887
 888    /* Return */
 889
 890    return;
 891 }
 892
 893
 894
 895 /****i* atheros5000.device/GoOnline ****************************************
 896 *
 897 *   NAME
 898 *       GoOnline -- Enable transmission/reception.
 899 *
 900 *   SYNOPSIS
 901 *       GoOnline(unit)
 902 *
 903 *       VOID GoOnline(struct DevUnit *);
 904 *
 905 ****************************************************************************
 906 *
 907 */
 908
 909 VOID GoOnline(struct DevUnit *unit, struct DevBase *base)
 910 {
 911    /* Enable interrupts */
 912
 913    unit->flags |= UNITF_ONLINE;
 914    unit->hal->ah_setInterrupts(unit->hal, INT_MASK);
 915
 916    /* Enable frame reception */
 917
 918    unit->hal->ah_enableReceive(unit->hal);
 919    unit->hal->ah_setRxFilter(unit->hal, unit->filter_mask);
 920    unit->hal->ah_startPcuReceive(unit->hal);
 921
 922 #if 0
 923    /* Reset TX queues */
 924
 925    unit->hal->ah_resetTxQueue(unit->hal, unit->tx_queue_no);
 926    unit->hal->ah_resetTxQueue(unit->hal, unit->mgmt_queue_no);
 927 #endif
 928
 929    /* Record start time and report Online event */
 930
 931    GetSysTime(&unit->stats.LastStart);
 932    ReportEvents(unit, S2EVENT_ONLINE, base);
 933
 934    return;
 935 }
 936
 937
 938
 939 /****i* atheros5000.device/GoOffline ***************************************
 940 *
 941 *   NAME
 942 *       GoOffline -- Disable transmission/reception.
 943 *
 944 *   SYNOPSIS
 945 *       GoOffline(unit)
 946 *
 947 *       VOID GoOffline(struct DevUnit *);
 948 *
 949 *   FUNCTION
 950 *
 951 *   INPUTS
 952 *       unit
 953 *
 954 *   RESULT
 955 *       None.
 956 *
 957 ****************************************************************************
 958 *
 959 */
 960
 961 VOID GoOffline(struct DevUnit *unit, struct DevBase *base)
 962 {
 963    unit->flags &= ~UNITF_ONLINE;
 964    if((unit->flags & UNITF_HAVEADAPTER) != 0)
 965    {
 966       /* Disable frame transmission */
 967
 968       unit->hal->ah_stopTxDma(unit->hal, unit->tx_queue_no);
 969       unit->hal->ah_stopTxDma(unit->hal, unit->mgmt_queue_no);
 970
 971       /* Disable frame reception */
 972
 973       unit->hal->ah_stopPcuReceive(unit->hal);
 974       unit->hal->ah_stopDmaReceive(unit->hal);
 975       unit->hal->ah_setRxFilter(unit->hal, 0);
 976 ath_hal_delay(3000);
 977
 978       /* Stop interrupts */
 979
 980       unit->hal->ah_setInterrupts(unit->hal, 0);
 981
 982       /* Update statistics */
 983
 984       UpdateStats(unit, base);
 985    }
 986
 987    /* Flush pending read and write requests */
 988
 989    FlushUnit(unit, MGMT_QUEUE, S2ERR_OUTOFSERVICE, base);
 990
 991    /* Report Offline event and return */
 992
 993    ReportEvents(unit, S2EVENT_OFFLINE, base);
 994    return;
 995 }
 996
 997
 998
 999 /****i* atheros5000.device/SetOptions **************************************
1000 *
1001 *   NAME
1002 *       SetOptions -- Set and use interface options.
1003 *
1004 *   SYNOPSIS
1005 *       reconfigure = SetOptions(unit, tag_list)
1006 *
1007 *       BOOL SetOptions(struct DevUnit *, struct TagItem *);
1008 *
1009 ****************************************************************************
1010 *
1011 */
1012
1013 BOOL SetOptions(struct DevUnit *unit, const struct TagItem *tag_list,
1014    struct DevBase *base)
1015 {
1016    struct TagItem *tag_item, *tlist = (struct TagItem *)tag_list;
1017    BOOL reconfigure = TRUE;
1018
1019    while((tag_item = NextTagItem(&tlist)) != NULL)
1020    {
1021       switch(tag_item->ti_Tag)
1022       {
1023       case S2INFO_SSID:
1024          ReportEvents(unit, S2EVENT_CONNECT, base);
1025          break;
1026
1027       case S2INFO_BSSID:
1028          CopyMem((APTR)tag_item->ti_Data, unit->bssid, ETH_ADDRESSSIZE);
1029          break;
1030
1031       case S2INFO_AssocID:
1032          unit->assoc_id = tag_item->ti_Data;
1033          break;
1034
1035       case S2INFO_Capabilities:
1036          unit->capabilities = tag_item->ti_Data;
1037          if((unit->capabilities & (1 << 5)) != 0)
1038             unit->flags |= UNITF_SHORTPREAMBLE;
1039          else
1040             unit->flags &= ~UNITF_SHORTPREAMBLE;
1041          break;
1042
1043       case S2INFO_DefaultKeyNo:
1044          unit->tx_key_no = tag_item->ti_Data;
1045          break;
1046
1047       case S2INFO_PortType:
1048          unit->mode = tag_item->ti_Data;
1049          break;
1050
1051       case S2INFO_Channel:
1052          if(tag_item->ti_Data != unit->channel)
1053          {
1054             unit->channel = tag_item->ti_Data;
1055             reconfigure = TRUE;
1056          }
1057          break;
1058
1059       case S2INFO_Band:
1060          if(tag_item->ti_Data != unit->band)
1061          {
1062             unit->band = tag_item->ti_Data;
1063             reconfigure = TRUE;
1064          }
1065          break;
1066       }
1067    }
1068
1069    return reconfigure;
1070 }
1071
1072
1073
1074 /****i* atheros5000.device/SetKey ******************************************
1075 *
1076 *   NAME
1077 *       SetKey -- Set an encryption key.
1078 *
1079 *   SYNOPSIS
1080 *       SetKey(unit, index, type, key, key_length,
1081 *           rx_counter)
1082 *
1083 *       VOID SetKey(struct DevUnit *, ULONG, ULONG, UBYTE *, ULONG,
1084 *           UBYTE *);
1085 *
1086 ****************************************************************************
1087 *
1088 */
1089
1090 VOID SetKey(struct DevUnit *unit, ULONG index, ULONG type, const UBYTE *key,
1091    ULONG key_length, const UBYTE *rx_counter, struct DevBase *base)
1092 {
1093    struct KeyUnion *slot;
1094    struct EClockVal eclock;
1095    HAL_KEYVAL hal_key;
1096    UWORD i;
1097
1098    Disable();
1099    slot = &unit->keys[index];
1100    switch(type)
1101    {
1102       case S2ENC_WEP:
1103          CopyMem(key, slot->u.wep.key, key_length);
1104          slot->u.wep.length = key_length;
1105
1106          if((unit->flags & UNITF_HARDWEP) == 0)
1107          {
1108             /* Create a reasonably random IV */
1109
1110             ReadEClock(&eclock);
1111             slot->u.wep.tx_iv = FastRand(eclock.ev_lo ^ eclock.ev_hi);
1112          }
1113
1114          break;
1115
1116       case S2ENC_TKIP:
1117          CopyMem(key, slot->u.tkip.key, 16);
1118          CopyMem(key + 16, slot->u.tkip.tx_mic_key, MIC_SIZE);
1119          CopyMem(key + 24, slot->u.tkip.rx_mic_key, MIC_SIZE);
1120          slot->u.tkip.tx_iv_low = 0;
1121          slot->u.tkip.tx_iv_high = 0;
1122          slot->u.tkip.rx_iv_low = LEWord(*(UWORD *)rx_counter);
1123          slot->u.tkip.rx_iv_high = LELong(*(ULONG *)(rx_counter + 2));
1124          slot->u.tkip.tx_ttak_set = FALSE;
1125          slot->u.tkip.rx_ttak_set = FALSE;
1126
1127          if((unit->flags & UNITF_HARDTKIP) != 0)
1128          {
1129 // TO DO: Wait for TX queue to empty
1130             /* Load parameters for hardware encryption */
1131
1132             hal_key.kv_type = HAL_CIPHER_TKIP;
1133             hal_key.kv_len = 16;
1134             CopyMem(slot->u.tkip.key, hal_key.kv_val, 16);
1135
1136             CopyMem(slot->u.tkip.tx_mic_key, hal_key.kv_mic, MIC_SIZE);
1137             unit->hal->ah_setKeyCacheEntry(unit->hal, index, &hal_key,
1138                unit->bssid, FALSE);
1139             CopyMem(slot->u.tkip.rx_mic_key, hal_key.kv_mic, MIC_SIZE);
1140             unit->hal->ah_setKeyCacheEntry(unit->hal, index + 32, &hal_key,
1141                unit->bssid, FALSE);
1142          }
1143          else
1144          {
1145             /* Convert key to native endianness */
1146
1147             for(i = 0; i < 8; i++)
1148                slot->u.tkip.key[i] = LEWord(slot->u.tkip.key[i]);
1149          }
1150
1151          break;
1152
1153       case S2ENC_CCMP:
1154          CopyMem(key, slot->u.ccmp.key, 16);
1155          slot->u.ccmp.tx_iv_low = 0;
1156          slot->u.ccmp.tx_iv_high = 0;
1157          slot->u.ccmp.rx_iv_low = LEWord(*(UWORD *)rx_counter);
1158          slot->u.ccmp.rx_iv_high = LELong(*(ULONG *)(rx_counter + 2));
1159          slot->u.ccmp.stream_set = FALSE;
1160
1161          if((unit->flags & UNITF_HARDCCMP) != 0)
1162          {
1163 // TO DO: Wait for TX queue to empty
1164             /* Load parameters for hardware encryption */
1165
1166             hal_key.kv_type = HAL_CIPHER_AES_CCM;
1167             hal_key.kv_len = 16;
1168             CopyMem(slot->u.ccmp.key, hal_key.kv_val, 16);
1169             unit->hal->ah_setKeyCacheEntry(unit->hal, index, &hal_key,
1170                unit->bssid, FALSE);
1171          }
1172    }
1173
1174    /* Update type of key in selected slot */
1175
1176    slot->type = type;
1177    Enable();
1178
1179    return;
1180 }
1181
1182
1183
1184 /****i* atheros5000.device/AddMulticastRange *******************************
1185 *
1186 *   NAME
1187 *       AddMulticastRange
1188 *
1189 *   SYNOPSIS
1190 *       success = AddMulticastRange(unit, lower_bound, upper_bound)
1191 *
1192 *       BOOL AddMulticastRange(struct DevUnit *, UBYTE *, UBYTE *);
1193 *
1194 ****************************************************************************
1195 *
1196 */
1197
1198 BOOL AddMulticastRange(struct DevUnit *unit, const UBYTE *lower_bound,
1199    const UBYTE *upper_bound, struct DevBase *base)
1200 {
1201    struct AddressRange *range;
1202    ULONG lower_bound_left, upper_bound_left;
1203    UWORD lower_bound_right, upper_bound_right;
1204
1205    lower_bound_left = BELong(*((ULONG *)lower_bound));
1206    lower_bound_right = BEWord(*((UWORD *)(lower_bound + 4)));
1207    upper_bound_left = BELong(*((ULONG *)upper_bound));
1208    upper_bound_right = BEWord(*((UWORD *)(upper_bound + 4)));
1209
1210    range = FindMulticastRange(unit, lower_bound_left, lower_bound_right,
1211       upper_bound_left, upper_bound_right, base);
1212
1213    if(range != NULL)
1214       range->add_count++;
1215    else
1216    {
1217       range = AllocMem(sizeof(struct AddressRange), MEMF_PUBLIC);
1218       if(range != NULL)
1219       {
1220          range->lower_bound_left = lower_bound_left;
1221          range->lower_bound_right = lower_bound_right;
1222          range->upper_bound_left = upper_bound_left;
1223          range->upper_bound_right = upper_bound_right;
1224          range->add_count = 1;
1225
1226          Disable();
1227          AddTail((APTR)&unit->multicast_ranges, (APTR)range);
1228          unit->range_count++;
1229          SetMulticast(unit, base);
1230          Enable();
1231       }
1232    }
1233
1234    return range != NULL;
1235 }
1236
1237
1238
1239 /****i* atheros5000.device/RemMulticastRange *******************************
1240 *
1241 *   NAME
1242 *       RemMulticastRange
1243 *
1244 *   SYNOPSIS
1245 *       found = RemMulticastRange(unit, lower_bound, upper_bound)
1246 *
1247 *       BOOL RemMulticastRange(struct DevUnit *, UBYTE *, UBYTE *);
1248 *
1249 ****************************************************************************
1250 *
1251 */
1252
1253 BOOL RemMulticastRange(struct DevUnit *unit, const UBYTE *lower_bound,
1254    const UBYTE *upper_bound, struct DevBase *base)
1255 {
1256    struct AddressRange *range;
1257    ULONG lower_bound_left, upper_bound_left;
1258    UWORD lower_bound_right, upper_bound_right;
1259
1260    lower_bound_left = BELong(*((ULONG *)lower_bound));
1261    lower_bound_right = BEWord(*((UWORD *)(lower_bound + 4)));
1262    upper_bound_left = BELong(*((ULONG *)upper_bound));
1263    upper_bound_right = BEWord(*((UWORD *)(upper_bound + 4)));
1264
1265    range = FindMulticastRange(unit, lower_bound_left, lower_bound_right,
1266       upper_bound_left, upper_bound_right, base);
1267
1268    if(range != NULL)
1269    {
1270       if(--range->add_count == 0)
1271       {
1272          Disable();
1273          Remove((APTR)range);
1274          unit->range_count--;
1275          SetMulticast(unit, base);
1276          Enable();
1277          FreeMem(range, sizeof(struct AddressRange));
1278       }
1279    }
1280
1281    return range != NULL;
1282 }
1283
1284
1285
1286 /****i* atheros5000.device/FindMulticastRange ******************************
1287 *
1288 *   NAME
1289 *       FindMulticastRange
1290 *
1291 *   SYNOPSIS
1292 *       range = FindMulticastRange(unit, lower_bound_left,
1293 *           lower_bound_right, upper_bound_left, upper_bound_right)
1294 *
1295 *       struct AddressRange *FindMulticastRange(struct DevUnit *, ULONG,
1296 *           UWORD, ULONG, UWORD);
1297 *
1298 ****************************************************************************
1299 *
1300 */
1301
1302 static struct AddressRange *FindMulticastRange(struct DevUnit *unit,
1303    ULONG lower_bound_left, UWORD lower_bound_right, ULONG upper_bound_left,
1304    UWORD upper_bound_right, struct DevBase *base)
1305 {
1306    struct AddressRange *range, *tail;
1307    BOOL found = FALSE;
1308
1309    range = (APTR)unit->multicast_ranges.mlh_Head;
1310    tail = (APTR)&unit->multicast_ranges.mlh_Tail;
1311
1312    while(range != tail && !found)
1313    {
1314       if(lower_bound_left == range->lower_bound_left &&
1315          lower_bound_right == range->lower_bound_right &&
1316          upper_bound_left == range->upper_bound_left &&
1317          upper_bound_right == range->upper_bound_right)
1318          found = TRUE;
1319       else
1320          range = (APTR)range->node.mln_Succ;
1321    }
1322
1323    if(!found)
1324       range = NULL;
1325
1326    return range;
1327 }
1328
1329
1330
1331 /****i* atheros5000.device/SetMulticast ************************************
1332 *
1333 *   NAME
1334 *       SetMulticast
1335 *
1336 *   SYNOPSIS
1337 *       SetMulticast(unit)
1338 *
1339 *       VOID SetMulticast(struct DevUnit *);
1340 *
1341 ****************************************************************************
1342 *
1343 */
1344
1345 static VOID SetMulticast(struct DevUnit *unit, struct DevBase *base)
1346 {
1347    unit->hal->ah_setMulticastFilter(unit->hal, 0xffffffff, 0xffffffff);
1348
1349    return;
1350 }
1351
1352
1353
1354 /****i* atheros5000.device/FindTypeStats ***********************************
1355 *
1356 *   NAME
1357 *       FindTypeStats
1358 *
1359 *   SYNOPSIS
1360 *       stats = FindTypeStats(unit, list,
1361 *           packet_type)
1362 *
1363 *       struct TypeStats *FindTypeStats(struct DevUnit *, struct MinList *,
1364 *           ULONG);
1365 *
1366 ****************************************************************************
1367 *
1368 */
1369
1370 struct TypeStats *FindTypeStats(struct DevUnit *unit, struct MinList *list,
1371    ULONG packet_type, struct DevBase *base)
1372 {
1373    struct TypeStats *stats, *tail;
1374    BOOL found = FALSE;
1375
1376    stats = (APTR)list->mlh_Head;
1377    tail = (APTR)&list->mlh_Tail;
1378
1379    while(stats != tail && !found)
1380    {
1381       if(stats->packet_type == packet_type)
1382          found = TRUE;
1383       else
1384          stats = (APTR)stats->node.mln_Succ;
1385    }
1386
1387    if(!found)
1388       stats = NULL;
1389
1390    return stats;
1391 }
1392
1393
1394
1395 /****i* atheros5000.device/FlushUnit ***************************************
1396 *
1397 *   NAME
1398 *       FlushUnit
1399 *
1400 *   SYNOPSIS
1401 *       FlushUnit(unit, last_queue, error)
1402 *
1403 *       VOID FlushUnit(struct DevUnit *, UBYTE, BYTE);
1404 *
1405 ****************************************************************************
1406 *
1407 */
1408
1409 VOID FlushUnit(struct DevUnit *unit, UBYTE last_queue, BYTE error,
1410    struct DevBase *base)
1411 {
1412    struct IORequest *request;
1413    UBYTE i;
1414    struct Opener *opener, *tail;
1415
1416    /* Abort queued requests */
1417
1418    for(i = 0; i <= last_queue; i++)
1419    {
1420       while((request = (APTR)GetMsg(unit->request_ports[i])) != NULL)
1421       {
1422          request->io_Error = IOERR_ABORTED;
1423          ReplyMsg((APTR)request);
1424       }
1425    }
1426
1427 #if 1
1428    opener = (APTR)unit->openers.mlh_Head;
1429    tail = (APTR)&unit->openers.mlh_Tail;
1430
1431    /* Flush every opener's read queues */
1432
1433    while(opener != tail)
1434    {
1435       while((request = (APTR)GetMsg(&opener->read_port)) != NULL)
1436       {
1437          request->io_Error = error;
1438          ReplyMsg((APTR)request);
1439       }
1440       while((request = (APTR)GetMsg(&opener->mgmt_port)) != NULL)
1441       {
1442          request->io_Error = error;
1443          ReplyMsg((APTR)request);
1444       }
1445       opener = (APTR)opener->node.mln_Succ;
1446    }
1447
1448 #else
1449    opener = request->ios2_BufferManagement;
1450    while((request = (APTR)GetMsg(&opener->read_port)) != NULL)
1451    {
1452       request->io_Error = IOERR_ABORTED;
1453       ReplyMsg((APTR)request);
1454    }
1455    while((request = (APTR)GetMsg(&opener->mgmt_port)) != NULL)
1456    {
1457       request->io_Error = IOERR_ABORTED;
1458       ReplyMsg((APTR)request);
1459    }
1460 #endif
1461
1462    /* Return */
1463
1464    return;
1465 }
1466
1467
1468
1469 /****i* atheros5000.device/StatusInt ***************************************
1470 *
1471 *   NAME
1472 *       StatusInt
1473 *
1474 *   SYNOPSIS
1475 *       finished = StatusInt(unit)
1476 *
1477 *       BOOL StatusInt(struct DevUnit *);
1478 *
1479 *   FUNCTION
1480 *
1481 *   INPUTS
1482 *       unit
1483 *
1484 *   RESULT
1485 *       finished
1486 *
1487 ****************************************************************************
1488 *
1489 * int_code is really in A5, but GCC 2.95.3 doesn't seem able to handle that.
1490 * Since we don't use this parameter, we can lie.
1491 *
1492 */
1493
1494 static BOOL StatusInt(REG(a1, struct DevUnit *unit), REG(a6, APTR int_code))
1495 {
1496    struct DevBase *base;
1497    uint32_t queue_mask;
1498    HAL_INT ints, int_mask;
1499
1500    base = unit->device;
1501    int_mask = unit->hal->ah_getInterrupts(unit->hal);
1502
1503    if(!unit->hal->ah_isInterruptPending(unit->hal)) return FALSE;
1504
1505    /* Handle ints */
1506
1507    if(unit->hal->ah_getPendingInterrupts(unit->hal, &ints))
1508    {
1509       if((ints & HAL_INT_TX) != 0)
1510       {
1511          int_mask &= ~(HAL_INT_TX | HAL_INT_TXDESC);
1512          queue_mask = 1 << unit->tx_queue_no | 1 << unit->mgmt_queue_no;
1513          unit->hal->ah_getTxIntrQueue(unit->hal, &queue_mask);
1514          if((queue_mask & 1 << unit->tx_queue_no) != 0)
1515             Cause(&unit->tx_end_int);
1516          if((queue_mask & 1 << unit->mgmt_queue_no) != 0)
1517             Cause(&unit->mgmt_end_int);
1518       }
1519       if((ints & HAL_INT_RX) != 0)
1520       {
1521          int_mask &= ~(HAL_INT_RX | HAL_INT_RXEOL);
1522          Cause(&unit->rx_int);
1523       }
1524    }
1525
1526 #ifdef __MORPHOS__
1527    int_mask = INT_MASK;
1528 #endif
1529 //   unit->hal->ah_setInterrupts(unit->hal, int_mask))
1530
1531    return FALSE;
1532 }
1533
1534
1535
1536 /****i* atheros5000.device/RXInt *******************************************
1537 *
1538 *   NAME
1539 *       RXInt -- Soft interrupt for packet reception.
1540 *
1541 *   SYNOPSIS
1542 *       RXInt(unit)
1543 *
1544 *       VOID RXInt(struct DevUnit *);
1545 *
1546 *   FUNCTION
1547 *
1548 *   INPUTS
1549 *       unit - A unit of this device.
1550 *
1551 *   RESULT
1552 *       None.
1553 *
1554 ****************************************************************************
1555 *
1556 */
1557
1558 static VOID RXInt(REG(a1, struct DevUnit *unit), REG(a6, APTR int_code))
1559 {
1560    UWORD ieee_length, frame_control, frame_type, slot, next_slot,
1561       encryption, key_no, buffer_no, old_length;
1562    struct DevBase *base;
1563    BOOL is_good;
1564    LONG frag_no;
1565    struct ath_desc *rx_desc, *next_desc;
1566    ULONG dma_size, rx_desc_p;
1567    UBYTE *buffer, *p, *frame, *data, *snap_frame, *source;
1568    struct ath_rx_status status;
1569
1570    base = unit->device;
1571    slot = unit->rx_slot;
1572    rx_desc = unit->rx_descs + slot;
1573    rx_desc_p = unit->rx_descs_p + slot * sizeof(struct ath_desc);
1574    next_slot = (slot + 1) % RX_SLOT_COUNT;
1575    next_desc = unit->rx_descs + next_slot;
1576
1577    dma_size = sizeof(struct ath_desc) * RX_SLOT_COUNT;
1578    CachePostDMA(unit->rx_descs, &dma_size, 0);
1579
1580    while(unit->hal->ah_procRxDesc(unit->hal, rx_desc, rx_desc_p, next_desc,
1581       unit->hal->ah_getTsf64(unit->hal), &status) != HAL_EINPROGRESS)
1582    {
1583       is_good = TRUE;
1584       buffer = unit->rx_buffers[slot];
1585
1586       dma_size = FRAME_BUFFER_SIZE;
1587       CachePostDMA(buffer, &dma_size, 0);
1588
1589       if(status.rs_status == 0
1590          && status.rs_datalen >= WIFI_FRM_DATA + FCS_SIZE)
1591       {
1592          /* Get fragment info */
1593
1594          frame = buffer;
1595          ieee_length = status.rs_datalen - FCS_SIZE - WIFI_FRM_DATA;
1596          data = frame + WIFI_FRM_DATA;
1597          frame_control =
1598             LEWord(*(UWORD *)(frame + WIFI_FRM_CONTROL));
1599
1600          /* Get buffer to store fragment in */
1601
1602          frag_no = LEWord(*(UWORD *)(frame + WIFI_FRM_SEQCONTROL));
1603          if(unit->mode == S2PORT_ADHOC)
1604             source = frame + WIFI_FRM_ADDRESS2;
1605          else
1606             source = frame + WIFI_FRM_ADDRESS3;
1607          snap_frame = GetRXBuffer(unit, source, frag_no, &buffer_no, base);
1608
1609          /* Get location to put new data */
1610
1611          if(snap_frame != NULL)
1612          {
1613             if((frag_no & 0xf ) > 0)
1614                old_length =
1615                   BEWord(*(UWORD *)(snap_frame + ETH_PACKET_IEEELEN));
1616             else
1617             {
1618                /* Create new 802.3 header */
1619
1620                CopyMem(frame + WIFI_FRM_ADDRESS1, snap_frame,
1621                   ETH_ADDRESSSIZE);
1622                CopyMem(source, snap_frame + ETH_PACKET_SOURCE,
1623                   ETH_ADDRESSSIZE);
1624                old_length = 0;
1625             }
1626             p = snap_frame + ETH_HEADERSIZE + old_length;
1627
1628             /* Get encryption type and key index */
1629
1630             if((frame_control & WIFI_FRM_CONTROLF_WEP) != 0)
1631             {
1632                key_no = data[3] >> 6 & 0x3;
1633                encryption = unit->keys[key_no].type;
1634             }
1635             else
1636                encryption = S2ENC_NONE;
1637
1638             /* Append fragment to frame, decrypting/checking fragment if
1639                necessary */
1640
1641             is_good = unit->fragment_decrypt_functions[encryption](unit,
1642                frame, data, &ieee_length, p, base);
1643
1644             /* Update length in frame being built with current fragment, or
1645                increment bad frame counter if fragment is bad */
1646
1647             if(is_good)
1648             {
1649                ieee_length += old_length;
1650                *(UWORD *)(snap_frame + ETH_PACKET_IEEELEN) =
1651                   MakeBEWord(ieee_length);
1652             }
1653             else
1654                unit->stats.BadData++;
1655
1656             /* If all fragments have arrived, process the complete frame */
1657
1658             if((frame_control & WIFI_FRM_CONTROLF_MOREFRAGS) == 0)
1659             {
1660                if(is_good)
1661                {
1662                   /* Decrypt complete frame if necessary */
1663
1664                   data = snap_frame + ETH_HEADERSIZE;
1665                   if(encryption == S2ENC_TKIP)
1666 //                     && (unit->flags & UNITF_HARDTKIP) == 0)
1667 //                     && (unit->flags & UNITF_HARDMIC) == 0)
1668                   {
1669                      is_good = TKIPDecryptFrame(unit, snap_frame, data,
1670                         ieee_length, data, key_no, base);
1671                      ieee_length -= MIC_SIZE;
1672                      *(UWORD *)(snap_frame + ETH_PACKET_IEEELEN) =
1673                         MakeBEWord(ieee_length);
1674                      if(!is_good)
1675                         unit->stats.BadData++;
1676                   }
1677                }
1678
1679                if(is_good)
1680                {
1681                   /* Get frame's 802.11 type and subtype */
1682
1683                   frame_type = (frame_control & WIFI_FRM_CONTROLF_TYPE)
1684                      >> WIFI_FRM_CONTROLB_TYPE;
1685
1686                   /* If it's a management frame, process it separately;
1687                      otherwise distribute it to clients after filtering */
1688
1689                   if(frame_type == WIFI_FRMTYPE_MGMT)
1690                   {
1691                      DistributeMgmtFrame(unit, frame, status.rs_datalen - 4,
1692                         base);
1693                   }
1694                   else if(AddressFilter(unit, snap_frame + ETH_PACKET_DEST,
1695                      base))
1696                   {
1697                      unit->stats.PacketsReceived++;
1698                      DistributeRXPacket(unit, snap_frame, base);
1699                   }
1700                }
1701             }
1702
1703             /* Mark fragment buffer as unused for next time */
1704
1705             unit->rx_fragment_nos[buffer_no] = -1;
1706          }
1707          else
1708             ReportEvents(unit, S2EVENT_ERROR | S2EVENT_RX, base);
1709       }
1710       else
1711       {
1712          is_good = FALSE;
1713       }
1714
1715       if(!is_good)
1716       {
1717          ReportEvents(unit, S2EVENT_ERROR | S2EVENT_HARDWARE | S2EVENT_RX,
1718             base);
1719       }
1720
1721       /* Prepare descriptor for next time */
1722
1723       unit->hal->ah_setupRxDesc(unit->hal, rx_desc, FRAME_BUFFER_SIZE,
1724          HAL_RXDESC_INTREQ);
1725
1726       dma_size = FRAME_BUFFER_SIZE;
1727       CachePreDMA(buffer, &dma_size, 0);
1728
1729       /* Get next descriptor */
1730
1731       slot = next_slot;
1732       rx_desc = next_desc;
1733       rx_desc_p = unit->rx_descs_p + slot * sizeof(struct ath_desc);
1734       next_slot = (slot + 1) % RX_SLOT_COUNT;
1735       next_desc = unit->rx_descs + next_slot;
1736    }
1737
1738    dma_size = sizeof(struct ath_desc) * RX_SLOT_COUNT;
1739    CachePreDMA(unit->rx_descs, &dma_size, 0);
1740
1741    unit->rx_slot = slot;
1742 // TO DO: unstall reception?
1743
1744    /* Re-enable RX interrupts */
1745
1746 #if 0
1747    Disable();
1748    unit->hal->ah_setInterrupts(unit->hal,
1749       unit->hal->ah_getInterrupts(unit->hal) | HAL_INT_RX | HAL_INT_RXEOL);
1750    Enable();
1751 #endif
1752
1753    return;
1754 }
1755
1756
1757
1758 /****i* atheros5000.device/GetRXBuffer *************************************
1759 *
1760 *   NAME
1761 *       GetRXBuffer -- Find an appropriate RX frame buffer to use.
1762 *
1763 *   SYNOPSIS
1764 *       buffer = GetRXBuffer(unit, address, frag_no)
1765 *
1766 *       UBYTE *GetRXBuffer(struct DevUnit *, UBYTE *, UWORD);
1767 *
1768 ****************************************************************************
1769 *
1770 */
1771
1772 static UBYTE *GetRXBuffer(struct DevUnit *unit, const UBYTE *address,
1773    UWORD frag_no, UWORD *buffer_no, struct DevBase *base)
1774 {
1775    UWORD i;
1776    UBYTE *buffer;
1777    LONG n;
1778    BOOL found;
1779
1780    buffer = unit->rx_frames;
1781    for(i = 0, found = FALSE; i < FRAME_BUFFER_COUNT * 2 && !found; i++)
1782    {
1783       /* Throw away old buffer contents if we didn't find a free slot the
1784          first time around */
1785
1786       if(i >= FRAME_BUFFER_COUNT)
1787          unit->rx_fragment_nos[i % FRAME_BUFFER_COUNT] = -1;
1788
1789       /* For a frame's first fragment, find an empty slot; for subsequent
1790          fragments, find a slot with matching source address */
1791
1792       n = unit->rx_fragment_nos[i % FRAME_BUFFER_COUNT];
1793       if(n == -1 && (frag_no & 0xf) == 0
1794          || *((ULONG *)(buffer + ETH_PACKET_SOURCE))
1795          == *((ULONG *)(address))
1796          && *((UWORD *)(buffer + ETH_PACKET_SOURCE + 4))
1797          == *((UWORD *)(address + 4)))
1798       {
1799          found = TRUE;
1800          if(n == -1)
1801             unit->rx_fragment_nos[i % FRAME_BUFFER_COUNT] = frag_no;
1802          *buffer_no = i;
1803       }
1804       else
1805          buffer += FRAME_BUFFER_SIZE;
1806    }
1807
1808    if(!found)
1809       buffer = NULL;
1810
1811    return buffer;
1812 }
1813
1814
1815
1816 /****i* atheros5000.device/DistributeRXPacket ******************************
1817 *
1818 *   NAME
1819 *       DistributeRXPacket -- Send a packet to all appropriate destinations.
1820 *
1821 *   SYNOPSIS
1822 *       DistributeRXPacket(unit, frame)
1823 *
1824 *       VOID DistributeRXPacket(struct DevUnit *, UBYTE *);
1825 *
1826 ****************************************************************************
1827 *
1828 */
1829
1830 static VOID DistributeRXPacket(struct DevUnit *unit, UBYTE *frame,
1831    struct DevBase *base)
1832 {
1833    UWORD packet_size, ieee_length;
1834    BOOL is_orphan = TRUE, accepted, is_snap = FALSE;
1835    ULONG packet_type;
1836    UBYTE *buffer;
1837    const UBYTE *template = snap_template;
1838    struct IOSana2Req *request, *request_tail;
1839    struct Opener *opener, *opener_tail;
1840    struct TypeStats *tracker;
1841
1842    ieee_length = BEWord(*(UWORD *)(frame + ETH_PACKET_IEEELEN));
1843    packet_size = ETH_HEADERSIZE + ieee_length;
1844    if(ieee_length >= SNAP_HEADERSIZE)
1845       is_snap = *(const ULONG *)(frame + ETH_PACKET_DATA)
1846          == *(const ULONG *)template;
1847
1848    /* De-encapsulate SNAP packets and get packet type */
1849
1850    if(is_snap)
1851    {
1852       buffer = unit->rx_buffer;
1853       packet_size -= SNAP_HEADERSIZE;
1854       CopyMem(frame, buffer, ETH_PACKET_TYPE);
1855       CopyMem(frame + ETH_HEADERSIZE + SNAP_FRM_TYPE,
1856          buffer + ETH_PACKET_TYPE, packet_size - ETH_PACKET_TYPE);
1857    }
1858    else
1859       buffer = frame;
1860
1861    packet_type = BEWord(*((UWORD *)(buffer + ETH_PACKET_TYPE)));
1862
1863    if(packet_size <= ETH_MAXPACKETSIZE)
1864    {
1865       /* Offer packet to every opener */
1866
1867       opener = (APTR)unit->openers.mlh_Head;
1868       opener_tail = (APTR)&unit->openers.mlh_Tail;
1869
1870       while(opener != opener_tail)
1871       {
1872          request = (APTR)opener->read_port.mp_MsgList.lh_Head;
1873          request_tail = (APTR)&opener->read_port.mp_MsgList.lh_Tail;
1874          accepted = FALSE;
1875
1876          /* Offer packet to each request until it's accepted */
1877
1878          while(request != request_tail && !accepted)
1879          {
1880             if(request->ios2_PacketType == packet_type)
1881             {
1882                CopyPacket(unit, request, packet_size, packet_type,
1883                   buffer, base);
1884                accepted = TRUE;
1885             }
1886             request =
1887                (APTR)request->ios2_Req.io_Message.mn_Node.ln_Succ;
1888          }
1889
1890          if(accepted)
1891             is_orphan = FALSE;
1892          opener = (APTR)opener->node.mln_Succ;
1893       }
1894
1895       /* If packet was unwanted, give it to S2_READORPHAN request */
1896
1897       if(is_orphan)
1898       {
1899          unit->stats.UnknownTypesReceived++;
1900          if(!IsMsgPortEmpty(unit->request_ports[ADOPT_QUEUE]))
1901          {
1902             CopyPacket(unit,
1903                (APTR)unit->request_ports[ADOPT_QUEUE]->
1904                mp_MsgList.lh_Head, packet_size, packet_type, buffer,
1905                base);
1906          }
1907       }
1908
1909       /* Update remaining statistics */
1910
1911       if(packet_type <= ETH_MTU)
1912          packet_type = ETH_MTU;
1913       tracker =
1914          FindTypeStats(unit, &unit->type_trackers, packet_type, base);
1915       if(tracker != NULL)
1916       {
1917          tracker->stats.PacketsReceived++;
1918          tracker->stats.BytesReceived += packet_size;
1919       }
1920    }
1921    else
1922       unit->stats.BadData++;
1923
1924    return;
1925 }
1926
1927
1928
1929 /****i* atheros5000.device/CopyPacket **************************************
1930 *
1931 *   NAME
1932 *       CopyPacket -- Copy packet to client's buffer.
1933 *
1934 *   SYNOPSIS
1935 *       CopyPacket(unit, request, packet_size, packet_type,
1936 *           buffer)
1937 *
1938 *       VOID CopyPacket(struct DevUnit *, struct IOSana2Req *, UWORD, UWORD,
1939 *           UBYTE *);
1940 *
1941 ****************************************************************************
1942 *
1943 */
1944
1945 static VOID CopyPacket(struct DevUnit *unit, struct IOSana2Req *request,
1946    UWORD packet_size, UWORD packet_type, UBYTE *buffer,
1947    struct DevBase *base)
1948 {
1949    struct Opener *opener;
1950    BOOL filtered = FALSE;
1951
1952    /* Set multicast and broadcast flags */
1953
1954    request->ios2_Req.io_Flags &= ~(SANA2IOF_BCAST | SANA2IOF_MCAST);
1955    if((*((ULONG *)(buffer + ETH_PACKET_DEST)) == 0xffffffff) &&
1956       (*((UWORD *)(buffer + ETH_PACKET_DEST + 4)) == 0xffff))
1957       request->ios2_Req.io_Flags |= SANA2IOF_BCAST;
1958    else if((buffer[ETH_PACKET_DEST] & 0x1) != 0)
1959       request->ios2_Req.io_Flags |= SANA2IOF_MCAST;
1960
1961    /* Set source and destination addresses and packet type */
1962
1963    CopyMem(buffer + ETH_PACKET_SOURCE, request->ios2_SrcAddr,
1964       ETH_ADDRESSSIZE);
1965    CopyMem(buffer + ETH_PACKET_DEST, request->ios2_DstAddr,
1966       ETH_ADDRESSSIZE);
1967    request->ios2_PacketType = packet_type;
1968
1969    /* Adjust for cooked packet request */
1970
1971    if((request->ios2_Req.io_Flags & SANA2IOF_RAW) == 0)
1972    {
1973       packet_size -= ETH_PACKET_DATA;
1974       buffer += ETH_PACKET_DATA;
1975    }
1976 #ifdef USE_HACKS
1977    else
1978       packet_size += 4;   /* Needed for Shapeshifter & Fusion? */
1979 #endif
1980    request->ios2_DataLength = packet_size;
1981
1982    /* Filter packet */
1983
1984    opener = request->ios2_BufferManagement;
1985    if(request->ios2_Req.io_Command == CMD_READ &&
1986       opener->filter_hook != NULL)
1987       if(!CallHookPkt(opener->filter_hook, request, buffer))
1988          filtered = TRUE;
1989
1990    if(!filtered)
1991    {
1992       /* Copy packet into opener's buffer and reply packet */
1993
1994       if(!opener->rx_function(request->ios2_Data, buffer, packet_size))
1995       {
1996          request->ios2_Req.io_Error = S2ERR_NO_RESOURCES;
1997          request->ios2_WireError = S2WERR_BUFF_ERROR;
1998          ReportEvents(unit,
1999             S2EVENT_ERROR | S2EVENT_SOFTWARE | S2EVENT_BUFF | S2EVENT_RX,
2000             base);
2001       }
2002       Remove((APTR)request);
2003       ReplyMsg((APTR)request);
2004    }
2005
2006    return;
2007 }
2008
2009
2010
2011 /****i* atheros5000.device/AddressFilter ***********************************
2012 *
2013 *   NAME
2014 *       AddressFilter -- Determine if an RX packet should be accepted.
2015 *
2016 *   SYNOPSIS
2017 *       accept = AddressFilter(unit, address)
2018 *
2019 *       BOOL AddressFilter(struct DevUnit *, UBYTE *);
2020 *
2021 ****************************************************************************
2022 *
2023 */
2024
2025 static BOOL AddressFilter(struct DevUnit *unit, UBYTE *address,
2026    struct DevBase *base)
2027 {
2028    struct AddressRange *range, *tail;
2029    BOOL accept = TRUE;
2030    ULONG address_left;
2031    UWORD address_right;
2032
2033    /* Check whether address is unicast/broadcast or multicast */
2034
2035    address_left = BELong(*((ULONG *)address));
2036    address_right = BEWord(*((UWORD *)(address + 4)));
2037
2038    if(((address_left & 0x01000000) != 0) &&
2039       !((address_left == 0xffffffff) && (address_right == 0xffff)))
2040    {
2041       /* Check if this multicast address is wanted */
2042
2043       range = (APTR)unit->multicast_ranges.mlh_Head;
2044       tail = (APTR)&unit->multicast_ranges.mlh_Tail;
2045       accept = FALSE;
2046
2047       while((range != tail) && !accept)
2048       {
2049          if((address_left > range->lower_bound_left ||
2050             address_left == range->lower_bound_left &&
2051             address_right >= range->lower_bound_right) &&
2052             (address_left < range->upper_bound_left ||
2053             address_left == range->upper_bound_left &&
2054             address_right <= range->upper_bound_right))
2055             accept = TRUE;
2056          range = (APTR)range->node.mln_Succ;
2057       }
2058
2059       if(!accept)
2060          unit->special_stats[S2SS_ETHERNET_BADMULTICAST & 0xffff]++;
2061    }
2062
2063    return accept;
2064 }
2065
2066
2067
2068 /****i* atheros5000.device/DistributeMgmtFrame *****************************
2069 *
2070 *   NAME
2071 *       DistributeMgmtFrame -- Send a management frame to clients.
2072 *
2073 *   SYNOPSIS
2074 *       DistributeMgmtFrame(unit, frame, frame_size)
2075 *
2076 *       VOID DistributeMgmtFrame(struct DevUnit *, UBYTE *, UWORD);
2077 *
2078 ****************************************************************************
2079 *
2080 */
2081
2082 static VOID DistributeMgmtFrame(struct DevUnit *unit, UBYTE *frame,
2083    UWORD frame_size, struct DevBase *base)
2084 {
2085    struct IOSana2Req *request;
2086    struct Opener *opener, *opener_tail;
2087
2088    /* Send packet to every opener */
2089
2090    opener = (APTR)unit->openers.mlh_Head;
2091    opener_tail = (APTR)&unit->openers.mlh_Tail;
2092
2093    while(opener != opener_tail)
2094    {
2095       request = (APTR)RemHead(&opener->mgmt_port.mp_MsgList);
2096
2097       if(request != NULL)
2098       {
2099          /* Copy packet into opener's buffer and reply packet */
2100
2101          if(frame_size <= request->ios2_DataLength)
2102          {
2103             CopyMem(frame, request->ios2_Data, frame_size);
2104             request->ios2_DataLength = frame_size;
2105          }
2106          else
2107          {
2108             request->ios2_Req.io_Error = S2ERR_NO_RESOURCES;
2109             request->ios2_WireError = S2WERR_BUFF_ERROR;
2110             ReportEvents(unit,
2111                S2EVENT_ERROR | S2EVENT_SOFTWARE | S2EVENT_BUFF | S2EVENT_RX,
2112                base);
2113          }
2114          ReplyMsg((APTR)request);
2115          request =
2116             (APTR)request->ios2_Req.io_Message.mn_Node.ln_Succ;
2117       }
2118
2119       opener = (APTR)opener->node.mln_Succ;
2120    }
2121
2122    return;
2123 }
2124
2125
2126
2127 /****i* atheros5000.device/TXInt *******************************************
2128 *
2129 *   NAME
2130 *       TXInt -- Soft interrupt for packet transmission.
2131 *
2132 *   SYNOPSIS
2133 *       TXInt(unit)
2134 *
2135 *       VOID TXInt(struct DevUnit *);
2136 *
2137 *   FUNCTION
2138 *
2139 *   INPUTS
2140 *       unit - A unit of this device.
2141 *
2142 *   RESULT
2143 *       None.
2144 *
2145 ****************************************************************************
2146 *
2147 */
2148
2149 static VOID TXInt(REG(a1, struct DevUnit *unit), REG(a6, APTR int_code))
2150 {
2151    struct DevBase *base;
2152    UWORD i, frame_size, data_size, packet_type, body_size, slot, new_slot,
2153       last_slot, encryption, subtype, duration;
2154    UBYTE *buffer, *q, *plaintext, *ciphertext, *frame,
2155       mic_header[ETH_ADDRESSSIZE * 2];
2156    const UBYTE *p, *dest, *source;
2157    struct IOSana2Req *request;
2158    BOOL proceed = TRUE, is_ieee;
2159    struct Opener *opener;
2160    ULONG wire_error, dma_size;
2161    struct ath_desc *tx_desc, *last_desc;
2162    UBYTE *(*dma_tx_function)(REG(a0, APTR));
2163    BYTE error;
2164    struct MsgPort *port;
2165    struct TypeStats *tracker;
2166    const HAL_RATE_TABLE *rate_table;
2167
2168    base = unit->device;
2169    port = unit->request_ports[WRITE_QUEUE];
2170    rate_table = unit->rate_table;
2171
2172    while(proceed && (!IsMsgPortEmpty(port)))
2173    {
2174       slot = unit->tx_in_slot;
2175       new_slot = (slot + 1) % TX_SLOT_COUNT;
2176
2177 //      if(new_slot != unit->tx_out_slot)
2178       if(slot == unit->tx_out_slot)   // one packet at a time
2179       {
2180          error = 0;
2181          body_size = 0;
2182
2183          /* Get request and DMA frame descriptor */
2184
2185          request = (APTR)port->mp_MsgList.lh_Head;
2186
2187          Remove((APTR)request);
2188          unit->tx_requests[slot] = request;
2189          tx_desc = unit->tx_descs + slot;
2190          frame = unit->tx_buffers[slot];
2191
2192          /* Get packet data */
2193
2194          opener = request->ios2_BufferManagement;
2195          dma_tx_function = opener->dma_tx_function;
2196          if(dma_tx_function != NULL)
2197             buffer = dma_tx_function(request->ios2_Data);
2198          else
2199             buffer = NULL;
2200
2201          if(buffer == NULL)
2202          {
2203             buffer = unit->tx_buffer;
2204             if(!opener->tx_function(buffer, request->ios2_Data,
2205                request->ios2_DataLength))
2206             {
2207                error = S2ERR_NO_RESOURCES;
2208                wire_error = S2WERR_BUFF_ERROR;
2209                ReportEvents(unit,
2210                   S2EVENT_ERROR | S2EVENT_SOFTWARE | S2EVENT_BUFF
2211                   | S2EVENT_TX, base);
2212             }
2213          }
2214
2215          if(error == 0)
2216          {
2217             /* Get packet type and/or length */
2218
2219             data_size = request->ios2_DataLength;
2220             if((request->ios2_Req.io_Flags & SANA2IOF_RAW) != 0)
2221             {
2222                data_size -= ETH_PACKET_DATA;
2223                packet_type = BEWord(*(UWORD *)(buffer + ETH_PACKET_TYPE));
2224             }
2225             else
2226                packet_type = request->ios2_PacketType;
2227             is_ieee = packet_type <= ETH_MTU;
2228
2229             /* Determine encryption type and frame subtype */
2230
2231             if(data_size > 0)
2232             {
2233                encryption = unit->keys[unit->tx_key_no].type;
2234                subtype = 0;
2235             }
2236             else
2237             {
2238                encryption = S2ENC_NONE;
2239                subtype = 4;
2240             }
2241
2242             /* Get source and destination addresses */
2243
2244             if((request->ios2_Req.io_Flags & SANA2IOF_RAW) != 0)
2245             {
2246                dest = buffer;
2247                source = buffer + ETH_ADDRESSSIZE;
2248                buffer += ETH_ADDRESSSIZE * 2 + 2;
2249             }
2250             else
2251             {
2252                dest = request->ios2_DstAddr;
2253                source = unit->address;
2254             }
2255
2256             /* Write 802.11 header */
2257
2258             q = frame;
2259             *(UWORD *)q = MakeLEWord(
2260                (encryption == S2ENC_NONE ? 0 : WIFI_FRM_CONTROLF_WEP)
2261                | (unit->mode == S2PORT_ADHOC ? 0 : WIFI_FRM_CONTROLF_TODS)
2262                | subtype << WIFI_FRM_CONTROLB_SUBTYPE
2263                | WIFI_FRMTYPE_DATA << WIFI_FRM_CONTROLB_TYPE);
2264             q += 2;
2265
2266             i = rate_table->rateCodeToIndex[unit->tx_rate_codes[0]];
2267             if((unit->flags & UNITF_SHORTPREAMBLE) != 0)
2268                duration = rate_table->info[i].spAckDuration;
2269             else
2270                duration = rate_table->info[i].lpAckDuration;
2271             *(UWORD *)q = MakeLEWord(duration);
2272             q += 2;
2273
2274             if(unit->mode == S2PORT_ADHOC)
2275                p = dest;
2276             else
2277                p = unit->bssid;
2278             for(i = 0; i < ETH_ADDRESSSIZE; i++)
2279                *q++ = *p++;
2280
2281             for(i = 0, p = source; i < ETH_ADDRESSSIZE; i++)
2282                *q++ = *p++;
2283
2284             if(unit->mode == S2PORT_ADHOC)
2285                p = unit->bssid;
2286             else
2287                p = dest;
2288             for(i = 0; i < ETH_ADDRESSSIZE; i++)
2289                *q++ = *p++;
2290             *(UWORD *)q = 0;
2291             q += 2;
2292
2293 // TO DO: need to pad header to 4-byte boundary?
2294
2295             /* Leave room for encryption overhead */
2296
2297             ciphertext = q;
2298             q += unit->iv_sizes[encryption];
2299             plaintext = q;
2300
2301             /* Write SNAP header */
2302
2303             if(!is_ieee)
2304             {
2305                for(i = 0, p = snap_template;
2306                   i < SNAP_FRM_TYPE; i++)
2307                   *q++ = *p++;
2308                *(UWORD *)q = MakeBEWord(packet_type);
2309                q += 2;
2310                body_size += SNAP_HEADERSIZE;
2311             }
2312
2313             /* Copy data into frame */
2314
2315             CopyMem(buffer, q, data_size);
2316             body_size += data_size;
2317
2318             /* Append MIC to frame for TKIP */
2319
2320             if(encryption == S2ENC_TKIP)
2321             {
2322 //               if((unit->flags & UNITF_HARDMIC) == 0)
2323                {
2324                   q = mic_header;
2325                   for(i = 0, p = dest; i < ETH_ADDRESSSIZE; i++)
2326                      *q++ = *p++;
2327                   for(i = 0, p = source; i < ETH_ADDRESSSIZE; i++)
2328                      *q++ = *p++;
2329                   TKIPEncryptFrame(unit, mic_header, plaintext, body_size,
2330                      plaintext, base);
2331                }
2332                body_size += MIC_SIZE;
2333             }
2334
2335             /* Encrypt fragment if applicable */
2336
2337             unit->fragment_encrypt_functions[encryption](unit, frame,
2338                plaintext, &body_size, ciphertext, base);
2339
2340             /* Fill in DMA descriptor for packet transmission */
2341
2342             frame_size = WIFI_FRM_DATA + body_size;
2343             tx_desc->ds_link = (ULONG)(UPINT)NULL;
2344             unit->hal->ah_setupTxDesc(unit->hal, tx_desc, frame_size + 4, // + CRC?
2345                WIFI_FRM_DATA, HAL_PKT_TYPE_NORMAL, TX_POWER,
2346                ((unit->flags & UNITF_SLOWRETRIES) != 0) ?
2347                   unit->tx_rate_codes[0] : unit->tx_rate_codes[1],
2348                ((unit->flags & UNITF_SLOWRETRIES) != 0) ? 1 : TX_TRIES,
2349                HAL_TXKEYIX_INVALID,
2350                HAL_ANTENNA_MIN_MODE,
2351                HAL_TXDESC_INTREQ | HAL_TXDESC_CLRDMASK,
2352                0, 0, 0, 0, 3);
2353             if((unit->flags & UNITF_SLOWRETRIES) != 0)
2354                unit->hal->ah_setupXTxDesc(unit->hal, tx_desc,
2355                   unit->tx_rate_codes[1], 1,
2356                   unit->tx_rate_codes[2], 1,
2357                   unit->tx_rate_codes[3], TX_TRIES - 3);
2358             unit->hal->ah_fillTxDesc(unit->hal, tx_desc, frame_size, TRUE, TRUE,
2359                tx_desc);
2360
2361             dma_size = frame_size;
2362             CachePreDMA(frame, &dma_size, DMA_ReadFromRAM);
2363
2364             /* Pass packet to adapter */
2365
2366             unit->hal->ah_stopTxDma(unit->hal, unit->tx_queue_no);
2367             last_slot = (slot + TX_SLOT_COUNT - 1) % TX_SLOT_COUNT;
2368             if(unit->tx_out_slot != slot)
2369             //if(unit->hal->ah_numTxPending(unit->hal, unit->tx_queue_no) > 0)
2370             {
2371                last_desc =
2372                   unit->tx_descs + last_slot;
2373                last_desc->ds_link = unit->tx_descs_p + slot * sizeof(struct ath_desc);
2374                dma_size = sizeof(struct ath_desc) * TX_SLOT_COUNT;
2375                CachePreDMA(unit->tx_descs, &dma_size, 0);
2376             }
2377             else
2378             {
2379                dma_size = sizeof(struct ath_desc) * TX_SLOT_COUNT;
2380                CachePreDMA(unit->tx_descs, &dma_size, 0);
2381                unit->hal->ah_setTxDP(unit->hal, unit->tx_queue_no,
2382                   unit->tx_descs_p + slot * sizeof(struct ath_desc));
2383             }
2384
2385             unit->hal->ah_startTxDma(unit->hal, unit->tx_queue_no);
2386             unit->tx_in_slot = new_slot;
2387          }
2388          else
2389          {
2390             /* Reply failed request */
2391
2392             request->ios2_Req.io_Error = error;
2393             request->ios2_WireError = wire_error;
2394             ReplyMsg((APTR)request);
2395          }
2396
2397          /* Update statistics */
2398
2399          if(error == 0)
2400          {
2401             unit->stats.PacketsSent++;
2402
2403             tracker = FindTypeStats(unit, &unit->type_trackers,
2404                request->ios2_PacketType, base);
2405             if(tracker != NULL)
2406             {
2407                tracker->stats.PacketsSent++;
2408                tracker->stats.BytesSent += ETH_HEADERSIZE + data_size;
2409             }
2410          }
2411       }
2412       else
2413          proceed = FALSE;
2414    }
2415
2416    /* Don't try to keep sending packets if there's no space left */
2417
2418    if(proceed)
2419       unit->request_ports[WRITE_QUEUE]->mp_Flags = PA_SOFTINT;
2420    else
2421       unit->request_ports[WRITE_QUEUE]->mp_Flags = PA_IGNORE;
2422
2423    return;
2424 }
2425
2426
2427
2428 /****i* atheros5000.device/TXEndInt ****************************************
2429 *
2430 *   NAME
2431 *       TXEndInt -- Clean up after a data frame has been sent.
2432 *
2433 *   SYNOPSIS
2434 *       TXEndInt(unit, int_code)
2435 *
2436 *       VOID TXEndInt(struct DevUnit *, APTR);
2437 *
2438 *   NOTES
2439 *       I think it's safe to assume that there will always be at least one
2440 *       completed packet whenever this interrupt is called.
2441 *
2442 ****************************************************************************
2443 *
2444 */
2445
2446 static VOID TXEndInt(REG(a1, struct DevUnit *unit),
2447    REG(a6, APTR int_code))
2448 {
2449    UWORD frame_size, new_out_slot, i;
2450    UBYTE *frame;
2451    struct DevBase *base;
2452    struct IOSana2Req *request;
2453    ULONG dma_size;
2454    struct TypeStats *tracker;
2455
2456    /* Find out which packets have completed */
2457
2458    base = unit->device;
2459    new_out_slot = (unit->tx_in_slot + TX_SLOT_COUNT
2460       - unit->hal->ah_numTxPending(unit->hal, unit->tx_queue_no))
2461       % TX_SLOT_COUNT;
2462
2463    dma_size = sizeof(struct ath_desc) * TX_SLOT_COUNT;
2464    CachePostDMA(unit->tx_descs, &dma_size, 0);
2465
2466    /* Retire sent packets */
2467
2468    for(i = unit->tx_out_slot; i != new_out_slot;
2469       i = (i + 1) % TX_SLOT_COUNT)
2470    {
2471       frame = unit->tx_buffers[i];
2472       dma_size = FRAME_BUFFER_SIZE;
2473       CachePostDMA(frame, &dma_size, DMA_ReadFromRAM);
2474
2475       /* Update statistics */
2476
2477       request = unit->tx_requests[i];
2478       frame_size = request->ios2_DataLength;
2479       if((request->ios2_Req.io_Flags & SANA2IOF_RAW) == 0)
2480          frame_size += ETH_HEADERSIZE;
2481
2482       tracker = FindTypeStats(unit, &unit->type_trackers,
2483          request->ios2_PacketType, base);
2484       if(tracker != NULL)
2485       {
2486          tracker->stats.PacketsSent++;
2487          tracker->stats.BytesSent += frame_size;
2488       }
2489
2490       /* Reply request */
2491
2492       request->ios2_Req.io_Error = 0;
2493       ReplyMsg((APTR)request);
2494    }
2495
2496    unit->tx_out_slot = i;
2497
2498    dma_size = sizeof(struct ath_desc) * TX_SLOT_COUNT;
2499    CachePreDMA(unit->tx_descs, &dma_size, 0);
2500
2501    /* Restart downloads if they had stopped */
2502
2503    if(unit->request_ports[WRITE_QUEUE]->mp_Flags == PA_IGNORE)
2504       Cause(&unit->tx_int);
2505
2506    return;
2507 }
2508
2509
2510
2511 /****i* atheros5000.device/MgmtTXInt ***************************************
2512 *
2513 *   NAME
2514 *       MgmtTXInt -- Soft interrupt for management frame transmission.
2515 *
2516 *   SYNOPSIS
2517 *       MgmtTXInt(unit)
2518 *
2519 *       VOID MgmtTXInt(struct DevUnit *);
2520 *
2521 *   FUNCTION
2522 *
2523 *   INPUTS
2524 *       unit - A unit of this device.
2525 *
2526 *   RESULT
2527 *       None.
2528 *
2529 ****************************************************************************
2530 *
2531 */
2532
2533 static VOID MgmtTXInt(REG(a1, struct DevUnit *unit), REG(a6, APTR int_code))
2534 {
2535    struct DevBase *base;
2536    UWORD frame_size, slot, new_slot, last_slot, i, duration;
2537    UBYTE *frame;
2538    struct IOSana2Req *request;
2539    BOOL proceed = TRUE, has_bssid;
2540    ULONG dma_size;
2541    struct ath_desc *desc, *last_desc;
2542    struct MsgPort *port;
2543    const HAL_RATE_TABLE *rate_table;
2544
2545    base = unit->device;
2546    port = unit->request_ports[MGMT_QUEUE];
2547    rate_table = unit->rate_table;
2548
2549    while(proceed && (!IsMsgPortEmpty(port)))
2550    {
2551       slot = unit->mgmt_in_slot;
2552       new_slot = (slot + 1) % MGMT_SLOT_COUNT;
2553
2554 //      if(new_slot != unit->mgmt_out_slot)
2555       if(slot == unit->mgmt_out_slot)   // one packet at a time
2556       {
2557          /* Get request and DMA frame descriptor */
2558
2559          request = (APTR)port->mp_MsgList.lh_Head;
2560
2561          Remove((APTR)request);
2562          unit->mgmt_requests[slot] = request;
2563          desc = unit->mgmt_descs + slot;
2564          frame = unit->mgmt_buffers[slot];
2565
2566          /* Get packet length */
2567
2568          frame_size = request->ios2_DataLength;
2569
2570          /* Copy frame into DMA buffer */
2571
2572          CopyMem(request->ios2_Data, frame, frame_size);
2573
2574          /* Set duration */
2575
2576          has_bssid = ((frame + WIFI_FRM_ADDRESS1)[0] & 0x1) == 0;
2577          i = rate_table->rateCodeToIndex[unit->mgmt_rate_code];
2578          if(has_bssid)
2579          {
2580             if((unit->flags & UNITF_SHORTPREAMBLE) != 0)
2581                duration = rate_table->info[i].spAckDuration;
2582             else
2583                duration = rate_table->info[i].lpAckDuration;
2584          }
2585          else
2586             duration = 0;
2587          *(UWORD *)(frame + WIFI_FRM_DURATION) = MakeLEWord(duration);
2588
2589          /* Fill in DMA descriptor for packet transmission */
2590
2591          desc->ds_link = (ULONG)(UPINT)NULL;
2592          unit->hal->ah_setupTxDesc(unit->hal, desc, frame_size + 4, // + CRC?
2593             WIFI_FRM_DATA, HAL_PKT_TYPE_NORMAL, TX_POWER,
2594             unit->mgmt_rate_code, TX_TRIES, HAL_TXKEYIX_INVALID,
2595             HAL_ANTENNA_MIN_MODE,
2596             HAL_TXDESC_INTREQ | HAL_TXDESC_CLRDMASK
2597             | (has_bssid ? 0 : HAL_TXDESC_NOACK),
2598             0, 0, 0, 0, 3);
2599          unit->hal->ah_fillTxDesc(unit->hal, desc, frame_size, TRUE, TRUE,
2600             desc);
2601
2602          dma_size = frame_size;
2603          CachePreDMA(frame, &dma_size, DMA_ReadFromRAM);
2604
2605          /* Pass packet to adapter */
2606
2607          unit->hal->ah_stopTxDma(unit->hal, unit->mgmt_queue_no);
2608          last_slot = (slot + MGMT_SLOT_COUNT - 1) % MGMT_SLOT_COUNT;
2609          if(unit->mgmt_out_slot != slot)
2610          //if(unit->hal->ah_numTxPending(unit->hal, unit->mgmt_queue_no) > 0)
2611          {
2612             last_desc = unit->mgmt_descs + last_slot;
2613             last_desc->ds_link =
2614                unit->mgmt_descs_p + slot * sizeof(struct ath_desc);
2615             dma_size = sizeof(struct ath_desc) * MGMT_SLOT_COUNT;
2616             CachePreDMA(unit->mgmt_descs, &dma_size, 0);
2617          }
2618          else
2619          {
2620             dma_size = sizeof(struct ath_desc) * MGMT_SLOT_COUNT;
2621             CachePreDMA(unit->mgmt_descs, &dma_size, 0);
2622             unit->hal->ah_setTxDP(unit->hal, unit->mgmt_queue_no,
2623                unit->mgmt_descs_p + slot * sizeof(struct ath_desc));
2624          }
2625
2626          unit->hal->ah_startTxDma(unit->hal, unit->mgmt_queue_no);
2627          unit->mgmt_in_slot = new_slot;
2628       }
2629       else
2630          proceed = FALSE;
2631    }
2632
2633    /* Don't try to keep sending packets if there's no space left */
2634
2635    if(proceed)
2636       unit->request_ports[MGMT_QUEUE]->mp_Flags = PA_SOFTINT;
2637    else
2638       unit->request_ports[MGMT_QUEUE]->mp_Flags = PA_IGNORE;
2639
2640    return;
2641 }
2642
2643
2644
2645 /****i* atheros5000.device/MgmtTXEndInt ************************************
2646 *
2647 *   NAME
2648 *       MgmtTXEndInt -- Clean up after a management frame has been sent.
2649 *
2650 *   SYNOPSIS
2651 *       MgmtTXEndInt(unit, int_code)
2652 *
2653 *       VOID MgmtTXEndInt(struct DevUnit *, APTR);
2654 *
2655 *   NOTES
2656 *       I think it's safe to assume that there will always be at least one
2657 *       completed packet whenever this interrupt is called.
2658 *
2659 ****************************************************************************
2660 *
2661 */
2662
2663 static VOID MgmtTXEndInt(REG(a1, struct DevUnit *unit),
2664    REG(a6, APTR int_code))
2665 {
2666    UWORD new_out_slot, i;
2667    UBYTE *frame;
2668    struct DevBase *base;
2669    struct IOSana2Req *request;
2670    ULONG dma_size;
2671
2672    /* Find out which packets have completed */
2673
2674    base = unit->device;
2675    new_out_slot = (unit->mgmt_in_slot + MGMT_SLOT_COUNT
2676       - unit->hal->ah_numTxPending(unit->hal, unit->mgmt_queue_no))
2677       % MGMT_SLOT_COUNT;
2678
2679    dma_size = sizeof(struct ath_desc) * MGMT_SLOT_COUNT;
2680    CachePostDMA(unit->mgmt_descs, &dma_size, 0);
2681
2682    /* Retire sent frames */
2683
2684    for(i = unit->mgmt_out_slot; i != new_out_slot;
2685       i = (i + 1) % MGMT_SLOT_COUNT)
2686    {
2687       frame = unit->mgmt_buffers[i];
2688       dma_size = FRAME_BUFFER_SIZE;
2689       CachePostDMA(frame, &dma_size, DMA_ReadFromRAM);
2690
2691       /* Reply request */
2692
2693       request = unit->mgmt_requests[i];
2694       request->ios2_Req.io_Error = 0;
2695       ReplyMsg((APTR)request);
2696    }
2697
2698    unit->mgmt_out_slot = i;
2699
2700    dma_size = sizeof(struct ath_desc) * MGMT_SLOT_COUNT;
2701    CachePreDMA(unit->mgmt_descs, &dma_size, 0);
2702
2703    /* Restart downloads if they had stopped */
2704
2705    if(unit->request_ports[MGMT_QUEUE]->mp_Flags == PA_IGNORE)
2706       Cause(&unit->mgmt_int);
2707
2708    return;
2709 }
2710
2711
2712
2713 /****i* atheros5000.device/ResetHandler ************************************
2714 *
2715 *   NAME
2716 *       ResetHandler -- Disable hardware before a reboot.
2717 *
2718 *   SYNOPSIS
2719 *       ResetHandler(unit, int_code)
2720 *
2721 *       VOID ResetHandler(struct DevUnit *, APTR);
2722 *
2723 ****************************************************************************
2724 *
2725 */
2726
2727 static VOID ResetHandler(REG(a1, struct DevUnit *unit),
2728    REG(a6, APTR int_code))
2729 {
2730    if((unit->flags & UNITF_HAVEADAPTER) != 0)
2731    {
2732       /* Disable frame transmission */
2733
2734       unit->hal->ah_stopTxDma(unit->hal, unit->tx_queue_no);
2735       unit->hal->ah_stopTxDma(unit->hal, unit->mgmt_queue_no);
2736
2737       /* Disable frame reception */
2738
2739       unit->hal->ah_stopPcuReceive(unit->hal);
2740       unit->hal->ah_stopDmaReceive(unit->hal);
2741
2742       /* Stop interrupts */
2743
2744       unit->hal->ah_setInterrupts(unit->hal, 0);
2745    }
2746
2747    return;
2748 }
2749
2750
2751
2752 /****i* atheros5000.device/UpdateStats *************************************
2753 *
2754 *   NAME
2755 *       UpdateStats
2756 *
2757 *   SYNOPSIS
2758 *       UpdateStats(unit)
2759 *
2760 *       VOID UpdateStats(struct DevUnit *);
2761 *
2762 *   FUNCTION
2763 *
2764 *   INPUTS
2765 *       unit - A unit of this device.
2766 *
2767 *   RESULT
2768 *       None.
2769 *
2770 ****************************************************************************
2771 *
2772 */
2773
2774 VOID UpdateStats(struct DevUnit *unit, struct DevBase *base)
2775 {
2776    /* Ask for and wait for stats */
2777
2778    return;
2779 }
2780
2781
2782
2783 /****i* atheros5000.device/ReportEvents ************************************
2784 *
2785 *   NAME
2786 *       ReportEvents
2787 *
2788 *   SYNOPSIS
2789 *       ReportEvents(unit, events)
2790 *
2791 *       VOID ReportEvents(struct DevUnit *, ULONG);
2792 *
2793 *   FUNCTION
2794 *
2795 *   INPUTS
2796 *       unit - A unit of this device.
2797 *       events - A mask of events to report.
2798 *
2799 *   RESULT
2800 *       None.
2801 *
2802 ****************************************************************************
2803 *
2804 */
2805
2806 static VOID ReportEvents(struct DevUnit *unit, ULONG events,
2807    struct DevBase *base)
2808 {
2809    struct IOSana2Req *request, *tail, *next_request;
2810    struct List *list;
2811
2812    list = &unit->request_ports[EVENT_QUEUE]->mp_MsgList;
2813    next_request = (APTR)list->lh_Head;
2814    tail = (APTR)&list->lh_Tail;
2815
2816    Disable();
2817    while(next_request != tail)
2818    {
2819       request = next_request;
2820       next_request = (APTR)request->ios2_Req.io_Message.mn_Node.ln_Succ;
2821
2822       if((request->ios2_WireError & events) != 0)
2823       {
2824          request->ios2_WireError = events;
2825          Remove((APTR)request);
2826          ReplyMsg((APTR)request);
2827       }
2828    }
2829    Enable();
2830
2831    return;
2832 }
2833
2834
2835
2836 /****i* atheros5000.device/GetRadioBands ***********************************
2837 *
2838 *   NAME
2839 *       GetRadioBands -- Get information on current network.
2840 *
2841 *   SYNOPSIS
2842 *       tag_list = GetRadioBands(unit, pool)
2843 *
2844 *       struct TagItem *GetRadioBands(struct DevUnit *, APTR);
2845 *
2846 *   FUNCTION
2847 *
2848 *   INPUTS
2849 *       unit - A unit of this device.
2850 *       pool - A memory pool.
2851 *
2852 *   RESULT
2853 *       None.
2854 *
2855 ****************************************************************************
2856 *
2857 */
2858
2859 #if 0
2860 struct TagItem *GetRadioBands(struct DevUnit *unit, APTR pool,
2861    struct DevBase *base)
2862 {
2863    BYTE error = 0;
2864    struct Sana2RadioBand *bands;
2865    UWORD i;
2866
2867    bands = AllocPooled(pool, sizeof(struct Sana2RadioBand) * 3);
2868    if(bands == NULL)
2869       error = S2ERR_NO_RESOURCES;
2870
2871    if(error == 0)
2872    {
2873       for(i = 0; i < 1; i++)
2874       {
2875          bands[i] = AllocPooled(pool, sizeof(UWORD) * unit->channel_counts[S2BAND_B]);
2876       }
2877    }
2878
2879 //   if(error != 0)
2880 //      bands = NULL;
2881
2882    return bands;
2883 }
2884 #endif
2885
2886
2887
2888 /****i* atheros5000.device/UnitTask ****************************************
2889 *
2890 *   NAME
2891 *       UnitTask
2892 *
2893 *   SYNOPSIS
2894 *       UnitTask()
2895 *
2896 *       VOID UnitTask();
2897 *
2898 *   FUNCTION
2899 *       Completes deferred requests, and handles card insertion and removal
2900 *       in conjunction with the relevant interrupts.
2901 *
2902 ****************************************************************************
2903 *
2904 */
2905
2906 #ifdef __MORPHOS__
2907 #undef UnitTask
2908 #endif
2909
2910 static VOID UnitTask(struct ExecBase *sys_base)
2911 {
2912    struct Task *task;
2913    struct IORequest *request;
2914    struct DevUnit *unit;
2915    struct DevBase *base;
2916    struct MsgPort *general_port;
2917    ULONG signals = 0, wait_signals, card_removed_signal,
2918       card_inserted_signal, general_port_signal;
2919
2920    /* Get parameters */
2921
2922    task = AbsExecBase->ThisTask;
2923    unit = task->tc_UserData;
2924    base = unit->device;
2925
2926    /* Activate general request port */
2927
2928    general_port = unit->request_ports[GENERAL_QUEUE];
2929    general_port->mp_SigTask = task;
2930    general_port->mp_SigBit = AllocSignal(-1);
2931    general_port_signal = 1 << general_port->mp_SigBit;
2932    general_port->mp_Flags = PA_SIGNAL;
2933
2934    /* Allocate signals for notification of card removal and insertion */
2935
2936    card_removed_signal = unit->card_removed_signal = 1 << AllocSignal(-1);
2937    card_inserted_signal = unit->card_inserted_signal = 1 << AllocSignal(-1);
2938    wait_signals = (1 << general_port->mp_SigBit) | card_removed_signal
2939       | card_inserted_signal | SIGBREAKF_CTRL_C;
2940
2941    /* Tell ourselves to check port for old messages */
2942
2943    Signal(task, general_port_signal);
2944
2945    /* Infinite loop to service requests and signals */
2946
2947    while((signals & SIGBREAKF_CTRL_C) == 0)
2948    {
2949       signals = Wait(wait_signals);
2950
2951       if((signals & card_inserted_signal) != 0)
2952       {
2953          if(unit->insertion_function(unit->card, base))
2954          {
2955             unit->flags |= UNITF_HAVEADAPTER;
2956             if((unit->flags & UNITF_CONFIGURED) != 0)
2957                ConfigureAdapter(unit, base);
2958             if((unit->flags & UNITF_WASONLINE) != 0)
2959             {
2960                GoOnline(unit, base);
2961                unit->flags &= ~UNITF_WASONLINE;
2962             }
2963          }
2964       }
2965
2966       if((signals & card_removed_signal) != 0)
2967       {
2968          unit->removal_function(unit->card, base);
2969          if((unit->flags & UNITF_WASONLINE) != 0)
2970             GoOffline(unit, base);
2971       }
2972
2973       if((signals & general_port_signal) != 0)
2974       {
2975          while((request = (APTR)GetMsg(general_port)) != NULL)
2976          {
2977             /* Service the request as soon as the unit is free */
2978
2979             ObtainSemaphore(&unit->access_lock);
2980             ServiceRequest((APTR)request, base);
2981          }
2982       }
2983    }
2984
2985    FreeMem(task->tc_SPLower, STACK_SIZE);
2986 }
2987
2988
2989