workbench/devs/networks/e1000/e1000_82542.c

   1 /*******************************************************************************
   2
   3   Intel PRO/1000 Linux driver
   4   Copyright(c) 1999 - 2008 Intel Corporation.
   5
   6   This program is free software; you can redistribute it and/or modify it
   7   under the terms and conditions of the GNU General Public License,
   8   version 2, as published by the Free Software Foundation.
   9
  10   This program is distributed in the hope it will be useful, but WITHOUT
  11   ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
  12   FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License for
  13   more details.
  14
  15   You should have received a copy of the GNU General Public License along with
  16   this program; if not, write to the Free Software Foundation, Inc.,
  17   51 Franklin St - Fifth Floor, Boston, MA 02110-1301 USA.
  18
  19   The full GNU General Public License is included in this distribution in
  20   the file called "COPYING".
  21
  22   Contact Information:
  23   Linux NICS <linux.nics@intel.com>
  24   e1000-devel Mailing List <e1000-devel@lists.sourceforge.net>
  25   Intel Corporation, 5200 N.E. Elam Young Parkway, Hillsboro, OR 97124-6497
  26
  27 *******************************************************************************/
  28
  29 /*
  30  * 82542 Gigabit Ethernet Controller
  31  */
  32
  33 #include "e1000_api.h"
  34
  35 static s32  e1000_init_phy_params_82542(struct e1000_hw *hw);
  36 static s32  e1000_init_nvm_params_82542(struct e1000_hw *hw);
  37 static s32  e1000_init_mac_params_82542(struct e1000_hw *hw);
  38 static s32  e1000_get_bus_info_82542(struct e1000_hw *hw);
  39 static s32  e1000_reset_hw_82542(struct e1000_hw *hw);
  40 static s32  e1000_init_hw_82542(struct e1000_hw *hw);
  41 static s32  e1000_setup_link_82542(struct e1000_hw *hw);
  42 static s32  e1000_led_on_82542(struct e1000_hw *hw);
  43 static s32  e1000_led_off_82542(struct e1000_hw *hw);
  44 static void e1000_rar_set_82542(struct e1000_hw *hw, u8 *addr, u32 index);
  45 static void e1000_clear_hw_cntrs_82542(struct e1000_hw *hw);
  46
  47 /**
  48  *  e1000_init_phy_params_82542 - Init PHY func ptrs.
  49  *  @hw: pointer to the HW structure
  50  **/
  51 static s32 e1000_init_phy_params_82542(struct e1000_hw *hw)
  52 {
  53         struct e1000_phy_info *phy = &hw->phy;
  54         s32 ret_val = E1000_SUCCESS;
  55
  56         DEBUGFUNC("e1000_init_phy_params_82542");
  57
  58         phy->type               = e1000_phy_none;
  59
  60         return ret_val;
  61 }
  62
  63 /**
  64  *  e1000_init_nvm_params_82542 - Init NVM func ptrs.
  65  *  @hw: pointer to the HW structure
  66  **/
  67 static s32 e1000_init_nvm_params_82542(struct e1000_hw *hw)
  68 {
  69         struct e1000_nvm_info *nvm = &hw->nvm;
  70
  71         DEBUGFUNC("e1000_init_nvm_params_82542");
  72
  73         nvm->address_bits       =  6;
  74         nvm->delay_usec         = 50;
  75         nvm->opcode_bits        =  3;
  76         nvm->type               = e1000_nvm_eeprom_microwire;
  77         nvm->word_size          = 64;
  78
  79         /* Function Pointers */
  80         nvm->ops.read           = e1000_read_nvm_microwire;
  81         nvm->ops.release        = e1000_stop_nvm;
  82         nvm->ops.write          = e1000_write_nvm_microwire;
  83         nvm->ops.update         = e1000_update_nvm_checksum_generic;
  84         nvm->ops.validate       = e1000_validate_nvm_checksum_generic;
  85
  86         return E1000_SUCCESS;
  87 }
  88
  89 /**
  90  *  e1000_init_mac_params_82542 - Init MAC func ptrs.
  91  *  @hw: pointer to the HW structure
  92  **/
  93 static s32 e1000_init_mac_params_82542(struct e1000_hw *hw)
  94 {
  95         struct e1000_mac_info *mac = &hw->mac;
  96
  97         DEBUGFUNC("e1000_init_mac_params_82542");
  98
  99         /* Set media type */
 100         hw->phy.media_type = e1000_media_type_fiber;
 101
 102         /* Set mta register count */
 103         mac->mta_reg_count = 128;
 104         /* Set rar entry count */
 105         mac->rar_entry_count = E1000_RAR_ENTRIES;
 106
 107         /* Function pointers */
 108
 109         /* bus type/speed/width */
 110         mac->ops.get_bus_info = e1000_get_bus_info_82542;
 111         /* function id */
 112         mac->ops.set_lan_id = e1000_set_lan_id_multi_port_pci;
 113         /* reset */
 114         mac->ops.reset_hw = e1000_reset_hw_82542;
 115         /* hw initialization */
 116         mac->ops.init_hw = e1000_init_hw_82542;
 117         /* link setup */
 118         mac->ops.setup_link = e1000_setup_link_82542;
 119         /* phy/fiber/serdes setup */
 120         mac->ops.setup_physical_interface = e1000_setup_fiber_serdes_link_generic;
 121         /* check for link */
 122         mac->ops.check_for_link = e1000_check_for_fiber_link_generic;
 123         /* multicast address update */
 124         mac->ops.update_mc_addr_list = e1000_update_mc_addr_list_generic;
 125         /* writing VFTA */
 126         mac->ops.write_vfta = e1000_write_vfta_generic;
 127         /* clearing VFTA */
 128         mac->ops.clear_vfta = e1000_clear_vfta_generic;
 129         /* setting MTA */
 130         mac->ops.mta_set = e1000_mta_set_generic;
 131         /* set RAR */
 132         mac->ops.rar_set = e1000_rar_set_82542;
 133         /* turn on/off LED */
 134         mac->ops.led_on = e1000_led_on_82542;
 135         mac->ops.led_off = e1000_led_off_82542;
 136         /* clear hardware counters */
 137         mac->ops.clear_hw_cntrs = e1000_clear_hw_cntrs_82542;
 138         /* link info */
 139         mac->ops.get_link_up_info = e1000_get_speed_and_duplex_fiber_serdes_generic;
 140
 141         return E1000_SUCCESS;
 142 }
 143
 144 /**
 145  *  e1000_init_function_pointers_82542 - Init func ptrs.
 146  *  @hw: pointer to the HW structure
 147  *
 148  *  Called to initialize all function pointers and parameters.
 149  **/
 150 void e1000_init_function_pointers_82542(struct e1000_hw *hw)
 151 {
 152         DEBUGFUNC("e1000_init_function_pointers_82542");
 153
 154         hw->mac.ops.init_params = e1000_init_mac_params_82542;
 155         hw->nvm.ops.init_params = e1000_init_nvm_params_82542;
 156         hw->phy.ops.init_params = e1000_init_phy_params_82542;
 157 }
 158
 159 /**
 160  *  e1000_get_bus_info_82542 - Obtain bus information for adapter
 161  *  @hw: pointer to the HW structure
 162  *
 163  *  This will obtain information about the HW bus for which the
 164  *  adapter is attached and stores it in the hw structure.
 165  **/
 166 static s32 e1000_get_bus_info_82542(struct e1000_hw *hw)
 167 {
 168         DEBUGFUNC("e1000_get_bus_info_82542");
 169
 170         hw->bus.type = e1000_bus_type_pci;
 171         hw->bus.speed = e1000_bus_speed_unknown;
 172         hw->bus.width = e1000_bus_width_unknown;
 173
 174         return E1000_SUCCESS;
 175 }
 176
 177 /**
 178  *  e1000_reset_hw_82542 - Reset hardware
 179  *  @hw: pointer to the HW structure
 180  *
 181  *  This resets the hardware into a known state.
 182  **/
 183 static s32 e1000_reset_hw_82542(struct e1000_hw *hw)
 184 {
 185         struct e1000_bus_info *bus = &hw->bus;
 186         s32 ret_val = E1000_SUCCESS;
 187         u32 ctrl;
 188
 189         DEBUGFUNC("e1000_reset_hw_82542");
 190
 191         if (hw->revision_id == E1000_REVISION_2) {
 192                 DEBUGOUT("Disabling MWI on 82542 rev 2\n");
 193                 e1000_pci_clear_mwi(hw);
 194         }
 195
 196         DEBUGOUT("Masking off all interrupts\n");
 197         E1000_WRITE_REG(hw, E1000_IMC, 0xffffffff);
 198
 199         E1000_WRITE_REG(hw, E1000_RCTL, 0);
 200         E1000_WRITE_REG(hw, E1000_TCTL, E1000_TCTL_PSP);
 201         E1000_WRITE_FLUSH(hw);
 202
 203         /*
 204          * Delay to allow any outstanding PCI transactions to complete before
 205          * resetting the device
 206          */
 207         msec_delay(10);
 208
 209         ctrl = E1000_READ_REG(hw, E1000_CTRL);
 210
 211         DEBUGOUT("Issuing a global reset to 82542/82543 MAC\n");
 212         E1000_WRITE_REG(hw, E1000_CTRL, ctrl | E1000_CTRL_RST);
 213
 214         hw->nvm.ops.reload(hw);
 215         msec_delay(2);
 216
 217         E1000_WRITE_REG(hw, E1000_IMC, 0xffffffff);
 218         E1000_READ_REG(hw, E1000_ICR);
 219
 220         if (hw->revision_id == E1000_REVISION_2) {
 221                 if (bus->pci_cmd_word & CMD_MEM_WRT_INVALIDATE)
 222                         e1000_pci_set_mwi(hw);
 223         }
 224
 225         return ret_val;
 226 }
 227
 228 /**
 229  *  e1000_init_hw_82542 - Initialize hardware
 230  *  @hw: pointer to the HW structure
 231  *
 232  *  This inits the hardware readying it for operation.
 233  **/
 234 static s32 e1000_init_hw_82542(struct e1000_hw *hw)
 235 {
 236         struct e1000_mac_info *mac = &hw->mac;
 237         struct e1000_dev_spec_82542 *dev_spec = &hw->dev_spec._82542;
 238         s32 ret_val = E1000_SUCCESS;
 239         u32 ctrl;
 240         u16 i;
 241
 242         DEBUGFUNC("e1000_init_hw_82542");
 243
 244         /* Disabling VLAN filtering */
 245         E1000_WRITE_REG(hw, E1000_VET, 0);
 246         mac->ops.clear_vfta(hw);
 247
 248         /* For 82542 (rev 2.0), disable MWI and put the receiver into reset */
 249         if (hw->revision_id == E1000_REVISION_2) {
 250                 DEBUGOUT("Disabling MWI on 82542 rev 2.0\n");
 251                 e1000_pci_clear_mwi(hw);
 252                 E1000_WRITE_REG(hw, E1000_RCTL, E1000_RCTL_RST);
 253                 E1000_WRITE_FLUSH(hw);
 254                 msec_delay(5);
 255         }
 256
 257         /* Setup the receive address. */
 258         e1000_init_rx_addrs_generic(hw, mac->rar_entry_count);
 259
 260         /* For 82542 (rev 2.0), take the receiver out of reset and enable MWI */
 261         if (hw->revision_id == E1000_REVISION_2) {
 262                 E1000_WRITE_REG(hw, E1000_RCTL, 0);
 263                 E1000_WRITE_FLUSH(hw);
 264                 msec_delay(1);
 265                 if (hw->bus.pci_cmd_word & CMD_MEM_WRT_INVALIDATE)
 266                         e1000_pci_set_mwi(hw);
 267         }
 268
 269         /* Zero out the Multicast HASH table */
 270         DEBUGOUT("Zeroing the MTA\n");
 271         for (i = 0; i < mac->mta_reg_count; i++)
 272                 E1000_WRITE_REG_ARRAY(hw, E1000_MTA, i, 0);
 273
 274         /*
 275          * Set the PCI priority bit correctly in the CTRL register.  This
 276          * determines if the adapter gives priority to receives, or if it
 277          * gives equal priority to transmits and receives.
 278          */
 279         if (dev_spec->dma_fairness) {
 280                 ctrl = E1000_READ_REG(hw, E1000_CTRL);
 281                 E1000_WRITE_REG(hw, E1000_CTRL, ctrl | E1000_CTRL_PRIOR);
 282         }
 283
 284         /* Setup link and flow control */
 285         ret_val = e1000_setup_link_82542(hw);
 286
 287         /*
 288          * Clear all of the statistics registers (clear on read).  It is
 289          * important that we do this after we have tried to establish link
 290          * because the symbol error count will increment wildly if there
 291          * is no link.
 292          */
 293         e1000_clear_hw_cntrs_82542(hw);
 294
 295         return ret_val;
 296 }
 297
 298 /**
 299  *  e1000_setup_link_82542 - Setup flow control and link settings
 300  *  @hw: pointer to the HW structure
 301  *
 302  *  Determines which flow control settings to use, then configures flow
 303  *  control.  Calls the appropriate media-specific link configuration
 304  *  function.  Assuming the adapter has a valid link partner, a valid link
 305  *  should be established.  Assumes the hardware has previously been reset
 306  *  and the transmitter and receiver are not enabled.
 307  **/
 308 static s32 e1000_setup_link_82542(struct e1000_hw *hw)
 309 {
 310         struct e1000_mac_info *mac = &hw->mac;
 311         s32 ret_val = E1000_SUCCESS;
 312
 313         DEBUGFUNC("e1000_setup_link_82542");
 314
 315         ret_val = e1000_set_default_fc_generic(hw);
 316         if (ret_val)
 317                 goto out;
 318
 319         hw->fc.requested_mode &= ~e1000_fc_tx_pause;
 320
 321         if (mac->report_tx_early == 1)
 322                 hw->fc.requested_mode &= ~e1000_fc_rx_pause;
 323
 324         /*
 325          * Save off the requested flow control mode for use later.  Depending
 326          * on the link partner's capabilities, we may or may not use this mode.
 327          */
 328         hw->fc.current_mode = hw->fc.requested_mode;
 329
 330         DEBUGOUT1("After fix-ups FlowControl is now = %x\n",
 331                                                      hw->fc.current_mode);
 332
 333         /* Call the necessary subroutine to configure the link. */
 334         ret_val = mac->ops.setup_physical_interface(hw);
 335         if (ret_val)
 336                 goto out;
 337
 338         /*
 339          * Initialize the flow control address, type, and PAUSE timer
 340          * registers to their default values.  This is done even if flow
 341          * control is disabled, because it does not hurt anything to
 342          * initialize these registers.
 343          */
 344         DEBUGOUT("Initializing Flow Control address, type and timer regs\n");
 345
 346         E1000_WRITE_REG(hw, E1000_FCAL, FLOW_CONTROL_ADDRESS_LOW);
 347         E1000_WRITE_REG(hw, E1000_FCAH, FLOW_CONTROL_ADDRESS_HIGH);
 348         E1000_WRITE_REG(hw, E1000_FCT, FLOW_CONTROL_TYPE);
 349
 350         E1000_WRITE_REG(hw, E1000_FCTTV, hw->fc.pause_time);
 351
 352         ret_val = e1000_set_fc_watermarks_generic(hw);
 353
 354 out:
 355         return ret_val;
 356 }
 357
 358 /**
 359  *  e1000_led_on_82542 - Turn on SW controllable LED
 360  *  @hw: pointer to the HW structure
 361  *
 362  *  Turns the SW defined LED on.
 363  **/
 364 static s32 e1000_led_on_82542(struct e1000_hw *hw)
 365 {
 366         u32 ctrl = E1000_READ_REG(hw, E1000_CTRL);
 367
 368         DEBUGFUNC("e1000_led_on_82542");
 369
 370         ctrl |= E1000_CTRL_SWDPIN0;
 371         ctrl |= E1000_CTRL_SWDPIO0;
 372         E1000_WRITE_REG(hw, E1000_CTRL, ctrl);
 373
 374         return E1000_SUCCESS;
 375 }
 376
 377 /**
 378  *  e1000_led_off_82542 - Turn off SW controllable LED
 379  *  @hw: pointer to the HW structure
 380  *
 381  *  Turns the SW defined LED off.
 382  **/
 383 static s32 e1000_led_off_82542(struct e1000_hw *hw)
 384 {
 385         u32 ctrl = E1000_READ_REG(hw, E1000_CTRL);
 386
 387         DEBUGFUNC("e1000_led_off_82542");
 388
 389         ctrl &= ~E1000_CTRL_SWDPIN0;
 390         ctrl |= E1000_CTRL_SWDPIO0;
 391         E1000_WRITE_REG(hw, E1000_CTRL, ctrl);
 392
 393         return E1000_SUCCESS;
 394 }
 395
 396 /**
 397  *  e1000_rar_set_82542 - Set receive address register
 398  *  @hw: pointer to the HW structure
 399  *  @addr: pointer to the receive address
 400  *  @index: receive address array register
 401  *
 402  *  Sets the receive address array register at index to the address passed
 403  *  in by addr.
 404  **/
 405 static void e1000_rar_set_82542(struct e1000_hw *hw, u8 *addr, u32 index)
 406 {
 407         u32 rar_low, rar_high;
 408
 409         DEBUGFUNC("e1000_rar_set_82542");
 410
 411         /*
 412          * HW expects these in little endian so we reverse the byte order
 413          * from network order (big endian) to little endian
 414          */
 415         rar_low = ((u32) addr[0] |
 416                    ((u32) addr[1] << 8) |
 417                    ((u32) addr[2] << 16) | ((u32) addr[3] << 24));
 418
 419         rar_high = ((u32) addr[4] | ((u32) addr[5] << 8));
 420
 421         /* If MAC address zero, no need to set the AV bit */
 422         if (rar_low || rar_high)
 423                 rar_high |= E1000_RAH_AV;
 424
 425         E1000_WRITE_REG_ARRAY(hw, E1000_RA, (index << 1), rar_low);
 426         E1000_WRITE_REG_ARRAY(hw, E1000_RA, ((index << 1) + 1), rar_high);
 427 }
 428
 429 /**
 430  *  e1000_translate_register_82542 - Translate the proper register offset
 431  *  @reg: e1000 register to be read
 432  *
 433  *  Registers in 82542 are located in different offsets than other adapters
 434  *  even though they function in the same manner.  This function takes in
 435  *  the name of the register to read and returns the correct offset for
 436  *  82542 silicon.
 437  **/
 438 u32 e1000_translate_register_82542(u32 reg)
 439 {
 440         /*
 441          * Some of the 82542 registers are located at different
 442          * offsets than they are in newer adapters.
 443          * Despite the difference in location, the registers
 444          * function in the same manner.
 445          */
 446         switch (reg) {
 447         case E1000_RA:
 448                 reg = 0x00040;
 449                 break;
 450         case E1000_RDTR:
 451                 reg = 0x00108;
 452                 break;
 453         case E1000_RDBAL(0):
 454                 reg = 0x00110;
 455                 break;
 456         case E1000_RDBAH(0):
 457                 reg = 0x00114;
 458                 break;
 459         case E1000_RDLEN(0):
 460                 reg = 0x00118;
 461                 break;
 462         case E1000_RDH(0):
 463                 reg = 0x00120;
 464                 break;
 465         case E1000_RDT(0):
 466                 reg = 0x00128;
 467                 break;
 468         case E1000_RDBAL(1):
 469                 reg = 0x00138;
 470                 break;
 471         case E1000_RDBAH(1):
 472                 reg = 0x0013C;
 473                 break;
 474         case E1000_RDLEN(1):
 475                 reg = 0x00140;
 476                 break;
 477         case E1000_RDH(1):
 478                 reg = 0x00148;
 479                 break;
 480         case E1000_RDT(1):
 481                 reg = 0x00150;
 482                 break;
 483         case E1000_FCRTH:
 484                 reg = 0x00160;
 485                 break;
 486         case E1000_FCRTL:
 487                 reg = 0x00168;
 488                 break;
 489         case E1000_MTA:
 490                 reg = 0x00200;
 491                 break;
 492         case E1000_TDBAL(0):
 493                 reg = 0x00420;
 494                 break;
 495         case E1000_TDBAH(0):
 496                 reg = 0x00424;
 497                 break;
 498         case E1000_TDLEN(0):
 499                 reg = 0x00428;
 500                 break;
 501         case E1000_TDH(0):
 502                 reg = 0x00430;
 503                 break;
 504         case E1000_TDT(0):
 505                 reg = 0x00438;
 506                 break;
 507         case E1000_TIDV:
 508                 reg = 0x00440;
 509                 break;
 510         case E1000_VFTA:
 511                 reg = 0x00600;
 512                 break;
 513         case E1000_TDFH:
 514                 reg = 0x08010;
 515                 break;
 516         case E1000_TDFT:
 517                 reg = 0x08018;
 518                 break;
 519         default:
 520                 break;
 521         }
 522
 523         return reg;
 524 }
 525
 526 /**
 527  *  e1000_clear_hw_cntrs_82542 - Clear device specific hardware counters
 528  *  @hw: pointer to the HW structure
 529  *
 530  *  Clears the hardware counters by reading the counter registers.
 531  **/
 532 static void e1000_clear_hw_cntrs_82542(struct e1000_hw *hw)
 533 {
 534         DEBUGFUNC("e1000_clear_hw_cntrs_82542");
 535
 536         e1000_clear_hw_cntrs_base_generic(hw);
 537
 538         E1000_READ_REG(hw, E1000_PRC64);
 539         E1000_READ_REG(hw, E1000_PRC127);
 540         E1000_READ_REG(hw, E1000_PRC255);
 541         E1000_READ_REG(hw, E1000_PRC511);
 542         E1000_READ_REG(hw, E1000_PRC1023);
 543         E1000_READ_REG(hw, E1000_PRC1522);
 544         E1000_READ_REG(hw, E1000_PTC64);
 545         E1000_READ_REG(hw, E1000_PTC127);
 546         E1000_READ_REG(hw, E1000_PTC255);
 547         E1000_READ_REG(hw, E1000_PTC511);
 548         E1000_READ_REG(hw, E1000_PTC1023);
 549         E1000_READ_REG(hw, E1000_PTC1522);
 550 }