1 /*******************************************************************************
3 Intel PRO/1000 Linux driver
4 Copyright(c) 1999 - 2008 Intel Corporation.
6 This program is free software; you can redistribute it and/or modify it
7 under the terms and conditions of the GNU General Public License,
8 version 2, as published by the Free Software Foundation.
10 This program is distributed in the hope it will be useful, but WITHOUT
11 ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
12 FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
15 You should have received a copy of the GNU General Public License along with
16 this program; if not, write to the Free Software Foundation, Inc.,
17 51 Franklin St - Fifth Floor, Boston, MA 02110-1301 USA.
19 The full GNU General Public License is included in this distribution in
20 the file called "COPYING".
23 Linux NICS <linux.nics@intel.com>
24 e1000-devel Mailing List <e1000-devel@lists.sourceforge.net>
25 Intel Corporation, 5200 N.E. Elam Young Parkway, Hillsboro, OR 97124-6497
27 *******************************************************************************/
30 * 82543GC Gigabit Ethernet Controller (Fiber)
31 * 82543GC Gigabit Ethernet Controller (Copper)
32 * 82544EI Gigabit Ethernet Controller (Copper)
33 * 82544EI Gigabit Ethernet Controller (Fiber)
34 * 82544GC Gigabit Ethernet Controller (Copper)
35 * 82544GC Gigabit Ethernet Controller (LOM)
38 #include "e1000_api.h"
40 static s32
e1000_init_phy_params_82543(struct e1000_hw
*hw
);
41 static s32
e1000_init_nvm_params_82543(struct e1000_hw
*hw
);
42 static s32
e1000_init_mac_params_82543(struct e1000_hw
*hw
);
43 static s32
e1000_read_phy_reg_82543(struct e1000_hw
*hw
, u32 offset
,
45 static s32
e1000_write_phy_reg_82543(struct e1000_hw
*hw
, u32 offset
,
47 static s32
e1000_phy_force_speed_duplex_82543(struct e1000_hw
*hw
);
48 static s32
e1000_phy_hw_reset_82543(struct e1000_hw
*hw
);
49 static s32
e1000_reset_hw_82543(struct e1000_hw
*hw
);
50 static s32
e1000_init_hw_82543(struct e1000_hw
*hw
);
51 static s32
e1000_setup_link_82543(struct e1000_hw
*hw
);
52 static s32
e1000_setup_copper_link_82543(struct e1000_hw
*hw
);
53 static s32
e1000_setup_fiber_link_82543(struct e1000_hw
*hw
);
54 static s32
e1000_check_for_copper_link_82543(struct e1000_hw
*hw
);
55 static s32
e1000_check_for_fiber_link_82543(struct e1000_hw
*hw
);
56 static s32
e1000_led_on_82543(struct e1000_hw
*hw
);
57 static s32
e1000_led_off_82543(struct e1000_hw
*hw
);
58 static void e1000_write_vfta_82543(struct e1000_hw
*hw
, u32 offset
,
60 static void e1000_mta_set_82543(struct e1000_hw
*hw
, u32 hash_value
);
61 static void e1000_clear_hw_cntrs_82543(struct e1000_hw
*hw
);
62 static s32
e1000_config_mac_to_phy_82543(struct e1000_hw
*hw
);
63 static bool e1000_init_phy_disabled_82543(struct e1000_hw
*hw
);
64 static void e1000_lower_mdi_clk_82543(struct e1000_hw
*hw
, u32
*ctrl
);
65 static s32
e1000_polarity_reversal_workaround_82543(struct e1000_hw
*hw
);
66 static void e1000_raise_mdi_clk_82543(struct e1000_hw
*hw
, u32
*ctrl
);
67 static u16
e1000_shift_in_mdi_bits_82543(struct e1000_hw
*hw
);
68 static void e1000_shift_out_mdi_bits_82543(struct e1000_hw
*hw
, u32 data
,
70 static bool e1000_tbi_compatibility_enabled_82543(struct e1000_hw
*hw
);
71 static void e1000_set_tbi_sbp_82543(struct e1000_hw
*hw
, bool state
);
74 * e1000_init_phy_params_82543 - Init PHY func ptrs.
75 * @hw: pointer to the HW structure
77 static s32
e1000_init_phy_params_82543(struct e1000_hw
*hw
)
79 struct e1000_phy_info
*phy
= &hw
->phy
;
80 s32 ret_val
= E1000_SUCCESS
;
82 DEBUGFUNC("e1000_init_phy_params_82543");
84 if (hw
->phy
.media_type
!= e1000_media_type_copper
) {
85 phy
->type
= e1000_phy_none
;
88 phy
->ops
.power_up
= e1000_power_up_phy_copper
;
89 phy
->ops
.power_down
= e1000_power_down_phy_copper
;
93 phy
->autoneg_mask
= AUTONEG_ADVERTISE_SPEED_DEFAULT
;
94 phy
->reset_delay_us
= 10000;
95 phy
->type
= e1000_phy_m88
;
97 /* Function Pointers */
98 phy
->ops
.check_polarity
= e1000_check_polarity_m88
;
99 phy
->ops
.commit
= e1000_phy_sw_reset_generic
;
100 phy
->ops
.force_speed_duplex
= e1000_phy_force_speed_duplex_82543
;
101 phy
->ops
.get_cable_length
= e1000_get_cable_length_m88
;
102 phy
->ops
.get_cfg_done
= e1000_get_cfg_done_generic
;
103 phy
->ops
.read_reg
= (hw
->mac
.type
== e1000_82543
)
104 ? e1000_read_phy_reg_82543
105 : e1000_read_phy_reg_m88
;
106 phy
->ops
.reset
= (hw
->mac
.type
== e1000_82543
)
107 ? e1000_phy_hw_reset_82543
108 : e1000_phy_hw_reset_generic
;
109 phy
->ops
.write_reg
= (hw
->mac
.type
== e1000_82543
)
110 ? e1000_write_phy_reg_82543
111 : e1000_write_phy_reg_m88
;
112 phy
->ops
.get_info
= e1000_get_phy_info_m88
;
115 * The external PHY of the 82543 can be in a funky state.
116 * Resetting helps us read the PHY registers for acquiring
119 if (!e1000_init_phy_disabled_82543(hw
)) {
120 ret_val
= phy
->ops
.reset(hw
);
122 DEBUGOUT("Resetting PHY during init failed.\n");
128 ret_val
= e1000_get_phy_id(hw
);
133 switch (hw
->mac
.type
) {
135 if (phy
->id
!= M88E1000_E_PHY_ID
) {
136 ret_val
= -E1000_ERR_PHY
;
141 if (phy
->id
!= M88E1000_I_PHY_ID
) {
142 ret_val
= -E1000_ERR_PHY
;
147 ret_val
= -E1000_ERR_PHY
;
157 * e1000_init_nvm_params_82543 - Init NVM func ptrs.
158 * @hw: pointer to the HW structure
160 static s32
e1000_init_nvm_params_82543(struct e1000_hw
*hw
)
162 struct e1000_nvm_info
*nvm
= &hw
->nvm
;
164 DEBUGFUNC("e1000_init_nvm_params_82543");
166 nvm
->type
= e1000_nvm_eeprom_microwire
;
168 nvm
->delay_usec
= 50;
169 nvm
->address_bits
= 6;
170 nvm
->opcode_bits
= 3;
172 /* Function Pointers */
173 nvm
->ops
.read
= e1000_read_nvm_microwire
;
174 nvm
->ops
.update
= e1000_update_nvm_checksum_generic
;
175 nvm
->ops
.valid_led_default
= e1000_valid_led_default_generic
;
176 nvm
->ops
.validate
= e1000_validate_nvm_checksum_generic
;
177 nvm
->ops
.write
= e1000_write_nvm_microwire
;
179 return E1000_SUCCESS
;
183 * e1000_init_mac_params_82543 - Init MAC func ptrs.
184 * @hw: pointer to the HW structure
186 static s32
e1000_init_mac_params_82543(struct e1000_hw
*hw
)
188 struct e1000_mac_info
*mac
= &hw
->mac
;
190 DEBUGFUNC("e1000_init_mac_params_82543");
193 switch (hw
->device_id
) {
194 case E1000_DEV_ID_82543GC_FIBER
:
195 case E1000_DEV_ID_82544EI_FIBER
:
196 hw
->phy
.media_type
= e1000_media_type_fiber
;
199 hw
->phy
.media_type
= e1000_media_type_copper
;
203 /* Set mta register count */
204 mac
->mta_reg_count
= 128;
205 /* Set rar entry count */
206 mac
->rar_entry_count
= E1000_RAR_ENTRIES
;
208 /* Function pointers */
210 /* bus type/speed/width */
211 mac
->ops
.get_bus_info
= e1000_get_bus_info_pci_generic
;
213 mac
->ops
.set_lan_id
= e1000_set_lan_id_multi_port_pci
;
215 mac
->ops
.reset_hw
= e1000_reset_hw_82543
;
216 /* hw initialization */
217 mac
->ops
.init_hw
= e1000_init_hw_82543
;
219 mac
->ops
.setup_link
= e1000_setup_link_82543
;
220 /* physical interface setup */
221 mac
->ops
.setup_physical_interface
=
222 (hw
->phy
.media_type
== e1000_media_type_copper
)
223 ? e1000_setup_copper_link_82543
224 : e1000_setup_fiber_link_82543
;
226 mac
->ops
.check_for_link
=
227 (hw
->phy
.media_type
== e1000_media_type_copper
)
228 ? e1000_check_for_copper_link_82543
229 : e1000_check_for_fiber_link_82543
;
231 mac
->ops
.get_link_up_info
=
232 (hw
->phy
.media_type
== e1000_media_type_copper
)
233 ? e1000_get_speed_and_duplex_copper_generic
234 : e1000_get_speed_and_duplex_fiber_serdes_generic
;
235 /* multicast address update */
236 mac
->ops
.update_mc_addr_list
= e1000_update_mc_addr_list_generic
;
238 mac
->ops
.write_vfta
= e1000_write_vfta_82543
;
240 mac
->ops
.clear_vfta
= e1000_clear_vfta_generic
;
242 mac
->ops
.mta_set
= e1000_mta_set_82543
;
243 /* turn on/off LED */
244 mac
->ops
.led_on
= e1000_led_on_82543
;
245 mac
->ops
.led_off
= e1000_led_off_82543
;
246 /* clear hardware counters */
247 mac
->ops
.clear_hw_cntrs
= e1000_clear_hw_cntrs_82543
;
249 /* Set tbi compatibility */
250 if ((hw
->mac
.type
!= e1000_82543
) ||
251 (hw
->phy
.media_type
== e1000_media_type_fiber
))
252 e1000_set_tbi_compatibility_82543(hw
, false);
254 return E1000_SUCCESS
;
258 * e1000_init_function_pointers_82543 - Init func ptrs.
259 * @hw: pointer to the HW structure
261 * Called to initialize all function pointers and parameters.
263 void e1000_init_function_pointers_82543(struct e1000_hw
*hw
)
265 DEBUGFUNC("e1000_init_function_pointers_82543");
267 hw
->mac
.ops
.init_params
= e1000_init_mac_params_82543
;
268 hw
->nvm
.ops
.init_params
= e1000_init_nvm_params_82543
;
269 hw
->phy
.ops
.init_params
= e1000_init_phy_params_82543
;
273 * e1000_tbi_compatibility_enabled_82543 - Returns TBI compat status
274 * @hw: pointer to the HW structure
276 * Returns the current status of 10-bit Interface (TBI) compatibility
277 * (enabled/disabled).
279 static bool e1000_tbi_compatibility_enabled_82543(struct e1000_hw
*hw
)
281 struct e1000_dev_spec_82543
*dev_spec
= &hw
->dev_spec
._82543
;
284 DEBUGFUNC("e1000_tbi_compatibility_enabled_82543");
286 if (hw
->mac
.type
!= e1000_82543
) {
287 DEBUGOUT("TBI compatibility workaround for 82543 only.\n");
291 state
= (dev_spec
->tbi_compatibility
& TBI_COMPAT_ENABLED
)
299 * e1000_set_tbi_compatibility_82543 - Set TBI compatibility
300 * @hw: pointer to the HW structure
301 * @state: enable/disable TBI compatibility
303 * Enables or disabled 10-bit Interface (TBI) compatibility.
305 void e1000_set_tbi_compatibility_82543(struct e1000_hw
*hw
, bool state
)
307 struct e1000_dev_spec_82543
*dev_spec
= &hw
->dev_spec
._82543
;
309 DEBUGFUNC("e1000_set_tbi_compatibility_82543");
311 if (hw
->mac
.type
!= e1000_82543
) {
312 DEBUGOUT("TBI compatibility workaround for 82543 only.\n");
317 dev_spec
->tbi_compatibility
|= TBI_COMPAT_ENABLED
;
319 dev_spec
->tbi_compatibility
&= ~TBI_COMPAT_ENABLED
;
326 * e1000_tbi_sbp_enabled_82543 - Returns TBI SBP status
327 * @hw: pointer to the HW structure
329 * Returns the current status of 10-bit Interface (TBI) store bad packet (SBP)
330 * (enabled/disabled).
332 bool e1000_tbi_sbp_enabled_82543(struct e1000_hw
*hw
)
334 struct e1000_dev_spec_82543
*dev_spec
= &hw
->dev_spec
._82543
;
337 DEBUGFUNC("e1000_tbi_sbp_enabled_82543");
339 if (hw
->mac
.type
!= e1000_82543
) {
340 DEBUGOUT("TBI compatibility workaround for 82543 only.\n");
344 state
= (dev_spec
->tbi_compatibility
& TBI_SBP_ENABLED
)
352 * e1000_set_tbi_sbp_82543 - Set TBI SBP
353 * @hw: pointer to the HW structure
354 * @state: enable/disable TBI store bad packet
356 * Enables or disabled 10-bit Interface (TBI) store bad packet (SBP).
358 static void e1000_set_tbi_sbp_82543(struct e1000_hw
*hw
, bool state
)
360 struct e1000_dev_spec_82543
*dev_spec
= &hw
->dev_spec
._82543
;
362 DEBUGFUNC("e1000_set_tbi_sbp_82543");
364 if (state
&& e1000_tbi_compatibility_enabled_82543(hw
))
365 dev_spec
->tbi_compatibility
|= TBI_SBP_ENABLED
;
367 dev_spec
->tbi_compatibility
&= ~TBI_SBP_ENABLED
;
373 * e1000_init_phy_disabled_82543 - Returns init PHY status
374 * @hw: pointer to the HW structure
376 * Returns the current status of whether PHY initialization is disabled.
377 * True if PHY initialization is disabled else false.
379 static bool e1000_init_phy_disabled_82543(struct e1000_hw
*hw
)
381 struct e1000_dev_spec_82543
*dev_spec
= &hw
->dev_spec
._82543
;
384 DEBUGFUNC("e1000_init_phy_disabled_82543");
386 if (hw
->mac
.type
!= e1000_82543
) {
391 ret_val
= dev_spec
->init_phy_disabled
;
398 * e1000_tbi_adjust_stats_82543 - Adjust stats when TBI enabled
399 * @hw: pointer to the HW structure
400 * @stats: Struct containing statistic register values
401 * @frame_len: The length of the frame in question
402 * @mac_addr: The Ethernet destination address of the frame in question
403 * @max_frame_size: The maximum frame size
405 * Adjusts the statistic counters when a frame is accepted by TBI_ACCEPT
407 void e1000_tbi_adjust_stats_82543(struct e1000_hw
*hw
,
408 struct e1000_hw_stats
*stats
, u32 frame_len
,
409 u8
*mac_addr
, u32 max_frame_size
)
411 if (!(e1000_tbi_sbp_enabled_82543(hw
)))
414 /* First adjust the frame length. */
417 * We need to adjust the statistics counters, since the hardware
418 * counters overcount this packet as a CRC error and undercount
419 * the packet as a good packet
421 /* This packet should not be counted as a CRC error. */
423 /* This packet does count as a Good Packet Received. */
426 /* Adjust the Good Octets received counters */
427 stats
->gorc
+= frame_len
;
430 * Is this a broadcast or multicast? Check broadcast first,
431 * since the test for a multicast frame will test positive on
434 if ((mac_addr
[0] == 0xff) && (mac_addr
[1] == 0xff))
435 /* Broadcast packet */
437 else if (*mac_addr
& 0x01)
438 /* Multicast packet */
442 * In this case, the hardware has overcounted the number of
445 if ((frame_len
== max_frame_size
) && (stats
->roc
> 0))
449 * Adjust the bin counters when the extra byte put the frame in the
450 * wrong bin. Remember that the frame_len was adjusted above.
452 if (frame_len
== 64) {
455 } else if (frame_len
== 127) {
458 } else if (frame_len
== 255) {
461 } else if (frame_len
== 511) {
464 } else if (frame_len
== 1023) {
467 } else if (frame_len
== 1522) {
476 * e1000_read_phy_reg_82543 - Read PHY register
477 * @hw: pointer to the HW structure
478 * @offset: register offset to be read
479 * @data: pointer to the read data
481 * Reads the PHY at offset and stores the information read to data.
483 static s32
e1000_read_phy_reg_82543(struct e1000_hw
*hw
, u32 offset
, u16
*data
)
486 s32 ret_val
= E1000_SUCCESS
;
488 DEBUGFUNC("e1000_read_phy_reg_82543");
490 if (offset
> MAX_PHY_REG_ADDRESS
) {
491 DEBUGOUT1("PHY Address %d is out of range\n", offset
);
492 ret_val
= -E1000_ERR_PARAM
;
497 * We must first send a preamble through the MDIO pin to signal the
498 * beginning of an MII instruction. This is done by sending 32
499 * consecutive "1" bits.
501 e1000_shift_out_mdi_bits_82543(hw
, PHY_PREAMBLE
, PHY_PREAMBLE_SIZE
);
504 * Now combine the next few fields that are required for a read
505 * operation. We use this method instead of calling the
506 * e1000_shift_out_mdi_bits routine five different times. The format
507 * of an MII read instruction consists of a shift out of 14 bits and
508 * is defined as follows:
509 * <Preamble><SOF><Op Code><Phy Addr><Offset>
510 * followed by a shift in of 18 bits. This first two bits shifted in
511 * are TurnAround bits used to avoid contention on the MDIO pin when a
512 * READ operation is performed. These two bits are thrown away
513 * followed by a shift in of 16 bits which contains the desired data.
515 mdic
= (offset
| (hw
->phy
.addr
<< 5) |
516 (PHY_OP_READ
<< 10) | (PHY_SOF
<< 12));
518 e1000_shift_out_mdi_bits_82543(hw
, mdic
, 14);
521 * Now that we've shifted out the read command to the MII, we need to
522 * "shift in" the 16-bit value (18 total bits) of the requested PHY
525 *data
= e1000_shift_in_mdi_bits_82543(hw
);
532 * e1000_write_phy_reg_82543 - Write PHY register
533 * @hw: pointer to the HW structure
534 * @offset: register offset to be written
535 * @data: pointer to the data to be written at offset
537 * Writes data to the PHY at offset.
539 static s32
e1000_write_phy_reg_82543(struct e1000_hw
*hw
, u32 offset
, u16 data
)
542 s32 ret_val
= E1000_SUCCESS
;
544 DEBUGFUNC("e1000_write_phy_reg_82543");
546 if (offset
> MAX_PHY_REG_ADDRESS
) {
547 DEBUGOUT1("PHY Address %d is out of range\n", offset
);
548 ret_val
= -E1000_ERR_PARAM
;
553 * We'll need to use the SW defined pins to shift the write command
554 * out to the PHY. We first send a preamble to the PHY to signal the
555 * beginning of the MII instruction. This is done by sending 32
556 * consecutive "1" bits.
558 e1000_shift_out_mdi_bits_82543(hw
, PHY_PREAMBLE
, PHY_PREAMBLE_SIZE
);
561 * Now combine the remaining required fields that will indicate a
562 * write operation. We use this method instead of calling the
563 * e1000_shift_out_mdi_bits routine for each field in the command. The
564 * format of a MII write instruction is as follows:
565 * <Preamble><SOF><Op Code><Phy Addr><Reg Addr><Turnaround><Data>.
567 mdic
= ((PHY_TURNAROUND
) | (offset
<< 2) | (hw
->phy
.addr
<< 7) |
568 (PHY_OP_WRITE
<< 12) | (PHY_SOF
<< 14));
572 e1000_shift_out_mdi_bits_82543(hw
, mdic
, 32);
579 * e1000_raise_mdi_clk_82543 - Raise Management Data Input clock
580 * @hw: pointer to the HW structure
581 * @ctrl: pointer to the control register
583 * Raise the management data input clock by setting the MDC bit in the control
586 static void e1000_raise_mdi_clk_82543(struct e1000_hw
*hw
, u32
*ctrl
)
589 * Raise the clock input to the Management Data Clock (by setting the
590 * MDC bit), and then delay a sufficient amount of time.
592 E1000_WRITE_REG(hw
, E1000_CTRL
, (*ctrl
| E1000_CTRL_MDC
));
593 E1000_WRITE_FLUSH(hw
);
598 * e1000_lower_mdi_clk_82543 - Lower Management Data Input clock
599 * @hw: pointer to the HW structure
600 * @ctrl: pointer to the control register
602 * Lower the management data input clock by clearing the MDC bit in the
605 static void e1000_lower_mdi_clk_82543(struct e1000_hw
*hw
, u32
*ctrl
)
608 * Lower the clock input to the Management Data Clock (by clearing the
609 * MDC bit), and then delay a sufficient amount of time.
611 E1000_WRITE_REG(hw
, E1000_CTRL
, (*ctrl
& ~E1000_CTRL_MDC
));
612 E1000_WRITE_FLUSH(hw
);
617 * e1000_shift_out_mdi_bits_82543 - Shift data bits our to the PHY
618 * @hw: pointer to the HW structure
619 * @data: data to send to the PHY
620 * @count: number of bits to shift out
622 * We need to shift 'count' bits out to the PHY. So, the value in the
623 * "data" parameter will be shifted out to the PHY one bit at a time.
624 * In order to do this, "data" must be broken down into bits.
626 static void e1000_shift_out_mdi_bits_82543(struct e1000_hw
*hw
, u32 data
,
632 * We need to shift "count" number of bits out to the PHY. So, the
633 * value in the "data" parameter will be shifted out to the PHY one
634 * bit at a time. In order to do this, "data" must be broken down
640 ctrl
= E1000_READ_REG(hw
, E1000_CTRL
);
642 /* Set MDIO_DIR and MDC_DIR direction bits to be used as output pins. */
643 ctrl
|= (E1000_CTRL_MDIO_DIR
| E1000_CTRL_MDC_DIR
);
647 * A "1" is shifted out to the PHY by setting the MDIO bit to
648 * "1" and then raising and lowering the Management Data Clock.
649 * A "0" is shifted out to the PHY by setting the MDIO bit to
650 * "0" and then raising and lowering the clock.
652 if (data
& mask
) ctrl
|= E1000_CTRL_MDIO
;
653 else ctrl
&= ~E1000_CTRL_MDIO
;
655 E1000_WRITE_REG(hw
, E1000_CTRL
, ctrl
);
656 E1000_WRITE_FLUSH(hw
);
660 e1000_raise_mdi_clk_82543(hw
, &ctrl
);
661 e1000_lower_mdi_clk_82543(hw
, &ctrl
);
668 * e1000_shift_in_mdi_bits_82543 - Shift data bits in from the PHY
669 * @hw: pointer to the HW structure
671 * In order to read a register from the PHY, we need to shift 18 bits
672 * in from the PHY. Bits are "shifted in" by raising the clock input to
673 * the PHY (setting the MDC bit), and then reading the value of the data out
676 static u16
e1000_shift_in_mdi_bits_82543(struct e1000_hw
*hw
)
683 * In order to read a register from the PHY, we need to shift in a
684 * total of 18 bits from the PHY. The first two bit (turnaround)
685 * times are used to avoid contention on the MDIO pin when a read
686 * operation is performed. These two bits are ignored by us and
687 * thrown away. Bits are "shifted in" by raising the input to the
688 * Management Data Clock (setting the MDC bit) and then reading the
689 * value of the MDIO bit.
691 ctrl
= E1000_READ_REG(hw
, E1000_CTRL
);
694 * Clear MDIO_DIR (SWDPIO1) to indicate this bit is to be used as
697 ctrl
&= ~E1000_CTRL_MDIO_DIR
;
698 ctrl
&= ~E1000_CTRL_MDIO
;
700 E1000_WRITE_REG(hw
, E1000_CTRL
, ctrl
);
701 E1000_WRITE_FLUSH(hw
);
704 * Raise and lower the clock before reading in the data. This accounts
705 * for the turnaround bits. The first clock occurred when we clocked
706 * out the last bit of the Register Address.
708 e1000_raise_mdi_clk_82543(hw
, &ctrl
);
709 e1000_lower_mdi_clk_82543(hw
, &ctrl
);
711 for (data
= 0, i
= 0; i
< 16; i
++) {
713 e1000_raise_mdi_clk_82543(hw
, &ctrl
);
714 ctrl
= E1000_READ_REG(hw
, E1000_CTRL
);
715 /* Check to see if we shifted in a "1". */
716 if (ctrl
& E1000_CTRL_MDIO
)
718 e1000_lower_mdi_clk_82543(hw
, &ctrl
);
721 e1000_raise_mdi_clk_82543(hw
, &ctrl
);
722 e1000_lower_mdi_clk_82543(hw
, &ctrl
);
728 * e1000_phy_force_speed_duplex_82543 - Force speed/duplex for PHY
729 * @hw: pointer to the HW structure
731 * Calls the function to force speed and duplex for the m88 PHY, and
732 * if the PHY is not auto-negotiating and the speed is forced to 10Mbit,
733 * then call the function for polarity reversal workaround.
735 static s32
e1000_phy_force_speed_duplex_82543(struct e1000_hw
*hw
)
739 DEBUGFUNC("e1000_phy_force_speed_duplex_82543");
741 ret_val
= e1000_phy_force_speed_duplex_m88(hw
);
745 if (!hw
->mac
.autoneg
&&
746 (hw
->mac
.forced_speed_duplex
& E1000_ALL_10_SPEED
))
747 ret_val
= e1000_polarity_reversal_workaround_82543(hw
);
754 * e1000_polarity_reversal_workaround_82543 - Workaround polarity reversal
755 * @hw: pointer to the HW structure
757 * When forcing link to 10 Full or 10 Half, the PHY can reverse the polarity
758 * inadvertently. To workaround the issue, we disable the transmitter on
759 * the PHY until we have established the link partner's link parameters.
761 static s32
e1000_polarity_reversal_workaround_82543(struct e1000_hw
*hw
)
763 s32 ret_val
= E1000_SUCCESS
;
768 if (!(hw
->phy
.ops
.write_reg
))
771 /* Polarity reversal workaround for forced 10F/10H links. */
773 /* Disable the transmitter on the PHY */
775 ret_val
= hw
->phy
.ops
.write_reg(hw
, M88E1000_PHY_PAGE_SELECT
, 0x0019);
778 ret_val
= hw
->phy
.ops
.write_reg(hw
, M88E1000_PHY_GEN_CONTROL
, 0xFFFF);
782 ret_val
= hw
->phy
.ops
.write_reg(hw
, M88E1000_PHY_PAGE_SELECT
, 0x0000);
787 * This loop will early-out if the NO link condition has been met.
788 * In other words, DO NOT use e1000_phy_has_link_generic() here.
790 for (i
= PHY_FORCE_TIME
; i
> 0; i
--) {
792 * Read the MII Status Register and wait for Link Status bit
796 ret_val
= hw
->phy
.ops
.read_reg(hw
, PHY_STATUS
, &mii_status_reg
);
800 ret_val
= hw
->phy
.ops
.read_reg(hw
, PHY_STATUS
, &mii_status_reg
);
804 if ((mii_status_reg
& ~MII_SR_LINK_STATUS
) == 0)
809 /* Recommended delay time after link has been lost */
810 msec_delay_irq(1000);
812 /* Now we will re-enable the transmitter on the PHY */
814 ret_val
= hw
->phy
.ops
.write_reg(hw
, M88E1000_PHY_PAGE_SELECT
, 0x0019);
818 ret_val
= hw
->phy
.ops
.write_reg(hw
, M88E1000_PHY_GEN_CONTROL
, 0xFFF0);
822 ret_val
= hw
->phy
.ops
.write_reg(hw
, M88E1000_PHY_GEN_CONTROL
, 0xFF00);
826 ret_val
= hw
->phy
.ops
.write_reg(hw
, M88E1000_PHY_GEN_CONTROL
, 0x0000);
830 ret_val
= hw
->phy
.ops
.write_reg(hw
, M88E1000_PHY_PAGE_SELECT
, 0x0000);
835 * Read the MII Status Register and wait for Link Status bit
838 ret_val
= e1000_phy_has_link_generic(hw
, PHY_FORCE_TIME
, 100000, &link
);
847 * e1000_phy_hw_reset_82543 - PHY hardware reset
848 * @hw: pointer to the HW structure
850 * Sets the PHY_RESET_DIR bit in the extended device control register
851 * to put the PHY into a reset and waits for completion. Once the reset
852 * has been accomplished, clear the PHY_RESET_DIR bit to take the PHY out
855 static s32
e1000_phy_hw_reset_82543(struct e1000_hw
*hw
)
860 DEBUGFUNC("e1000_phy_hw_reset_82543");
863 * Read the Extended Device Control Register, assert the PHY_RESET_DIR
864 * bit to put the PHY into reset...
866 ctrl_ext
= E1000_READ_REG(hw
, E1000_CTRL_EXT
);
867 ctrl_ext
|= E1000_CTRL_EXT_SDP4_DIR
;
868 ctrl_ext
&= ~E1000_CTRL_EXT_SDP4_DATA
;
869 E1000_WRITE_REG(hw
, E1000_CTRL_EXT
, ctrl_ext
);
870 E1000_WRITE_FLUSH(hw
);
874 /* ...then take it out of reset. */
875 ctrl_ext
|= E1000_CTRL_EXT_SDP4_DATA
;
876 E1000_WRITE_REG(hw
, E1000_CTRL_EXT
, ctrl_ext
);
877 E1000_WRITE_FLUSH(hw
);
881 if (!(hw
->phy
.ops
.get_cfg_done
))
882 return E1000_SUCCESS
;
884 ret_val
= hw
->phy
.ops
.get_cfg_done(hw
);
890 * e1000_reset_hw_82543 - Reset hardware
891 * @hw: pointer to the HW structure
893 * This resets the hardware into a known state.
895 static s32
e1000_reset_hw_82543(struct e1000_hw
*hw
)
898 s32 ret_val
= E1000_SUCCESS
;
900 DEBUGFUNC("e1000_reset_hw_82543");
902 DEBUGOUT("Masking off all interrupts\n");
903 E1000_WRITE_REG(hw
, E1000_IMC
, 0xffffffff);
905 E1000_WRITE_REG(hw
, E1000_RCTL
, 0);
906 E1000_WRITE_REG(hw
, E1000_TCTL
, E1000_TCTL_PSP
);
907 E1000_WRITE_FLUSH(hw
);
909 e1000_set_tbi_sbp_82543(hw
, false);
912 * Delay to allow any outstanding PCI transactions to complete before
913 * resetting the device
917 ctrl
= E1000_READ_REG(hw
, E1000_CTRL
);
919 DEBUGOUT("Issuing a global reset to 82543/82544 MAC\n");
920 if (hw
->mac
.type
== e1000_82543
) {
921 E1000_WRITE_REG(hw
, E1000_CTRL
, ctrl
| E1000_CTRL_RST
);
924 * The 82544 can't ACK the 64-bit write when issuing the
925 * reset, so use IO-mapping as a workaround.
927 E1000_WRITE_REG_IO(hw
, E1000_CTRL
, ctrl
| E1000_CTRL_RST
);
931 * After MAC reset, force reload of NVM to restore power-on
932 * settings to device.
934 hw
->nvm
.ops
.reload(hw
);
937 /* Masking off and clearing any pending interrupts */
938 E1000_WRITE_REG(hw
, E1000_IMC
, 0xffffffff);
939 E1000_READ_REG(hw
, E1000_ICR
);
945 * e1000_init_hw_82543 - Initialize hardware
946 * @hw: pointer to the HW structure
948 * This inits the hardware readying it for operation.
950 static s32
e1000_init_hw_82543(struct e1000_hw
*hw
)
952 struct e1000_mac_info
*mac
= &hw
->mac
;
953 struct e1000_dev_spec_82543
*dev_spec
= &hw
->dev_spec
._82543
;
958 DEBUGFUNC("e1000_init_hw_82543");
960 /* Disabling VLAN filtering */
961 E1000_WRITE_REG(hw
, E1000_VET
, 0);
962 mac
->ops
.clear_vfta(hw
);
964 /* Setup the receive address. */
965 e1000_init_rx_addrs_generic(hw
, mac
->rar_entry_count
);
967 /* Zero out the Multicast HASH table */
968 DEBUGOUT("Zeroing the MTA\n");
969 for (i
= 0; i
< mac
->mta_reg_count
; i
++) {
970 E1000_WRITE_REG_ARRAY(hw
, E1000_MTA
, i
, 0);
971 E1000_WRITE_FLUSH(hw
);
975 * Set the PCI priority bit correctly in the CTRL register. This
976 * determines if the adapter gives priority to receives, or if it
977 * gives equal priority to transmits and receives.
979 if (hw
->mac
.type
== e1000_82543
&& dev_spec
->dma_fairness
) {
980 ctrl
= E1000_READ_REG(hw
, E1000_CTRL
);
981 E1000_WRITE_REG(hw
, E1000_CTRL
, ctrl
| E1000_CTRL_PRIOR
);
984 e1000_pcix_mmrbc_workaround_generic(hw
);
986 /* Setup link and flow control */
987 ret_val
= mac
->ops
.setup_link(hw
);
990 * Clear all of the statistics registers (clear on read). It is
991 * important that we do this after we have tried to establish link
992 * because the symbol error count will increment wildly if there
995 e1000_clear_hw_cntrs_82543(hw
);
1001 * e1000_setup_link_82543 - Setup flow control and link settings
1002 * @hw: pointer to the HW structure
1004 * Read the EEPROM to determine the initial polarity value and write the
1005 * extended device control register with the information before calling
1006 * the generic setup link function, which does the following:
1007 * Determines which flow control settings to use, then configures flow
1008 * control. Calls the appropriate media-specific link configuration
1009 * function. Assuming the adapter has a valid link partner, a valid link
1010 * should be established. Assumes the hardware has previously been reset
1011 * and the transmitter and receiver are not enabled.
1013 static s32
e1000_setup_link_82543(struct e1000_hw
*hw
)
1019 DEBUGFUNC("e1000_setup_link_82543");
1022 * Take the 4 bits from NVM word 0xF that determine the initial
1023 * polarity value for the SW controlled pins, and setup the
1024 * Extended Device Control reg with that info.
1025 * This is needed because one of the SW controlled pins is used for
1026 * signal detection. So this should be done before phy setup.
1028 if (hw
->mac
.type
== e1000_82543
) {
1029 ret_val
= hw
->nvm
.ops
.read(hw
, NVM_INIT_CONTROL2_REG
, 1, &data
);
1031 DEBUGOUT("NVM Read Error\n");
1032 ret_val
= -E1000_ERR_NVM
;
1035 ctrl_ext
= ((data
& NVM_WORD0F_SWPDIO_EXT_MASK
) <<
1036 NVM_SWDPIO_EXT_SHIFT
);
1037 E1000_WRITE_REG(hw
, E1000_CTRL_EXT
, ctrl_ext
);
1040 ret_val
= e1000_setup_link_generic(hw
);
1047 * e1000_setup_copper_link_82543 - Configure copper link settings
1048 * @hw: pointer to the HW structure
1050 * Configures the link for auto-neg or forced speed and duplex. Then we check
1051 * for link, once link is established calls to configure collision distance
1052 * and flow control are called.
1054 static s32
e1000_setup_copper_link_82543(struct e1000_hw
*hw
)
1060 DEBUGFUNC("e1000_setup_copper_link_82543");
1062 ctrl
= E1000_READ_REG(hw
, E1000_CTRL
) | E1000_CTRL_SLU
;
1064 * With 82543, we need to force speed and duplex on the MAC
1065 * equal to what the PHY speed and duplex configuration is.
1066 * In addition, we need to perform a hardware reset on the
1067 * PHY to take it out of reset.
1069 if (hw
->mac
.type
== e1000_82543
) {
1070 ctrl
|= (E1000_CTRL_FRCSPD
| E1000_CTRL_FRCDPX
);
1071 E1000_WRITE_REG(hw
, E1000_CTRL
, ctrl
);
1072 ret_val
= hw
->phy
.ops
.reset(hw
);
1075 hw
->phy
.reset_disable
= false;
1077 ctrl
&= ~(E1000_CTRL_FRCSPD
| E1000_CTRL_FRCDPX
);
1078 E1000_WRITE_REG(hw
, E1000_CTRL
, ctrl
);
1081 /* Set MDI/MDI-X, Polarity Reversal, and downshift settings */
1082 ret_val
= e1000_copper_link_setup_m88(hw
);
1086 if (hw
->mac
.autoneg
) {
1088 * Setup autoneg and flow control advertisement and perform
1091 ret_val
= e1000_copper_link_autoneg(hw
);
1096 * PHY will be set to 10H, 10F, 100H or 100F
1097 * depending on user settings.
1099 DEBUGOUT("Forcing Speed and Duplex\n");
1100 ret_val
= e1000_phy_force_speed_duplex_82543(hw
);
1102 DEBUGOUT("Error Forcing Speed and Duplex\n");
1108 * Check link status. Wait up to 100 microseconds for link to become
1111 ret_val
= e1000_phy_has_link_generic(hw
,
1112 COPPER_LINK_UP_LIMIT
,
1120 DEBUGOUT("Valid link established!!!\n");
1121 /* Config the MAC and PHY after link is up */
1122 if (hw
->mac
.type
== e1000_82544
) {
1123 e1000_config_collision_dist_generic(hw
);
1125 ret_val
= e1000_config_mac_to_phy_82543(hw
);
1129 ret_val
= e1000_config_fc_after_link_up_generic(hw
);
1131 DEBUGOUT("Unable to establish link!!!\n");
1139 * e1000_setup_fiber_link_82543 - Setup link for fiber
1140 * @hw: pointer to the HW structure
1142 * Configures collision distance and flow control for fiber links. Upon
1143 * successful setup, poll for link.
1145 static s32
e1000_setup_fiber_link_82543(struct e1000_hw
*hw
)
1150 DEBUGFUNC("e1000_setup_fiber_link_82543");
1152 ctrl
= E1000_READ_REG(hw
, E1000_CTRL
);
1154 /* Take the link out of reset */
1155 ctrl
&= ~E1000_CTRL_LRST
;
1157 e1000_config_collision_dist_generic(hw
);
1159 ret_val
= e1000_commit_fc_settings_generic(hw
);
1163 DEBUGOUT("Auto-negotiation enabled\n");
1165 E1000_WRITE_REG(hw
, E1000_CTRL
, ctrl
);
1166 E1000_WRITE_FLUSH(hw
);
1170 * For these adapters, the SW definable pin 1 is cleared when the
1171 * optics detect a signal. If we have a signal, then poll for a
1172 * "Link-Up" indication.
1174 if (!(E1000_READ_REG(hw
, E1000_CTRL
) & E1000_CTRL_SWDPIN1
)) {
1175 ret_val
= e1000_poll_fiber_serdes_link_generic(hw
);
1177 DEBUGOUT("No signal detected\n");
1185 * e1000_check_for_copper_link_82543 - Check for link (Copper)
1186 * @hw: pointer to the HW structure
1188 * Checks the phy for link, if link exists, do the following:
1189 * - check for downshift
1190 * - do polarity workaround (if necessary)
1191 * - configure collision distance
1192 * - configure flow control after link up
1193 * - configure tbi compatibility
1195 static s32
e1000_check_for_copper_link_82543(struct e1000_hw
*hw
)
1197 struct e1000_mac_info
*mac
= &hw
->mac
;
1203 DEBUGFUNC("e1000_check_for_copper_link_82543");
1205 if (!mac
->get_link_status
) {
1206 ret_val
= E1000_SUCCESS
;
1210 ret_val
= e1000_phy_has_link_generic(hw
, 1, 0, &link
);
1215 goto out
; /* No link detected */
1217 mac
->get_link_status
= false;
1219 e1000_check_downshift_generic(hw
);
1222 * If we are forcing speed/duplex, then we can return since
1223 * we have already determined whether we have link or not.
1225 if (!mac
->autoneg
) {
1227 * If speed and duplex are forced to 10H or 10F, then we will
1228 * implement the polarity reversal workaround. We disable
1229 * interrupts first, and upon returning, place the devices
1230 * interrupt state to its previous value except for the link
1231 * status change interrupt which will happened due to the
1232 * execution of this workaround.
1234 if (mac
->forced_speed_duplex
& E1000_ALL_10_SPEED
) {
1235 E1000_WRITE_REG(hw
, E1000_IMC
, 0xFFFFFFFF);
1236 ret_val
= e1000_polarity_reversal_workaround_82543(hw
);
1237 icr
= E1000_READ_REG(hw
, E1000_ICR
);
1238 E1000_WRITE_REG(hw
, E1000_ICS
, (icr
& ~E1000_ICS_LSC
));
1239 E1000_WRITE_REG(hw
, E1000_IMS
, IMS_ENABLE_MASK
);
1242 ret_val
= -E1000_ERR_CONFIG
;
1247 * We have a M88E1000 PHY and Auto-Neg is enabled. If we
1248 * have Si on board that is 82544 or newer, Auto
1249 * Speed Detection takes care of MAC speed/duplex
1250 * configuration. So we only need to configure Collision
1251 * Distance in the MAC. Otherwise, we need to force
1252 * speed/duplex on the MAC to the current PHY speed/duplex
1255 if (mac
->type
== e1000_82544
)
1256 e1000_config_collision_dist_generic(hw
);
1258 ret_val
= e1000_config_mac_to_phy_82543(hw
);
1260 DEBUGOUT("Error configuring MAC to PHY settings\n");
1266 * Configure Flow Control now that Auto-Neg has completed.
1267 * First, we need to restore the desired flow control
1268 * settings because we may have had to re-autoneg with a
1269 * different link partner.
1271 ret_val
= e1000_config_fc_after_link_up_generic(hw
);
1273 DEBUGOUT("Error configuring flow control\n");
1277 * At this point we know that we are on copper and we have
1278 * auto-negotiated link. These are conditions for checking the link
1279 * partner capability register. We use the link speed to determine if
1280 * TBI compatibility needs to be turned on or off. If the link is not
1281 * at gigabit speed, then TBI compatibility is not needed. If we are
1282 * at gigabit speed, we turn on TBI compatibility.
1284 if (e1000_tbi_compatibility_enabled_82543(hw
)) {
1285 ret_val
= mac
->ops
.get_link_up_info(hw
, &speed
, &duplex
);
1287 DEBUGOUT("Error getting link speed and duplex\n");
1290 if (speed
!= SPEED_1000
) {
1292 * If link speed is not set to gigabit speed,
1293 * we do not need to enable TBI compatibility.
1295 if (e1000_tbi_sbp_enabled_82543(hw
)) {
1297 * If we previously were in the mode,
1300 e1000_set_tbi_sbp_82543(hw
, false);
1301 rctl
= E1000_READ_REG(hw
, E1000_RCTL
);
1302 rctl
&= ~E1000_RCTL_SBP
;
1303 E1000_WRITE_REG(hw
, E1000_RCTL
, rctl
);
1307 * If TBI compatibility is was previously off,
1308 * turn it on. For compatibility with a TBI link
1309 * partner, we will store bad packets. Some
1310 * frames have an additional byte on the end and
1311 * will look like CRC errors to to the hardware.
1313 if (!e1000_tbi_sbp_enabled_82543(hw
)) {
1314 e1000_set_tbi_sbp_82543(hw
, true);
1315 rctl
= E1000_READ_REG(hw
, E1000_RCTL
);
1316 rctl
|= E1000_RCTL_SBP
;
1317 E1000_WRITE_REG(hw
, E1000_RCTL
, rctl
);
1326 * e1000_check_for_fiber_link_82543 - Check for link (Fiber)
1327 * @hw: pointer to the HW structure
1329 * Checks for link up on the hardware. If link is not up and we have
1330 * a signal, then we need to force link up.
1332 static s32
e1000_check_for_fiber_link_82543(struct e1000_hw
*hw
)
1334 struct e1000_mac_info
*mac
= &hw
->mac
;
1335 u32 rxcw
, ctrl
, status
;
1336 s32 ret_val
= E1000_SUCCESS
;
1338 DEBUGFUNC("e1000_check_for_fiber_link_82543");
1340 ctrl
= E1000_READ_REG(hw
, E1000_CTRL
);
1341 status
= E1000_READ_REG(hw
, E1000_STATUS
);
1342 rxcw
= E1000_READ_REG(hw
, E1000_RXCW
);
1345 * If we don't have link (auto-negotiation failed or link partner
1346 * cannot auto-negotiate), the cable is plugged in (we have signal),
1347 * and our link partner is not trying to auto-negotiate with us (we
1348 * are receiving idles or data), we need to force link up. We also
1349 * need to give auto-negotiation time to complete, in case the cable
1350 * was just plugged in. The autoneg_failed flag does this.
1352 /* (ctrl & E1000_CTRL_SWDPIN1) == 0 == have signal */
1353 if ((!(ctrl
& E1000_CTRL_SWDPIN1
)) &&
1354 (!(status
& E1000_STATUS_LU
)) &&
1355 (!(rxcw
& E1000_RXCW_C
))) {
1356 if (mac
->autoneg_failed
== 0) {
1357 mac
->autoneg_failed
= 1;
1361 DEBUGOUT("NOT RXing /C/, disable AutoNeg and force link.\n");
1363 /* Disable auto-negotiation in the TXCW register */
1364 E1000_WRITE_REG(hw
, E1000_TXCW
, (mac
->txcw
& ~E1000_TXCW_ANE
));
1366 /* Force link-up and also force full-duplex. */
1367 ctrl
= E1000_READ_REG(hw
, E1000_CTRL
);
1368 ctrl
|= (E1000_CTRL_SLU
| E1000_CTRL_FD
);
1369 E1000_WRITE_REG(hw
, E1000_CTRL
, ctrl
);
1371 /* Configure Flow Control after forcing link up. */
1372 ret_val
= e1000_config_fc_after_link_up_generic(hw
);
1374 DEBUGOUT("Error configuring flow control\n");
1377 } else if ((ctrl
& E1000_CTRL_SLU
) && (rxcw
& E1000_RXCW_C
)) {
1379 * If we are forcing link and we are receiving /C/ ordered
1380 * sets, re-enable auto-negotiation in the TXCW register
1381 * and disable forced link in the Device Control register
1382 * in an attempt to auto-negotiate with our link partner.
1384 DEBUGOUT("RXing /C/, enable AutoNeg and stop forcing link.\n");
1385 E1000_WRITE_REG(hw
, E1000_TXCW
, mac
->txcw
);
1386 E1000_WRITE_REG(hw
, E1000_CTRL
, (ctrl
& ~E1000_CTRL_SLU
));
1388 mac
->serdes_has_link
= true;
1396 * e1000_config_mac_to_phy_82543 - Configure MAC to PHY settings
1397 * @hw: pointer to the HW structure
1399 * For the 82543 silicon, we need to set the MAC to match the settings
1400 * of the PHY, even if the PHY is auto-negotiating.
1402 static s32
e1000_config_mac_to_phy_82543(struct e1000_hw
*hw
)
1405 s32 ret_val
= E1000_SUCCESS
;
1408 DEBUGFUNC("e1000_config_mac_to_phy_82543");
1410 if (!(hw
->phy
.ops
.read_reg
))
1413 /* Set the bits to force speed and duplex */
1414 ctrl
= E1000_READ_REG(hw
, E1000_CTRL
);
1415 ctrl
|= (E1000_CTRL_FRCSPD
| E1000_CTRL_FRCDPX
);
1416 ctrl
&= ~(E1000_CTRL_SPD_SEL
| E1000_CTRL_ILOS
);
1419 * Set up duplex in the Device Control and Transmit Control
1420 * registers depending on negotiated values.
1422 ret_val
= hw
->phy
.ops
.read_reg(hw
, M88E1000_PHY_SPEC_STATUS
, &phy_data
);
1426 ctrl
&= ~E1000_CTRL_FD
;
1427 if (phy_data
& M88E1000_PSSR_DPLX
)
1428 ctrl
|= E1000_CTRL_FD
;
1430 e1000_config_collision_dist_generic(hw
);
1433 * Set up speed in the Device Control register depending on
1434 * negotiated values.
1436 if ((phy_data
& M88E1000_PSSR_SPEED
) == M88E1000_PSSR_1000MBS
)
1437 ctrl
|= E1000_CTRL_SPD_1000
;
1438 else if ((phy_data
& M88E1000_PSSR_SPEED
) == M88E1000_PSSR_100MBS
)
1439 ctrl
|= E1000_CTRL_SPD_100
;
1441 E1000_WRITE_REG(hw
, E1000_CTRL
, ctrl
);
1448 * e1000_write_vfta_82543 - Write value to VLAN filter table
1449 * @hw: pointer to the HW structure
1450 * @offset: the 32-bit offset in which to write the value to.
1451 * @value: the 32-bit value to write at location offset.
1453 * This writes a 32-bit value to a 32-bit offset in the VLAN filter
1456 static void e1000_write_vfta_82543(struct e1000_hw
*hw
, u32 offset
, u32 value
)
1460 DEBUGFUNC("e1000_write_vfta_82543");
1462 if ((hw
->mac
.type
== e1000_82544
) && (offset
& 1)) {
1463 temp
= E1000_READ_REG_ARRAY(hw
, E1000_VFTA
, offset
- 1);
1464 E1000_WRITE_REG_ARRAY(hw
, E1000_VFTA
, offset
, value
);
1465 E1000_WRITE_FLUSH(hw
);
1466 E1000_WRITE_REG_ARRAY(hw
, E1000_VFTA
, offset
- 1, temp
);
1467 E1000_WRITE_FLUSH(hw
);
1469 e1000_write_vfta_generic(hw
, offset
, value
);
1474 * e1000_mta_set_82543 - Set multicast filter table address
1475 * @hw: pointer to the HW structure
1476 * @hash_value: determines the MTA register and bit to set
1478 * The multicast table address is a register array of 32-bit registers.
1479 * The hash_value is used to determine what register the bit is in, the
1480 * current value is read, the new bit is OR'd in and the new value is
1481 * written back into the register.
1483 static void e1000_mta_set_82543(struct e1000_hw
*hw
, u32 hash_value
)
1485 u32 hash_bit
, hash_reg
, mta
, temp
;
1487 DEBUGFUNC("e1000_mta_set_82543");
1489 hash_reg
= (hash_value
>> 5);
1492 * If we are on an 82544 and we are trying to write an odd offset
1493 * in the MTA, save off the previous entry before writing and
1494 * restore the old value after writing.
1496 if ((hw
->mac
.type
== e1000_82544
) && (hash_reg
& 1)) {
1497 hash_reg
&= (hw
->mac
.mta_reg_count
- 1);
1498 hash_bit
= hash_value
& 0x1F;
1499 mta
= E1000_READ_REG_ARRAY(hw
, E1000_MTA
, hash_reg
);
1500 mta
|= (1 << hash_bit
);
1501 temp
= E1000_READ_REG_ARRAY(hw
, E1000_MTA
, hash_reg
- 1);
1503 E1000_WRITE_REG_ARRAY(hw
, E1000_MTA
, hash_reg
, mta
);
1504 E1000_WRITE_FLUSH(hw
);
1505 E1000_WRITE_REG_ARRAY(hw
, E1000_MTA
, hash_reg
- 1, temp
);
1506 E1000_WRITE_FLUSH(hw
);
1508 e1000_mta_set_generic(hw
, hash_value
);
1513 * e1000_led_on_82543 - Turn on SW controllable LED
1514 * @hw: pointer to the HW structure
1516 * Turns the SW defined LED on.
1518 static s32
e1000_led_on_82543(struct e1000_hw
*hw
)
1520 u32 ctrl
= E1000_READ_REG(hw
, E1000_CTRL
);
1522 DEBUGFUNC("e1000_led_on_82543");
1524 if (hw
->mac
.type
== e1000_82544
&&
1525 hw
->phy
.media_type
== e1000_media_type_copper
) {
1526 /* Clear SW-definable Pin 0 to turn on the LED */
1527 ctrl
&= ~E1000_CTRL_SWDPIN0
;
1528 ctrl
|= E1000_CTRL_SWDPIO0
;
1530 /* Fiber 82544 and all 82543 use this method */
1531 ctrl
|= E1000_CTRL_SWDPIN0
;
1532 ctrl
|= E1000_CTRL_SWDPIO0
;
1534 E1000_WRITE_REG(hw
, E1000_CTRL
, ctrl
);
1536 return E1000_SUCCESS
;
1540 * e1000_led_off_82543 - Turn off SW controllable LED
1541 * @hw: pointer to the HW structure
1543 * Turns the SW defined LED off.
1545 static s32
e1000_led_off_82543(struct e1000_hw
*hw
)
1547 u32 ctrl
= E1000_READ_REG(hw
, E1000_CTRL
);
1549 DEBUGFUNC("e1000_led_off_82543");
1551 if (hw
->mac
.type
== e1000_82544
&&
1552 hw
->phy
.media_type
== e1000_media_type_copper
) {
1553 /* Set SW-definable Pin 0 to turn off the LED */
1554 ctrl
|= E1000_CTRL_SWDPIN0
;
1555 ctrl
|= E1000_CTRL_SWDPIO0
;
1557 ctrl
&= ~E1000_CTRL_SWDPIN0
;
1558 ctrl
|= E1000_CTRL_SWDPIO0
;
1560 E1000_WRITE_REG(hw
, E1000_CTRL
, ctrl
);
1562 return E1000_SUCCESS
;
1566 * e1000_clear_hw_cntrs_82543 - Clear device specific hardware counters
1567 * @hw: pointer to the HW structure
1569 * Clears the hardware counters by reading the counter registers.
1571 static void e1000_clear_hw_cntrs_82543(struct e1000_hw
*hw
)
1573 DEBUGFUNC("e1000_clear_hw_cntrs_82543");
1575 e1000_clear_hw_cntrs_base_generic(hw
);
1577 E1000_READ_REG(hw
, E1000_PRC64
);
1578 E1000_READ_REG(hw
, E1000_PRC127
);
1579 E1000_READ_REG(hw
, E1000_PRC255
);
1580 E1000_READ_REG(hw
, E1000_PRC511
);
1581 E1000_READ_REG(hw
, E1000_PRC1023
);
1582 E1000_READ_REG(hw
, E1000_PRC1522
);
1583 E1000_READ_REG(hw
, E1000_PTC64
);
1584 E1000_READ_REG(hw
, E1000_PTC127
);
1585 E1000_READ_REG(hw
, E1000_PTC255
);
1586 E1000_READ_REG(hw
, E1000_PTC511
);
1587 E1000_READ_REG(hw
, E1000_PTC1023
);
1588 E1000_READ_REG(hw
, E1000_PTC1522
);
1590 E1000_READ_REG(hw
, E1000_ALGNERRC
);
1591 E1000_READ_REG(hw
, E1000_RXERRC
);
1592 E1000_READ_REG(hw
, E1000_TNCRS
);
1593 E1000_READ_REG(hw
, E1000_CEXTERR
);
1594 E1000_READ_REG(hw
, E1000_TSCTC
);
1595 E1000_READ_REG(hw
, E1000_TSCTFC
);