1 /*******************************************************************************
3 Intel PRO/1000 Linux driver
4 Copyright(c) 1999 - 2008 Intel Corporation.
6 This program is free software; you can redistribute it and/or modify it
7 under the terms and conditions of the GNU General Public License,
8 version 2, as published by the Free Software Foundation.
10 This program is distributed in the hope it will be useful, but WITHOUT
11 ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
12 FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
15 You should have received a copy of the GNU General Public License along with
16 this program; if not, write to the Free Software Foundation, Inc.,
17 51 Franklin St - Fifth Floor, Boston, MA 02110-1301 USA.
19 The full GNU General Public License is included in this distribution in
20 the file called "COPYING".
23 Linux NICS <linux.nics@intel.com>
24 e1000-devel Mailing List <e1000-devel@lists.sourceforge.net>
25 Intel Corporation, 5200 N.E. Elam Young Parkway, Hillsboro, OR 97124-6497
27 *******************************************************************************/
29 #ifndef _E1000_DEFINES_H_
30 #define _E1000_DEFINES_H_
32 /* Number of Transmit and Receive Descriptors must be a multiple of 8 */
33 #define REQ_TX_DESCRIPTOR_MULTIPLE 8
34 #define REQ_RX_DESCRIPTOR_MULTIPLE 8
36 /* Definitions for power management and wakeup registers */
38 #define E1000_WUC_APME 0x00000001 /* APM Enable */
39 #define E1000_WUC_PME_EN 0x00000002 /* PME Enable */
40 #define E1000_WUC_PME_STATUS 0x00000004 /* PME Status */
41 #define E1000_WUC_APMPME 0x00000008 /* Assert PME on APM Wakeup */
42 #define E1000_WUC_LSCWE 0x00000010 /* Link Status wake up enable */
43 #define E1000_WUC_LSCWO 0x00000020 /* Link Status wake up override */
44 #define E1000_WUC_SPM 0x80000000 /* Enable SPM */
45 #define E1000_WUC_PHY_WAKE 0x00000100 /* if PHY supports wakeup */
47 /* Wake Up Filter Control */
48 #define E1000_WUFC_LNKC 0x00000001 /* Link Status Change Wakeup Enable */
49 #define E1000_WUFC_MAG 0x00000002 /* Magic Packet Wakeup Enable */
50 #define E1000_WUFC_EX 0x00000004 /* Directed Exact Wakeup Enable */
51 #define E1000_WUFC_MC 0x00000008 /* Directed Multicast Wakeup Enable */
52 #define E1000_WUFC_BC 0x00000010 /* Broadcast Wakeup Enable */
53 #define E1000_WUFC_ARP 0x00000020 /* ARP Request Packet Wakeup Enable */
54 #define E1000_WUFC_IPV4 0x00000040 /* Directed IPv4 Packet Wakeup Enable */
55 #define E1000_WUFC_IPV6 0x00000080 /* Directed IPv6 Packet Wakeup Enable */
56 #define E1000_WUFC_IGNORE_TCO 0x00008000 /* Ignore WakeOn TCO packets */
57 #define E1000_WUFC_FLX0 0x00010000 /* Flexible Filter 0 Enable */
58 #define E1000_WUFC_FLX1 0x00020000 /* Flexible Filter 1 Enable */
59 #define E1000_WUFC_FLX2 0x00040000 /* Flexible Filter 2 Enable */
60 #define E1000_WUFC_FLX3 0x00080000 /* Flexible Filter 3 Enable */
61 #define E1000_WUFC_ALL_FILTERS 0x000F00FF /* Mask for all wakeup filters */
62 #define E1000_WUFC_FLX_OFFSET 16 /* Offset to the Flexible Filters bits */
63 #define E1000_WUFC_FLX_FILTERS 0x000F0000 /*Mask for the 4 flexible filters */
66 #define E1000_WUS_LNKC E1000_WUFC_LNKC
67 #define E1000_WUS_MAG E1000_WUFC_MAG
68 #define E1000_WUS_EX E1000_WUFC_EX
69 #define E1000_WUS_MC E1000_WUFC_MC
70 #define E1000_WUS_BC E1000_WUFC_BC
71 #define E1000_WUS_ARP E1000_WUFC_ARP
72 #define E1000_WUS_IPV4 E1000_WUFC_IPV4
73 #define E1000_WUS_IPV6 E1000_WUFC_IPV6
74 #define E1000_WUS_FLX0 E1000_WUFC_FLX0
75 #define E1000_WUS_FLX1 E1000_WUFC_FLX1
76 #define E1000_WUS_FLX2 E1000_WUFC_FLX2
77 #define E1000_WUS_FLX3 E1000_WUFC_FLX3
78 #define E1000_WUS_FLX_FILTERS E1000_WUFC_FLX_FILTERS
80 /* Wake Up Packet Length */
81 #define E1000_WUPL_LENGTH_MASK 0x0FFF /* Only the lower 12 bits are valid */
83 /* Four Flexible Filters are supported */
84 #define E1000_FLEXIBLE_FILTER_COUNT_MAX 4
86 /* Each Flexible Filter is at most 128 (0x80) bytes in length */
87 #define E1000_FLEXIBLE_FILTER_SIZE_MAX 128
89 #define E1000_FFLT_SIZE E1000_FLEXIBLE_FILTER_COUNT_MAX
90 #define E1000_FFMT_SIZE E1000_FLEXIBLE_FILTER_SIZE_MAX
91 #define E1000_FFVT_SIZE E1000_FLEXIBLE_FILTER_SIZE_MAX
93 /* Extended Device Control */
94 #define E1000_CTRL_EXT_GPI0_EN 0x00000001 /* Maps SDP4 to GPI0 */
95 #define E1000_CTRL_EXT_GPI1_EN 0x00000002 /* Maps SDP5 to GPI1 */
96 #define E1000_CTRL_EXT_PHYINT_EN E1000_CTRL_EXT_GPI1_EN
97 #define E1000_CTRL_EXT_GPI2_EN 0x00000004 /* Maps SDP6 to GPI2 */
98 #define E1000_CTRL_EXT_GPI3_EN 0x00000008 /* Maps SDP7 to GPI3 */
99 /* Reserved (bits 4,5) in >= 82575 */
100 #define E1000_CTRL_EXT_SDP4_DATA 0x00000010 /* Value of SW Definable Pin 4 */
101 #define E1000_CTRL_EXT_SDP5_DATA 0x00000020 /* Value of SW Definable Pin 5 */
102 #define E1000_CTRL_EXT_PHY_INT E1000_CTRL_EXT_SDP5_DATA
103 #define E1000_CTRL_EXT_SDP6_DATA 0x00000040 /* Value of SW Definable Pin 6 */
104 #define E1000_CTRL_EXT_SDP7_DATA 0x00000080 /* Value of SW Definable Pin 7 */
105 /* SDP 4/5 (bits 8,9) are reserved in >= 82575 */
106 #define E1000_CTRL_EXT_SDP4_DIR 0x00000100 /* Direction of SDP4 0=in 1=out */
107 #define E1000_CTRL_EXT_SDP5_DIR 0x00000200 /* Direction of SDP5 0=in 1=out */
108 #define E1000_CTRL_EXT_SDP6_DIR 0x00000400 /* Direction of SDP6 0=in 1=out */
109 #define E1000_CTRL_EXT_SDP7_DIR 0x00000800 /* Direction of SDP7 0=in 1=out */
110 #define E1000_CTRL_EXT_ASDCHK 0x00001000 /* Initiate an ASD sequence */
111 #define E1000_CTRL_EXT_EE_RST 0x00002000 /* Reinitialize from EEPROM */
112 #define E1000_CTRL_EXT_IPS 0x00004000 /* Invert Power State */
113 #define E1000_CTRL_EXT_SPD_BYPS 0x00008000 /* Speed Select Bypass */
114 #define E1000_CTRL_EXT_RO_DIS 0x00020000 /* Relaxed Ordering disable */
115 #define E1000_CTRL_EXT_DMA_DYN_CLK_EN 0x00080000 /* DMA Dynamic Clock Gating */
116 #define E1000_CTRL_EXT_LINK_MODE_MASK 0x00C00000
117 #define E1000_CTRL_EXT_LINK_MODE_GMII 0x00000000
118 #define E1000_CTRL_EXT_LINK_MODE_TBI 0x00C00000
119 #define E1000_CTRL_EXT_LINK_MODE_KMRN 0x00000000
120 #define E1000_CTRL_EXT_LINK_MODE_PCIE_SERDES 0x00C00000
121 #define E1000_CTRL_EXT_LINK_MODE_PCIX_SERDES 0x00800000
122 #define E1000_CTRL_EXT_LINK_MODE_SGMII 0x00800000
123 #define E1000_CTRL_EXT_EIAME 0x01000000
124 #define E1000_CTRL_EXT_IRCA 0x00000001
125 #define E1000_CTRL_EXT_WR_WMARK_MASK 0x03000000
126 #define E1000_CTRL_EXT_WR_WMARK_256 0x00000000
127 #define E1000_CTRL_EXT_WR_WMARK_320 0x01000000
128 #define E1000_CTRL_EXT_WR_WMARK_384 0x02000000
129 #define E1000_CTRL_EXT_WR_WMARK_448 0x03000000
130 #define E1000_CTRL_EXT_CANC 0x04000000 /* Int delay cancellation */
131 #define E1000_CTRL_EXT_DRV_LOAD 0x10000000 /* Driver loaded bit for FW */
132 /* IAME enable bit (27) was removed in >= 82575 */
133 #define E1000_CTRL_EXT_IAME 0x08000000 /* Int acknowledge Auto-mask */
134 #define E1000_CRTL_EXT_PB_PAREN 0x01000000 /* packet buffer parity error
135 * detection enabled */
136 #define E1000_CTRL_EXT_DF_PAREN 0x02000000 /* descriptor FIFO parity
137 * error detection enable */
138 #define E1000_CTRL_EXT_GHOST_PAREN 0x40000000
139 #define E1000_CTRL_EXT_PBA_CLR 0x80000000 /* PBA Clear */
140 #define E1000_I2CCMD_REG_ADDR_SHIFT 16
141 #define E1000_I2CCMD_REG_ADDR 0x00FF0000
142 #define E1000_I2CCMD_PHY_ADDR_SHIFT 24
143 #define E1000_I2CCMD_PHY_ADDR 0x07000000
144 #define E1000_I2CCMD_OPCODE_READ 0x08000000
145 #define E1000_I2CCMD_OPCODE_WRITE 0x00000000
146 #define E1000_I2CCMD_RESET 0x10000000
147 #define E1000_I2CCMD_READY 0x20000000
148 #define E1000_I2CCMD_INTERRUPT_ENA 0x40000000
149 #define E1000_I2CCMD_ERROR 0x80000000
150 #define E1000_MAX_SGMII_PHY_REG_ADDR 255
151 #define E1000_I2CCMD_PHY_TIMEOUT 200
153 /* Receive Descriptor bit definitions */
154 #define E1000_RXD_STAT_DD 0x01 /* Descriptor Done */
155 #define E1000_RXD_STAT_EOP 0x02 /* End of Packet */
156 #define E1000_RXD_STAT_IXSM 0x04 /* Ignore checksum */
157 #define E1000_RXD_STAT_VP 0x08 /* IEEE VLAN Packet */
158 #define E1000_RXD_STAT_UDPCS 0x10 /* UDP xsum calculated */
159 #define E1000_RXD_STAT_TCPCS 0x20 /* TCP xsum calculated */
160 #define E1000_RXD_STAT_IPCS 0x40 /* IP xsum calculated */
161 #define E1000_RXD_STAT_PIF 0x80 /* passed in-exact filter */
162 #define E1000_RXD_STAT_CRCV 0x100 /* Speculative CRC Valid */
163 #define E1000_RXD_STAT_IPIDV 0x200 /* IP identification valid */
164 #define E1000_RXD_STAT_UDPV 0x400 /* Valid UDP checksum */
165 #define E1000_RXD_STAT_DYNINT 0x800 /* Pkt caused INT via DYNINT */
166 #define E1000_RXD_STAT_ACK 0x8000 /* ACK Packet indication */
167 #define E1000_RXD_ERR_CE 0x01 /* CRC Error */
168 #define E1000_RXD_ERR_SE 0x02 /* Symbol Error */
169 #define E1000_RXD_ERR_SEQ 0x04 /* Sequence Error */
170 #define E1000_RXD_ERR_CXE 0x10 /* Carrier Extension Error */
171 #define E1000_RXD_ERR_TCPE 0x20 /* TCP/UDP Checksum Error */
172 #define E1000_RXD_ERR_IPE 0x40 /* IP Checksum Error */
173 #define E1000_RXD_ERR_RXE 0x80 /* Rx Data Error */
174 #define E1000_RXD_SPC_VLAN_MASK 0x0FFF /* VLAN ID is in lower 12 bits */
175 #define E1000_RXD_SPC_PRI_MASK 0xE000 /* Priority is in upper 3 bits */
176 #define E1000_RXD_SPC_PRI_SHIFT 13
177 #define E1000_RXD_SPC_CFI_MASK 0x1000 /* CFI is bit 12 */
178 #define E1000_RXD_SPC_CFI_SHIFT 12
180 #define E1000_RXDEXT_STATERR_CE 0x01000000
181 #define E1000_RXDEXT_STATERR_SE 0x02000000
182 #define E1000_RXDEXT_STATERR_SEQ 0x04000000
183 #define E1000_RXDEXT_STATERR_CXE 0x10000000
184 #define E1000_RXDEXT_STATERR_TCPE 0x20000000
185 #define E1000_RXDEXT_STATERR_IPE 0x40000000
186 #define E1000_RXDEXT_STATERR_RXE 0x80000000
188 /* mask to determine if packets should be dropped due to frame errors */
189 #define E1000_RXD_ERR_FRAME_ERR_MASK ( \
192 E1000_RXD_ERR_SEQ | \
193 E1000_RXD_ERR_CXE | \
196 /* Same mask, but for extended and packet split descriptors */
197 #define E1000_RXDEXT_ERR_FRAME_ERR_MASK ( \
198 E1000_RXDEXT_STATERR_CE | \
199 E1000_RXDEXT_STATERR_SE | \
200 E1000_RXDEXT_STATERR_SEQ | \
201 E1000_RXDEXT_STATERR_CXE | \
202 E1000_RXDEXT_STATERR_RXE)
204 #define E1000_MRQC_ENABLE_MASK 0x00000007
205 #define E1000_MRQC_ENABLE_RSS_2Q 0x00000001
206 #define E1000_MRQC_ENABLE_RSS_INT 0x00000004
207 #define E1000_MRQC_RSS_FIELD_MASK 0xFFFF0000
208 #define E1000_MRQC_RSS_FIELD_IPV4_TCP 0x00010000
209 #define E1000_MRQC_RSS_FIELD_IPV4 0x00020000
210 #define E1000_MRQC_RSS_FIELD_IPV6_TCP_EX 0x00040000
211 #define E1000_MRQC_RSS_FIELD_IPV6_EX 0x00080000
212 #define E1000_MRQC_RSS_FIELD_IPV6 0x00100000
213 #define E1000_MRQC_RSS_FIELD_IPV6_TCP 0x00200000
215 #define E1000_RXDPS_HDRSTAT_HDRSP 0x00008000
216 #define E1000_RXDPS_HDRSTAT_HDRLEN_MASK 0x000003FF
218 /* Management Control */
219 #define E1000_MANC_SMBUS_EN 0x00000001 /* SMBus Enabled - RO */
220 #define E1000_MANC_ASF_EN 0x00000002 /* ASF Enabled - RO */
221 #define E1000_MANC_R_ON_FORCE 0x00000004 /* Reset on Force TCO - RO */
222 #define E1000_MANC_RMCP_EN 0x00000100 /* Enable RCMP 026Fh Filtering */
223 #define E1000_MANC_0298_EN 0x00000200 /* Enable RCMP 0298h Filtering */
224 #define E1000_MANC_IPV4_EN 0x00000400 /* Enable IPv4 */
225 #define E1000_MANC_IPV6_EN 0x00000800 /* Enable IPv6 */
226 #define E1000_MANC_SNAP_EN 0x00001000 /* Accept LLC/SNAP */
227 #define E1000_MANC_ARP_EN 0x00002000 /* Enable ARP Request Filtering */
228 /* Enable Neighbor Discovery Filtering */
229 #define E1000_MANC_NEIGHBOR_EN 0x00004000
230 #define E1000_MANC_ARP_RES_EN 0x00008000 /* Enable ARP response Filtering */
231 #define E1000_MANC_TCO_RESET 0x00010000 /* TCO Reset Occurred */
232 #define E1000_MANC_RCV_TCO_EN 0x00020000 /* Receive TCO Packets Enabled */
233 #define E1000_MANC_REPORT_STATUS 0x00040000 /* Status Reporting Enabled */
234 #define E1000_MANC_RCV_ALL 0x00080000 /* Receive All Enabled */
235 #define E1000_MANC_BLK_PHY_RST_ON_IDE 0x00040000 /* Block phy resets */
236 /* Enable MAC address filtering */
237 #define E1000_MANC_EN_MAC_ADDR_FILTER 0x00100000
238 /* Enable MNG packets to host memory */
239 #define E1000_MANC_EN_MNG2HOST 0x00200000
240 /* Enable IP address filtering */
241 #define E1000_MANC_EN_IP_ADDR_FILTER 0x00400000
242 #define E1000_MANC_EN_XSUM_FILTER 0x00800000 /* Enable checksum filtering */
243 #define E1000_MANC_BR_EN 0x01000000 /* Enable broadcast filtering */
244 #define E1000_MANC_SMB_REQ 0x01000000 /* SMBus Request */
245 #define E1000_MANC_SMB_GNT 0x02000000 /* SMBus Grant */
246 #define E1000_MANC_SMB_CLK_IN 0x04000000 /* SMBus Clock In */
247 #define E1000_MANC_SMB_DATA_IN 0x08000000 /* SMBus Data In */
248 #define E1000_MANC_SMB_DATA_OUT 0x10000000 /* SMBus Data Out */
249 #define E1000_MANC_SMB_CLK_OUT 0x20000000 /* SMBus Clock Out */
251 #define E1000_MANC_SMB_DATA_OUT_SHIFT 28 /* SMBus Data Out Shift */
252 #define E1000_MANC_SMB_CLK_OUT_SHIFT 29 /* SMBus Clock Out Shift */
254 /* Receive Control */
255 #define E1000_RCTL_RST 0x00000001 /* Software reset */
256 #define E1000_RCTL_EN 0x00000002 /* enable */
257 #define E1000_RCTL_SBP 0x00000004 /* store bad packet */
258 #define E1000_RCTL_UPE 0x00000008 /* unicast promisc enable */
259 #define E1000_RCTL_MPE 0x00000010 /* multicast promisc enable */
260 #define E1000_RCTL_LPE 0x00000020 /* long packet enable */
261 #define E1000_RCTL_LBM_NO 0x00000000 /* no loopback mode */
262 #define E1000_RCTL_LBM_MAC 0x00000040 /* MAC loopback mode */
263 #define E1000_RCTL_LBM_SLP 0x00000080 /* serial link loopback mode */
264 #define E1000_RCTL_LBM_TCVR 0x000000C0 /* tcvr loopback mode */
265 #define E1000_RCTL_DTYP_MASK 0x00000C00 /* Descriptor type mask */
266 #define E1000_RCTL_DTYP_PS 0x00000400 /* Packet Split descriptor */
267 #define E1000_RCTL_RDMTS_HALF 0x00000000 /* rx desc min thresh size */
268 #define E1000_RCTL_RDMTS_QUAT 0x00000100 /* rx desc min thresh size */
269 #define E1000_RCTL_RDMTS_EIGTH 0x00000200 /* rx desc min thresh size */
270 #define E1000_RCTL_MO_SHIFT 12 /* multicast offset shift */
271 #define E1000_RCTL_MO_0 0x00000000 /* multicast offset 11:0 */
272 #define E1000_RCTL_MO_1 0x00001000 /* multicast offset 12:1 */
273 #define E1000_RCTL_MO_2 0x00002000 /* multicast offset 13:2 */
274 #define E1000_RCTL_MO_3 0x00003000 /* multicast offset 15:4 */
275 #define E1000_RCTL_MDR 0x00004000 /* multicast desc ring 0 */
276 #define E1000_RCTL_BAM 0x00008000 /* broadcast enable */
277 /* these buffer sizes are valid if E1000_RCTL_BSEX is 0 */
278 #define E1000_RCTL_SZ_2048 0x00000000 /* rx buffer size 2048 */
279 #define E1000_RCTL_SZ_1024 0x00010000 /* rx buffer size 1024 */
280 #define E1000_RCTL_SZ_512 0x00020000 /* rx buffer size 512 */
281 #define E1000_RCTL_SZ_256 0x00030000 /* rx buffer size 256 */
282 /* these buffer sizes are valid if E1000_RCTL_BSEX is 1 */
283 #define E1000_RCTL_SZ_16384 0x00010000 /* rx buffer size 16384 */
284 #define E1000_RCTL_SZ_8192 0x00020000 /* rx buffer size 8192 */
285 #define E1000_RCTL_SZ_4096 0x00030000 /* rx buffer size 4096 */
286 #define E1000_RCTL_VFE 0x00040000 /* vlan filter enable */
287 #define E1000_RCTL_CFIEN 0x00080000 /* canonical form enable */
288 #define E1000_RCTL_CFI 0x00100000 /* canonical form indicator */
289 #define E1000_RCTL_DPF 0x00400000 /* discard pause frames */
290 #define E1000_RCTL_PMCF 0x00800000 /* pass MAC control frames */
291 #define E1000_RCTL_BSEX 0x02000000 /* Buffer size extension */
292 #define E1000_RCTL_SECRC 0x04000000 /* Strip Ethernet CRC */
293 #define E1000_RCTL_FLXBUF_MASK 0x78000000 /* Flexible buffer size */
294 #define E1000_RCTL_FLXBUF_SHIFT 27 /* Flexible buffer shift */
297 * Use byte values for the following shift parameters
299 * psrctl |= (((ROUNDUP(value0, 128) >> E1000_PSRCTL_BSIZE0_SHIFT) &
300 * E1000_PSRCTL_BSIZE0_MASK) |
301 * ((ROUNDUP(value1, 1024) >> E1000_PSRCTL_BSIZE1_SHIFT) &
302 * E1000_PSRCTL_BSIZE1_MASK) |
303 * ((ROUNDUP(value2, 1024) << E1000_PSRCTL_BSIZE2_SHIFT) &
304 * E1000_PSRCTL_BSIZE2_MASK) |
305 * ((ROUNDUP(value3, 1024) << E1000_PSRCTL_BSIZE3_SHIFT) |;
306 * E1000_PSRCTL_BSIZE3_MASK))
307 * where value0 = [128..16256], default=256
308 * value1 = [1024..64512], default=4096
309 * value2 = [0..64512], default=4096
310 * value3 = [0..64512], default=0
313 #define E1000_PSRCTL_BSIZE0_MASK 0x0000007F
314 #define E1000_PSRCTL_BSIZE1_MASK 0x00003F00
315 #define E1000_PSRCTL_BSIZE2_MASK 0x003F0000
316 #define E1000_PSRCTL_BSIZE3_MASK 0x3F000000
318 #define E1000_PSRCTL_BSIZE0_SHIFT 7 /* Shift _right_ 7 */
319 #define E1000_PSRCTL_BSIZE1_SHIFT 2 /* Shift _right_ 2 */
320 #define E1000_PSRCTL_BSIZE2_SHIFT 6 /* Shift _left_ 6 */
321 #define E1000_PSRCTL_BSIZE3_SHIFT 14 /* Shift _left_ 14 */
323 /* SWFW_SYNC Definitions */
324 #define E1000_SWFW_EEP_SM 0x1
325 #define E1000_SWFW_PHY0_SM 0x2
326 #define E1000_SWFW_PHY1_SM 0x4
327 #define E1000_SWFW_CSR_SM 0x8
329 /* FACTPS Definitions */
330 #define E1000_FACTPS_LFS 0x40000000 /* LAN Function Select */
332 #define E1000_CTRL_FD 0x00000001 /* Full duplex.0=half; 1=full */
333 #define E1000_CTRL_BEM 0x00000002 /* Endian Mode.0=little,1=big */
334 #define E1000_CTRL_PRIOR 0x00000004 /* Priority on PCI. 0=rx,1=fair */
335 #define E1000_CTRL_GIO_MASTER_DISABLE 0x00000004 /*Blocks new Master reqs */
336 #define E1000_CTRL_LRST 0x00000008 /* Link reset. 0=normal,1=reset */
337 #define E1000_CTRL_TME 0x00000010 /* Test mode. 0=normal,1=test */
338 #define E1000_CTRL_SLE 0x00000020 /* Serial Link on 0=dis,1=en */
339 #define E1000_CTRL_ASDE 0x00000020 /* Auto-speed detect enable */
340 #define E1000_CTRL_SLU 0x00000040 /* Set link up (Force Link) */
341 #define E1000_CTRL_ILOS 0x00000080 /* Invert Loss-Of Signal */
342 #define E1000_CTRL_SPD_SEL 0x00000300 /* Speed Select Mask */
343 #define E1000_CTRL_SPD_10 0x00000000 /* Force 10Mb */
344 #define E1000_CTRL_SPD_100 0x00000100 /* Force 100Mb */
345 #define E1000_CTRL_SPD_1000 0x00000200 /* Force 1Gb */
346 #define E1000_CTRL_BEM32 0x00000400 /* Big Endian 32 mode */
347 #define E1000_CTRL_FRCSPD 0x00000800 /* Force Speed */
348 #define E1000_CTRL_FRCDPX 0x00001000 /* Force Duplex */
349 #define E1000_CTRL_D_UD_EN 0x00002000 /* Dock/Undock enable */
350 #define E1000_CTRL_D_UD_POLARITY 0x00004000 /* Defined polarity of Dock/Undock
351 * indication in SDP[0] */
352 #define E1000_CTRL_FORCE_PHY_RESET 0x00008000 /* Reset both PHY ports, through
354 #define E1000_CTRL_EXT_LINK_EN 0x00010000 /* enable link status from external
355 * LINK_0 and LINK_1 pins */
356 #define E1000_CTRL_SWDPIN0 0x00040000 /* SWDPIN 0 value */
357 #define E1000_CTRL_SWDPIN1 0x00080000 /* SWDPIN 1 value */
358 #define E1000_CTRL_SWDPIN2 0x00100000 /* SWDPIN 2 value */
359 #define E1000_CTRL_SWDPIN3 0x00200000 /* SWDPIN 3 value */
360 #define E1000_CTRL_SWDPIO0 0x00400000 /* SWDPIN 0 Input or output */
361 #define E1000_CTRL_SWDPIO1 0x00800000 /* SWDPIN 1 input or output */
362 #define E1000_CTRL_SWDPIO2 0x01000000 /* SWDPIN 2 input or output */
363 #define E1000_CTRL_SWDPIO3 0x02000000 /* SWDPIN 3 input or output */
364 #define E1000_CTRL_RST 0x04000000 /* Global reset */
365 #define E1000_CTRL_RFCE 0x08000000 /* Receive Flow Control enable */
366 #define E1000_CTRL_TFCE 0x10000000 /* Transmit flow control enable */
367 #define E1000_CTRL_RTE 0x20000000 /* Routing tag enable */
368 #define E1000_CTRL_VME 0x40000000 /* IEEE VLAN mode enable */
369 #define E1000_CTRL_PHY_RST 0x80000000 /* PHY Reset */
370 #define E1000_CTRL_SW2FW_INT 0x02000000 /* Initiate an interrupt to ME */
371 #define E1000_CTRL_I2C_ENA 0x02000000 /* I2C enable */
374 * Bit definitions for the Management Data IO (MDIO) and Management Data
375 * Clock (MDC) pins in the Device Control Register.
377 #define E1000_CTRL_PHY_RESET_DIR E1000_CTRL_SWDPIO0
378 #define E1000_CTRL_PHY_RESET E1000_CTRL_SWDPIN0
379 #define E1000_CTRL_MDIO_DIR E1000_CTRL_SWDPIO2
380 #define E1000_CTRL_MDIO E1000_CTRL_SWDPIN2
381 #define E1000_CTRL_MDC_DIR E1000_CTRL_SWDPIO3
382 #define E1000_CTRL_MDC E1000_CTRL_SWDPIN3
383 #define E1000_CTRL_PHY_RESET_DIR4 E1000_CTRL_EXT_SDP4_DIR
384 #define E1000_CTRL_PHY_RESET4 E1000_CTRL_EXT_SDP4_DATA
386 #define E1000_CONNSW_ENRGSRC 0x4
387 #define E1000_PCS_CFG_PCS_EN 8
388 #define E1000_PCS_LCTL_FLV_LINK_UP 1
389 #define E1000_PCS_LCTL_FSV_10 0
390 #define E1000_PCS_LCTL_FSV_100 2
391 #define E1000_PCS_LCTL_FSV_1000 4
392 #define E1000_PCS_LCTL_FDV_FULL 8
393 #define E1000_PCS_LCTL_FSD 0x10
394 #define E1000_PCS_LCTL_FORCE_LINK 0x20
395 #define E1000_PCS_LCTL_LOW_LINK_LATCH 0x40
396 #define E1000_PCS_LCTL_FORCE_FCTRL 0x80
397 #define E1000_PCS_LCTL_AN_ENABLE 0x10000
398 #define E1000_PCS_LCTL_AN_RESTART 0x20000
399 #define E1000_PCS_LCTL_AN_TIMEOUT 0x40000
400 #define E1000_PCS_LCTL_AN_SGMII_BYPASS 0x80000
401 #define E1000_PCS_LCTL_AN_SGMII_TRIGGER 0x100000
402 #define E1000_PCS_LCTL_FAST_LINK_TIMER 0x1000000
403 #define E1000_PCS_LCTL_LINK_OK_FIX 0x2000000
404 #define E1000_PCS_LCTL_CRS_ON_NI 0x4000000
405 #define E1000_ENABLE_SERDES_LOOPBACK 0x0410
407 #define E1000_PCS_LSTS_LINK_OK 1
408 #define E1000_PCS_LSTS_SPEED_10 0
409 #define E1000_PCS_LSTS_SPEED_100 2
410 #define E1000_PCS_LSTS_SPEED_1000 4
411 #define E1000_PCS_LSTS_DUPLEX_FULL 8
412 #define E1000_PCS_LSTS_SYNK_OK 0x10
413 #define E1000_PCS_LSTS_AN_COMPLETE 0x10000
414 #define E1000_PCS_LSTS_AN_PAGE_RX 0x20000
415 #define E1000_PCS_LSTS_AN_TIMED_OUT 0x40000
416 #define E1000_PCS_LSTS_AN_REMOTE_FAULT 0x80000
417 #define E1000_PCS_LSTS_AN_ERROR_RWS 0x100000
420 #define E1000_STATUS_FD 0x00000001 /* Full duplex.0=half,1=full */
421 #define E1000_STATUS_LU 0x00000002 /* Link up.0=no,1=link */
422 #define E1000_STATUS_FUNC_MASK 0x0000000C /* PCI Function Mask */
423 #define E1000_STATUS_FUNC_SHIFT 2
424 #define E1000_STATUS_FUNC_0 0x00000000 /* Function 0 */
425 #define E1000_STATUS_FUNC_1 0x00000004 /* Function 1 */
426 #define E1000_STATUS_TXOFF 0x00000010 /* transmission paused */
427 #define E1000_STATUS_TBIMODE 0x00000020 /* TBI mode */
428 #define E1000_STATUS_SPEED_MASK 0x000000C0
429 #define E1000_STATUS_SPEED_10 0x00000000 /* Speed 10Mb/s */
430 #define E1000_STATUS_SPEED_100 0x00000040 /* Speed 100Mb/s */
431 #define E1000_STATUS_SPEED_1000 0x00000080 /* Speed 1000Mb/s */
432 #define E1000_STATUS_LAN_INIT_DONE 0x00000200 /* Lan Init Completion by NVM */
433 #define E1000_STATUS_ASDV 0x00000300 /* Auto speed detect value */
434 #define E1000_STATUS_DOCK_CI 0x00000800 /* Change in Dock/Undock state.
435 * Clear on write '0'. */
436 #define E1000_STATUS_GIO_MASTER_ENABLE 0x00080000 /* Master request status */
437 #define E1000_STATUS_MTXCKOK 0x00000400 /* MTX clock running OK */
438 #define E1000_STATUS_PCI66 0x00000800 /* In 66Mhz slot */
439 #define E1000_STATUS_BUS64 0x00001000 /* In 64 bit slot */
440 #define E1000_STATUS_PCIX_MODE 0x00002000 /* PCI-X mode */
441 #define E1000_STATUS_PCIX_SPEED 0x0000C000 /* PCI-X bus speed */
442 #define E1000_STATUS_BMC_SKU_0 0x00100000 /* BMC USB redirect disabled */
443 #define E1000_STATUS_BMC_SKU_1 0x00200000 /* BMC SRAM disabled */
444 #define E1000_STATUS_BMC_SKU_2 0x00400000 /* BMC SDRAM disabled */
445 #define E1000_STATUS_BMC_CRYPTO 0x00800000 /* BMC crypto disabled */
446 #define E1000_STATUS_BMC_LITE 0x01000000 /* BMC external code execution
448 #define E1000_STATUS_RGMII_ENABLE 0x02000000 /* RGMII disabled */
449 #define E1000_STATUS_FUSE_8 0x04000000
450 #define E1000_STATUS_FUSE_9 0x08000000
451 #define E1000_STATUS_SERDES0_DIS 0x10000000 /* SERDES disabled on port 0 */
452 #define E1000_STATUS_SERDES1_DIS 0x20000000 /* SERDES disabled on port 1 */
454 /* Constants used to interpret the masked PCI-X bus speed. */
455 #define E1000_STATUS_PCIX_SPEED_66 0x00000000 /* PCI-X bus speed 50-66 MHz */
456 #define E1000_STATUS_PCIX_SPEED_100 0x00004000 /* PCI-X bus speed 66-100 MHz */
457 #define E1000_STATUS_PCIX_SPEED_133 0x00008000 /*PCI-X bus speed 100-133 MHz*/
460 #define SPEED_100 100
461 #define SPEED_1000 1000
462 #define HALF_DUPLEX 1
463 #define FULL_DUPLEX 2
465 #define PHY_FORCE_TIME 20
467 #define ADVERTISE_10_HALF 0x0001
468 #define ADVERTISE_10_FULL 0x0002
469 #define ADVERTISE_100_HALF 0x0004
470 #define ADVERTISE_100_FULL 0x0008
471 #define ADVERTISE_1000_HALF 0x0010 /* Not used, just FYI */
472 #define ADVERTISE_1000_FULL 0x0020
474 /* 1000/H is not supported, nor spec-compliant. */
475 #define E1000_ALL_SPEED_DUPLEX (ADVERTISE_10_HALF | ADVERTISE_10_FULL | \
476 ADVERTISE_100_HALF | ADVERTISE_100_FULL | \
478 #define E1000_ALL_NOT_GIG (ADVERTISE_10_HALF | ADVERTISE_10_FULL | \
479 ADVERTISE_100_HALF | ADVERTISE_100_FULL)
480 #define E1000_ALL_100_SPEED (ADVERTISE_100_HALF | ADVERTISE_100_FULL)
481 #define E1000_ALL_10_SPEED (ADVERTISE_10_HALF | ADVERTISE_10_FULL)
482 #define E1000_ALL_FULL_DUPLEX (ADVERTISE_10_FULL | ADVERTISE_100_FULL | \
484 #define E1000_ALL_HALF_DUPLEX (ADVERTISE_10_HALF | ADVERTISE_100_HALF)
486 #define AUTONEG_ADVERTISE_SPEED_DEFAULT E1000_ALL_SPEED_DUPLEX
489 #define E1000_LEDCTL_LED0_MODE_MASK 0x0000000F
490 #define E1000_LEDCTL_LED0_MODE_SHIFT 0
491 #define E1000_LEDCTL_LED0_BLINK_RATE 0x00000020
492 #define E1000_LEDCTL_LED0_IVRT 0x00000040
493 #define E1000_LEDCTL_LED0_BLINK 0x00000080
494 #define E1000_LEDCTL_LED1_MODE_MASK 0x00000F00
495 #define E1000_LEDCTL_LED1_MODE_SHIFT 8
496 #define E1000_LEDCTL_LED1_BLINK_RATE 0x00002000
497 #define E1000_LEDCTL_LED1_IVRT 0x00004000
498 #define E1000_LEDCTL_LED1_BLINK 0x00008000
499 #define E1000_LEDCTL_LED2_MODE_MASK 0x000F0000
500 #define E1000_LEDCTL_LED2_MODE_SHIFT 16
501 #define E1000_LEDCTL_LED2_BLINK_RATE 0x00200000
502 #define E1000_LEDCTL_LED2_IVRT 0x00400000
503 #define E1000_LEDCTL_LED2_BLINK 0x00800000
504 #define E1000_LEDCTL_LED3_MODE_MASK 0x0F000000
505 #define E1000_LEDCTL_LED3_MODE_SHIFT 24
506 #define E1000_LEDCTL_LED3_BLINK_RATE 0x20000000
507 #define E1000_LEDCTL_LED3_IVRT 0x40000000
508 #define E1000_LEDCTL_LED3_BLINK 0x80000000
510 #define E1000_LEDCTL_MODE_LINK_10_1000 0x0
511 #define E1000_LEDCTL_MODE_LINK_100_1000 0x1
512 #define E1000_LEDCTL_MODE_LINK_UP 0x2
513 #define E1000_LEDCTL_MODE_ACTIVITY 0x3
514 #define E1000_LEDCTL_MODE_LINK_ACTIVITY 0x4
515 #define E1000_LEDCTL_MODE_LINK_10 0x5
516 #define E1000_LEDCTL_MODE_LINK_100 0x6
517 #define E1000_LEDCTL_MODE_LINK_1000 0x7
518 #define E1000_LEDCTL_MODE_PCIX_MODE 0x8
519 #define E1000_LEDCTL_MODE_FULL_DUPLEX 0x9
520 #define E1000_LEDCTL_MODE_COLLISION 0xA
521 #define E1000_LEDCTL_MODE_BUS_SPEED 0xB
522 #define E1000_LEDCTL_MODE_BUS_SIZE 0xC
523 #define E1000_LEDCTL_MODE_PAUSED 0xD
524 #define E1000_LEDCTL_MODE_LED_ON 0xE
525 #define E1000_LEDCTL_MODE_LED_OFF 0xF
527 /* Transmit Descriptor bit definitions */
528 #define E1000_TXD_DTYP_D 0x00100000 /* Data Descriptor */
529 #define E1000_TXD_DTYP_C 0x00000000 /* Context Descriptor */
530 #define E1000_TXD_POPTS_SHIFT 8 /* POPTS shift */
531 #define E1000_TXD_POPTS_IXSM 0x01 /* Insert IP checksum */
532 #define E1000_TXD_POPTS_TXSM 0x02 /* Insert TCP/UDP checksum */
533 #define E1000_TXD_CMD_EOP 0x01000000 /* End of Packet */
534 #define E1000_TXD_CMD_IFCS 0x02000000 /* Insert FCS (Ethernet CRC) */
535 #define E1000_TXD_CMD_IC 0x04000000 /* Insert Checksum */
536 #define E1000_TXD_CMD_RS 0x08000000 /* Report Status */
537 #define E1000_TXD_CMD_RPS 0x10000000 /* Report Packet Sent */
538 #define E1000_TXD_CMD_DEXT 0x20000000 /* Descriptor extension (0 = legacy) */
539 #define E1000_TXD_CMD_VLE 0x40000000 /* Add VLAN tag */
540 #define E1000_TXD_CMD_IDE 0x80000000 /* Enable Tidv register */
541 #define E1000_TXD_STAT_DD 0x00000001 /* Descriptor Done */
542 #define E1000_TXD_STAT_EC 0x00000002 /* Excess Collisions */
543 #define E1000_TXD_STAT_LC 0x00000004 /* Late Collisions */
544 #define E1000_TXD_STAT_TU 0x00000008 /* Transmit underrun */
545 #define E1000_TXD_CMD_TCP 0x01000000 /* TCP packet */
546 #define E1000_TXD_CMD_IP 0x02000000 /* IP packet */
547 #define E1000_TXD_CMD_TSE 0x04000000 /* TCP Seg enable */
548 #define E1000_TXD_STAT_TC 0x00000004 /* Tx Underrun */
549 /* Extended desc bits for Linksec and timesync */
551 /* Transmit Control */
552 #define E1000_TCTL_RST 0x00000001 /* software reset */
553 #define E1000_TCTL_EN 0x00000002 /* enable tx */
554 #define E1000_TCTL_BCE 0x00000004 /* busy check enable */
555 #define E1000_TCTL_PSP 0x00000008 /* pad short packets */
556 #define E1000_TCTL_CT 0x00000ff0 /* collision threshold */
557 #define E1000_TCTL_COLD 0x003ff000 /* collision distance */
558 #define E1000_TCTL_SWXOFF 0x00400000 /* SW Xoff transmission */
559 #define E1000_TCTL_PBE 0x00800000 /* Packet Burst Enable */
560 #define E1000_TCTL_RTLC 0x01000000 /* Re-transmit on late collision */
561 #define E1000_TCTL_NRTU 0x02000000 /* No Re-transmit on underrun */
562 #define E1000_TCTL_MULR 0x10000000 /* Multiple request support */
564 /* Transmit Arbitration Count */
565 #define E1000_TARC0_ENABLE 0x00000400 /* Enable Tx Queue 0 */
568 #define E1000_SCTL_DISABLE_SERDES_LOOPBACK 0x0400
570 /* Receive Checksum Control */
571 #define E1000_RXCSUM_PCSS_MASK 0x000000FF /* Packet Checksum Start */
572 #define E1000_RXCSUM_IPOFL 0x00000100 /* IPv4 checksum offload */
573 #define E1000_RXCSUM_TUOFL 0x00000200 /* TCP / UDP checksum offload */
574 #define E1000_RXCSUM_IPV6OFL 0x00000400 /* IPv6 checksum offload */
575 #define E1000_RXCSUM_CRCOFL 0x00000800 /* CRC32 offload enable */
576 #define E1000_RXCSUM_IPPCSE 0x00001000 /* IP payload checksum enable */
577 #define E1000_RXCSUM_PCSD 0x00002000 /* packet checksum disabled */
579 /* Header split receive */
580 #define E1000_RFCTL_ISCSI_DIS 0x00000001
581 #define E1000_RFCTL_ISCSI_DWC_MASK 0x0000003E
582 #define E1000_RFCTL_ISCSI_DWC_SHIFT 1
583 #define E1000_RFCTL_NFSW_DIS 0x00000040
584 #define E1000_RFCTL_NFSR_DIS 0x00000080
585 #define E1000_RFCTL_NFS_VER_MASK 0x00000300
586 #define E1000_RFCTL_NFS_VER_SHIFT 8
587 #define E1000_RFCTL_IPV6_DIS 0x00000400
588 #define E1000_RFCTL_IPV6_XSUM_DIS 0x00000800
589 #define E1000_RFCTL_ACK_DIS 0x00001000
590 #define E1000_RFCTL_ACKD_DIS 0x00002000
591 #define E1000_RFCTL_IPFRSP_DIS 0x00004000
592 #define E1000_RFCTL_EXTEN 0x00008000
593 #define E1000_RFCTL_IPV6_EX_DIS 0x00010000
594 #define E1000_RFCTL_NEW_IPV6_EXT_DIS 0x00020000
595 #define E1000_RFCTL_LEF 0x00040000
597 /* Collision related configuration parameters */
598 #define E1000_COLLISION_THRESHOLD 15
599 #define E1000_CT_SHIFT 4
600 #define E1000_COLLISION_DISTANCE 63
601 #define E1000_COLD_SHIFT 12
603 /* Default values for the transmit IPG register */
604 #define DEFAULT_82542_TIPG_IPGT 10
605 #define DEFAULT_82543_TIPG_IPGT_FIBER 9
606 #define DEFAULT_82543_TIPG_IPGT_COPPER 8
608 #define E1000_TIPG_IPGT_MASK 0x000003FF
609 #define E1000_TIPG_IPGR1_MASK 0x000FFC00
610 #define E1000_TIPG_IPGR2_MASK 0x3FF00000
612 #define DEFAULT_82542_TIPG_IPGR1 2
613 #define DEFAULT_82543_TIPG_IPGR1 8
614 #define E1000_TIPG_IPGR1_SHIFT 10
616 #define DEFAULT_82542_TIPG_IPGR2 10
617 #define DEFAULT_82543_TIPG_IPGR2 6
618 #define DEFAULT_80003ES2LAN_TIPG_IPGR2 7
619 #define E1000_TIPG_IPGR2_SHIFT 20
621 /* Ethertype field values */
622 #define ETHERNET_IEEE_VLAN_TYPE 0x8100 /* 802.3ac packet */
624 #define ETHERNET_FCS_SIZE 4
625 #define MAX_JUMBO_FRAME_SIZE 0x3F00
627 /* Extended Configuration Control and Size */
628 #define E1000_EXTCNF_CTRL_MDIO_SW_OWNERSHIP 0x00000020
629 #define E1000_EXTCNF_CTRL_LCD_WRITE_ENABLE 0x00000001
630 #define E1000_EXTCNF_CTRL_SWFLAG 0x00000020
631 #define E1000_EXTCNF_SIZE_EXT_PCIE_LENGTH_MASK 0x00FF0000
632 #define E1000_EXTCNF_SIZE_EXT_PCIE_LENGTH_SHIFT 16
633 #define E1000_EXTCNF_CTRL_EXT_CNF_POINTER_MASK 0x0FFF0000
634 #define E1000_EXTCNF_CTRL_EXT_CNF_POINTER_SHIFT 16
636 #define E1000_PHY_CTRL_SPD_EN 0x00000001
637 #define E1000_PHY_CTRL_D0A_LPLU 0x00000002
638 #define E1000_PHY_CTRL_NOND0A_LPLU 0x00000004
639 #define E1000_PHY_CTRL_NOND0A_GBE_DISABLE 0x00000008
640 #define E1000_PHY_CTRL_GBE_DISABLE 0x00000040
642 #define E1000_KABGTXD_BGSQLBIAS 0x00050000
645 #define E1000_PBA_6K 0x0006 /* 6KB */
646 #define E1000_PBA_8K 0x0008 /* 8KB */
647 #define E1000_PBA_10K 0x000A /* 10KB */
648 #define E1000_PBA_12K 0x000C /* 12KB */
649 #define E1000_PBA_14K 0x000E /* 14KB */
650 #define E1000_PBA_16K 0x0010 /* 16KB */
651 #define E1000_PBA_18K 0x0012
652 #define E1000_PBA_20K 0x0014
653 #define E1000_PBA_22K 0x0016
654 #define E1000_PBA_24K 0x0018
655 #define E1000_PBA_26K 0x001A
656 #define E1000_PBA_30K 0x001E
657 #define E1000_PBA_32K 0x0020
658 #define E1000_PBA_34K 0x0022
659 #define E1000_PBA_35K 0x0023
660 #define E1000_PBA_38K 0x0026
661 #define E1000_PBA_40K 0x0028
662 #define E1000_PBA_48K 0x0030 /* 48KB */
663 #define E1000_PBA_64K 0x0040 /* 64KB */
665 #define E1000_PBS_16K E1000_PBA_16K
666 #define E1000_PBS_24K E1000_PBA_24K
672 #define MIN_NUM_XMITS 1000
674 /* SW Semaphore Register */
675 #define E1000_SWSM_SMBI 0x00000001 /* Driver Semaphore bit */
676 #define E1000_SWSM_SWESMBI 0x00000002 /* FW Semaphore bit */
677 #define E1000_SWSM_WMNG 0x00000004 /* Wake MNG Clock */
678 #define E1000_SWSM_DRV_LOAD 0x00000008 /* Driver Loaded Bit */
680 #define E1000_SWSM2_LOCK 0x00000002 /* Secondary driver semaphore bit */
682 /* Interrupt Cause Read */
683 #define E1000_ICR_TXDW 0x00000001 /* Transmit desc written back */
684 #define E1000_ICR_TXQE 0x00000002 /* Transmit Queue empty */
685 #define E1000_ICR_LSC 0x00000004 /* Link Status Change */
686 #define E1000_ICR_RXSEQ 0x00000008 /* rx sequence error */
687 #define E1000_ICR_RXDMT0 0x00000010 /* rx desc min. threshold (0) */
688 #define E1000_ICR_RXO 0x00000040 /* rx overrun */
689 #define E1000_ICR_RXT0 0x00000080 /* rx timer intr (ring 0) */
690 #define E1000_ICR_VMMB 0x00000100 /* VM MB event */
691 #define E1000_ICR_MDAC 0x00000200 /* MDIO access complete */
692 #define E1000_ICR_RXCFG 0x00000400 /* Rx /c/ ordered set */
693 #define E1000_ICR_GPI_EN0 0x00000800 /* GP Int 0 */
694 #define E1000_ICR_GPI_EN1 0x00001000 /* GP Int 1 */
695 #define E1000_ICR_GPI_EN2 0x00002000 /* GP Int 2 */
696 #define E1000_ICR_GPI_EN3 0x00004000 /* GP Int 3 */
697 #define E1000_ICR_TXD_LOW 0x00008000
698 #define E1000_ICR_SRPD 0x00010000
699 #define E1000_ICR_ACK 0x00020000 /* Receive Ack frame */
700 #define E1000_ICR_MNG 0x00040000 /* Manageability event */
701 #define E1000_ICR_DOCK 0x00080000 /* Dock/Undock */
702 #define E1000_ICR_INT_ASSERTED 0x80000000 /* If this bit asserted, the driver
703 * should claim the interrupt */
704 #define E1000_ICR_RXD_FIFO_PAR0 0x00100000 /* Q0 Rx desc FIFO parity error */
705 #define E1000_ICR_TXD_FIFO_PAR0 0x00200000 /* Q0 Tx desc FIFO parity error */
706 #define E1000_ICR_HOST_ARB_PAR 0x00400000 /* host arb read buffer parity err */
707 #define E1000_ICR_PB_PAR 0x00800000 /* packet buffer parity error */
708 #define E1000_ICR_RXD_FIFO_PAR1 0x01000000 /* Q1 Rx desc FIFO parity error */
709 #define E1000_ICR_TXD_FIFO_PAR1 0x02000000 /* Q1 Tx desc FIFO parity error */
710 #define E1000_ICR_ALL_PARITY 0x03F00000 /* all parity error bits */
711 #define E1000_ICR_DSW 0x00000020 /* FW changed the status of DISSW
713 #define E1000_ICR_PHYINT 0x00001000 /* LAN connected device generates
715 #define E1000_ICR_DOUTSYNC 0x10000000 /* NIC DMA out of sync */
716 #define E1000_ICR_EPRST 0x00100000 /* ME hardware reset occurs */
720 * This defines the bits that are set in the Interrupt Mask
721 * Set/Read Register. Each bit is documented below:
722 * o RXDMT0 = Receive Descriptor Minimum Threshold hit (ring 0)
723 * o RXSEQ = Receive Sequence Error
725 #define POLL_IMS_ENABLE_MASK ( \
730 * This defines the bits that are set in the Interrupt Mask
731 * Set/Read Register. Each bit is documented below:
732 * o RXT0 = Receiver Timer Interrupt (ring 0)
733 * o TXDW = Transmit Descriptor Written Back
734 * o RXDMT0 = Receive Descriptor Minimum Threshold hit (ring 0)
735 * o RXSEQ = Receive Sequence Error
736 * o LSC = Link Status Change
738 #define IMS_ENABLE_MASK ( \
745 /* Interrupt Mask Set */
746 #define E1000_IMS_TXDW E1000_ICR_TXDW /* Tx desc written back */
747 #define E1000_IMS_TXQE E1000_ICR_TXQE /* Transmit Queue empty */
748 #define E1000_IMS_LSC E1000_ICR_LSC /* Link Status Change */
749 #define E1000_IMS_VMMB E1000_ICR_VMMB /* Mail box activity */
750 #define E1000_IMS_RXSEQ E1000_ICR_RXSEQ /* rx sequence error */
751 #define E1000_IMS_RXDMT0 E1000_ICR_RXDMT0 /* rx desc min. threshold */
752 #define E1000_IMS_RXO E1000_ICR_RXO /* rx overrun */
753 #define E1000_IMS_RXT0 E1000_ICR_RXT0 /* rx timer intr */
754 #define E1000_IMS_MDAC E1000_ICR_MDAC /* MDIO access complete */
755 #define E1000_IMS_RXCFG E1000_ICR_RXCFG /* Rx /c/ ordered set */
756 #define E1000_IMS_GPI_EN0 E1000_ICR_GPI_EN0 /* GP Int 0 */
757 #define E1000_IMS_GPI_EN1 E1000_ICR_GPI_EN1 /* GP Int 1 */
758 #define E1000_IMS_GPI_EN2 E1000_ICR_GPI_EN2 /* GP Int 2 */
759 #define E1000_IMS_GPI_EN3 E1000_ICR_GPI_EN3 /* GP Int 3 */
760 #define E1000_IMS_TXD_LOW E1000_ICR_TXD_LOW
761 #define E1000_IMS_SRPD E1000_ICR_SRPD
762 #define E1000_IMS_ACK E1000_ICR_ACK /* Receive Ack frame */
763 #define E1000_IMS_MNG E1000_ICR_MNG /* Manageability event */
764 #define E1000_IMS_DOCK E1000_ICR_DOCK /* Dock/Undock */
765 #define E1000_IMS_RXD_FIFO_PAR0 E1000_ICR_RXD_FIFO_PAR0 /* Q0 Rx desc FIFO
767 #define E1000_IMS_TXD_FIFO_PAR0 E1000_ICR_TXD_FIFO_PAR0 /* Q0 Tx desc FIFO
769 #define E1000_IMS_HOST_ARB_PAR E1000_ICR_HOST_ARB_PAR /* host arb read buffer
771 #define E1000_IMS_PB_PAR E1000_ICR_PB_PAR /* packet buffer parity
773 #define E1000_IMS_RXD_FIFO_PAR1 E1000_ICR_RXD_FIFO_PAR1 /* Q1 Rx desc FIFO
775 #define E1000_IMS_TXD_FIFO_PAR1 E1000_ICR_TXD_FIFO_PAR1 /* Q1 Tx desc FIFO
777 #define E1000_IMS_DSW E1000_ICR_DSW
778 #define E1000_IMS_PHYINT E1000_ICR_PHYINT
779 #define E1000_IMS_DOUTSYNC E1000_ICR_DOUTSYNC /* NIC DMA out of sync */
780 #define E1000_IMS_EPRST E1000_ICR_EPRST
782 /* Interrupt Cause Set */
783 #define E1000_ICS_TXDW E1000_ICR_TXDW /* Tx desc written back */
784 #define E1000_ICS_TXQE E1000_ICR_TXQE /* Transmit Queue empty */
785 #define E1000_ICS_LSC E1000_ICR_LSC /* Link Status Change */
786 #define E1000_ICS_RXSEQ E1000_ICR_RXSEQ /* rx sequence error */
787 #define E1000_ICS_RXDMT0 E1000_ICR_RXDMT0 /* rx desc min. threshold */
788 #define E1000_ICS_RXO E1000_ICR_RXO /* rx overrun */
789 #define E1000_ICS_RXT0 E1000_ICR_RXT0 /* rx timer intr */
790 #define E1000_ICS_MDAC E1000_ICR_MDAC /* MDIO access complete */
791 #define E1000_ICS_RXCFG E1000_ICR_RXCFG /* Rx /c/ ordered set */
792 #define E1000_ICS_GPI_EN0 E1000_ICR_GPI_EN0 /* GP Int 0 */
793 #define E1000_ICS_GPI_EN1 E1000_ICR_GPI_EN1 /* GP Int 1 */
794 #define E1000_ICS_GPI_EN2 E1000_ICR_GPI_EN2 /* GP Int 2 */
795 #define E1000_ICS_GPI_EN3 E1000_ICR_GPI_EN3 /* GP Int 3 */
796 #define E1000_ICS_TXD_LOW E1000_ICR_TXD_LOW
797 #define E1000_ICS_SRPD E1000_ICR_SRPD
798 #define E1000_ICS_ACK E1000_ICR_ACK /* Receive Ack frame */
799 #define E1000_ICS_MNG E1000_ICR_MNG /* Manageability event */
800 #define E1000_ICS_DOCK E1000_ICR_DOCK /* Dock/Undock */
801 #define E1000_ICS_RXD_FIFO_PAR0 E1000_ICR_RXD_FIFO_PAR0 /* Q0 Rx desc FIFO
803 #define E1000_ICS_TXD_FIFO_PAR0 E1000_ICR_TXD_FIFO_PAR0 /* Q0 Tx desc FIFO
805 #define E1000_ICS_HOST_ARB_PAR E1000_ICR_HOST_ARB_PAR /* host arb read buffer
807 #define E1000_ICS_PB_PAR E1000_ICR_PB_PAR /* packet buffer parity
809 #define E1000_ICS_RXD_FIFO_PAR1 E1000_ICR_RXD_FIFO_PAR1 /* Q1 Rx desc FIFO
811 #define E1000_ICS_TXD_FIFO_PAR1 E1000_ICR_TXD_FIFO_PAR1 /* Q1 Tx desc FIFO
813 #define E1000_ICS_DSW E1000_ICR_DSW
814 #define E1000_ICS_DOUTSYNC E1000_ICR_DOUTSYNC /* NIC DMA out of sync */
815 #define E1000_ICS_PHYINT E1000_ICR_PHYINT
816 #define E1000_ICS_EPRST E1000_ICR_EPRST
818 /* Transmit Descriptor Control */
819 #define E1000_TXDCTL_PTHRESH 0x0000003F /* TXDCTL Prefetch Threshold */
820 #define E1000_TXDCTL_HTHRESH 0x00003F00 /* TXDCTL Host Threshold */
821 #define E1000_TXDCTL_WTHRESH 0x003F0000 /* TXDCTL Writeback Threshold */
822 #define E1000_TXDCTL_GRAN 0x01000000 /* TXDCTL Granularity */
823 #define E1000_TXDCTL_LWTHRESH 0xFE000000 /* TXDCTL Low Threshold */
824 #define E1000_TXDCTL_FULL_TX_DESC_WB 0x01010000 /* GRAN=1, WTHRESH=1 */
825 #define E1000_TXDCTL_MAX_TX_DESC_PREFETCH 0x0100001F /* GRAN=1, PTHRESH=31 */
826 /* Enable the counting of descriptors still to be processed. */
827 #define E1000_TXDCTL_COUNT_DESC 0x00400000
829 /* Flow Control Constants */
830 #define FLOW_CONTROL_ADDRESS_LOW 0x00C28001
831 #define FLOW_CONTROL_ADDRESS_HIGH 0x00000100
832 #define FLOW_CONTROL_TYPE 0x8808
834 /* 802.1q VLAN Packet Size */
835 #define VLAN_TAG_SIZE 4 /* 802.3ac tag (not DMA'd) */
836 #define E1000_VLAN_FILTER_TBL_SIZE 128 /* VLAN Filter Table (4096 bits) */
838 /* Receive Address */
840 * Number of high/low register pairs in the RAR. The RAR (Receive Address
841 * Registers) holds the directed and multicast addresses that we monitor.
842 * Technically, we have 16 spots. However, we reserve one of these spots
843 * (RAR[15]) for our directed address used by controllers with
844 * manageability enabled, allowing us room for 15 multicast addresses.
846 #define E1000_RAR_ENTRIES 15
847 #define E1000_RAH_AV 0x80000000 /* Receive descriptor valid */
848 #define E1000_RAL_MAC_ADDR_LEN 4
849 #define E1000_RAH_MAC_ADDR_LEN 2
850 #define E1000_RAH_POOL_MASK 0x03FC0000
851 #define E1000_RAH_POOL_1 0x00040000
854 #define E1000_SUCCESS 0
855 #define E1000_ERR_NVM 1
856 #define E1000_ERR_PHY 2
857 #define E1000_ERR_CONFIG 3
858 #define E1000_ERR_PARAM 4
859 #define E1000_ERR_MAC_INIT 5
860 #define E1000_ERR_PHY_TYPE 6
861 #define E1000_ERR_RESET 9
862 #define E1000_ERR_MASTER_REQUESTS_PENDING 10
863 #define E1000_ERR_HOST_INTERFACE_COMMAND 11
864 #define E1000_BLK_PHY_RESET 12
865 #define E1000_ERR_SWFW_SYNC 13
866 #define E1000_NOT_IMPLEMENTED 14
867 #define E1000_ERR_MBX 15
869 /* Loop limit on how long we wait for auto-negotiation to complete */
870 #define FIBER_LINK_UP_LIMIT 50
871 #define COPPER_LINK_UP_LIMIT 10
872 #define PHY_AUTO_NEG_LIMIT 45
873 #define PHY_FORCE_LIMIT 20
874 /* Number of 100 microseconds we wait for PCI Express master disable */
875 #define MASTER_DISABLE_TIMEOUT 800
876 /* Number of milliseconds we wait for PHY configuration done after MAC reset */
877 #define PHY_CFG_TIMEOUT 100
878 /* Number of 2 milliseconds we wait for acquiring MDIO ownership. */
879 #define MDIO_OWNERSHIP_TIMEOUT 10
880 /* Number of milliseconds for NVM auto read done after MAC reset. */
881 #define AUTO_READ_DONE_TIMEOUT 10
884 #define E1000_FCRTH_RTH 0x0000FFF8 /* Mask Bits[15:3] for RTH */
885 #define E1000_FCRTH_XFCE 0x80000000 /* External Flow Control Enable */
886 #define E1000_FCRTL_RTL 0x0000FFF8 /* Mask Bits[15:3] for RTL */
887 #define E1000_FCRTL_XONE 0x80000000 /* Enable XON frame transmission */
889 /* Transmit Configuration Word */
890 #define E1000_TXCW_FD 0x00000020 /* TXCW full duplex */
891 #define E1000_TXCW_HD 0x00000040 /* TXCW half duplex */
892 #define E1000_TXCW_PAUSE 0x00000080 /* TXCW sym pause request */
893 #define E1000_TXCW_ASM_DIR 0x00000100 /* TXCW astm pause direction */
894 #define E1000_TXCW_PAUSE_MASK 0x00000180 /* TXCW pause request mask */
895 #define E1000_TXCW_RF 0x00003000 /* TXCW remote fault */
896 #define E1000_TXCW_NP 0x00008000 /* TXCW next page */
897 #define E1000_TXCW_CW 0x0000ffff /* TxConfigWord mask */
898 #define E1000_TXCW_TXC 0x40000000 /* Transmit Config control */
899 #define E1000_TXCW_ANE 0x80000000 /* Auto-neg enable */
901 /* Receive Configuration Word */
902 #define E1000_RXCW_CW 0x0000ffff /* RxConfigWord mask */
903 #define E1000_RXCW_NC 0x04000000 /* Receive config no carrier */
904 #define E1000_RXCW_IV 0x08000000 /* Receive config invalid */
905 #define E1000_RXCW_CC 0x10000000 /* Receive config change */
906 #define E1000_RXCW_C 0x20000000 /* Receive config */
907 #define E1000_RXCW_SYNCH 0x40000000 /* Receive config synch */
908 #define E1000_RXCW_ANC 0x80000000 /* Auto-neg complete */
910 /* PCI Express Control */
911 #define E1000_GCR_RXD_NO_SNOOP 0x00000001
912 #define E1000_GCR_RXDSCW_NO_SNOOP 0x00000002
913 #define E1000_GCR_RXDSCR_NO_SNOOP 0x00000004
914 #define E1000_GCR_TXD_NO_SNOOP 0x00000008
915 #define E1000_GCR_TXDSCW_NO_SNOOP 0x00000010
916 #define E1000_GCR_TXDSCR_NO_SNOOP 0x00000020
918 #define PCIE_NO_SNOOP_ALL (E1000_GCR_RXD_NO_SNOOP | \
919 E1000_GCR_RXDSCW_NO_SNOOP | \
920 E1000_GCR_RXDSCR_NO_SNOOP | \
921 E1000_GCR_TXD_NO_SNOOP | \
922 E1000_GCR_TXDSCW_NO_SNOOP | \
923 E1000_GCR_TXDSCR_NO_SNOOP)
925 /* PHY Control Register */
926 #define MII_CR_SPEED_SELECT_MSB 0x0040 /* bits 6,13: 10=1000, 01=100, 00=10 */
927 #define MII_CR_COLL_TEST_ENABLE 0x0080 /* Collision test enable */
928 #define MII_CR_FULL_DUPLEX 0x0100 /* FDX =1, half duplex =0 */
929 #define MII_CR_RESTART_AUTO_NEG 0x0200 /* Restart auto negotiation */
930 #define MII_CR_ISOLATE 0x0400 /* Isolate PHY from MII */
931 #define MII_CR_POWER_DOWN 0x0800 /* Power down */
932 #define MII_CR_AUTO_NEG_EN 0x1000 /* Auto Neg Enable */
933 #define MII_CR_SPEED_SELECT_LSB 0x2000 /* bits 6,13: 10=1000, 01=100, 00=10 */
934 #define MII_CR_LOOPBACK 0x4000 /* 0 = normal, 1 = loopback */
935 #define MII_CR_RESET 0x8000 /* 0 = normal, 1 = PHY reset */
936 #define MII_CR_SPEED_1000 0x0040
937 #define MII_CR_SPEED_100 0x2000
938 #define MII_CR_SPEED_10 0x0000
940 /* PHY Status Register */
941 #define MII_SR_EXTENDED_CAPS 0x0001 /* Extended register capabilities */
942 #define MII_SR_JABBER_DETECT 0x0002 /* Jabber Detected */
943 #define MII_SR_LINK_STATUS 0x0004 /* Link Status 1 = link */
944 #define MII_SR_AUTONEG_CAPS 0x0008 /* Auto Neg Capable */
945 #define MII_SR_REMOTE_FAULT 0x0010 /* Remote Fault Detect */
946 #define MII_SR_AUTONEG_COMPLETE 0x0020 /* Auto Neg Complete */
947 #define MII_SR_PREAMBLE_SUPPRESS 0x0040 /* Preamble may be suppressed */
948 #define MII_SR_EXTENDED_STATUS 0x0100 /* Ext. status info in Reg 0x0F */
949 #define MII_SR_100T2_HD_CAPS 0x0200 /* 100T2 Half Duplex Capable */
950 #define MII_SR_100T2_FD_CAPS 0x0400 /* 100T2 Full Duplex Capable */
951 #define MII_SR_10T_HD_CAPS 0x0800 /* 10T Half Duplex Capable */
952 #define MII_SR_10T_FD_CAPS 0x1000 /* 10T Full Duplex Capable */
953 #define MII_SR_100X_HD_CAPS 0x2000 /* 100X Half Duplex Capable */
954 #define MII_SR_100X_FD_CAPS 0x4000 /* 100X Full Duplex Capable */
955 #define MII_SR_100T4_CAPS 0x8000 /* 100T4 Capable */
957 /* Autoneg Advertisement Register */
958 #define NWAY_AR_SELECTOR_FIELD 0x0001 /* indicates IEEE 802.3 CSMA/CD */
959 #define NWAY_AR_10T_HD_CAPS 0x0020 /* 10T Half Duplex Capable */
960 #define NWAY_AR_10T_FD_CAPS 0x0040 /* 10T Full Duplex Capable */
961 #define NWAY_AR_100TX_HD_CAPS 0x0080 /* 100TX Half Duplex Capable */
962 #define NWAY_AR_100TX_FD_CAPS 0x0100 /* 100TX Full Duplex Capable */
963 #define NWAY_AR_100T4_CAPS 0x0200 /* 100T4 Capable */
964 #define NWAY_AR_PAUSE 0x0400 /* Pause operation desired */
965 #define NWAY_AR_ASM_DIR 0x0800 /* Asymmetric Pause Direction bit */
966 #define NWAY_AR_REMOTE_FAULT 0x2000 /* Remote Fault detected */
967 #define NWAY_AR_NEXT_PAGE 0x8000 /* Next Page ability supported */
969 /* Link Partner Ability Register (Base Page) */
970 #define NWAY_LPAR_SELECTOR_FIELD 0x0000 /* LP protocol selector field */
971 #define NWAY_LPAR_10T_HD_CAPS 0x0020 /* LP is 10T Half Duplex Capable */
972 #define NWAY_LPAR_10T_FD_CAPS 0x0040 /* LP is 10T Full Duplex Capable */
973 #define NWAY_LPAR_100TX_HD_CAPS 0x0080 /* LP is 100TX Half Duplex Capable */
974 #define NWAY_LPAR_100TX_FD_CAPS 0x0100 /* LP is 100TX Full Duplex Capable */
975 #define NWAY_LPAR_100T4_CAPS 0x0200 /* LP is 100T4 Capable */
976 #define NWAY_LPAR_PAUSE 0x0400 /* LP Pause operation desired */
977 #define NWAY_LPAR_ASM_DIR 0x0800 /* LP Asymmetric Pause Direction bit */
978 #define NWAY_LPAR_REMOTE_FAULT 0x2000 /* LP has detected Remote Fault */
979 #define NWAY_LPAR_ACKNOWLEDGE 0x4000 /* LP has rx'd link code word */
980 #define NWAY_LPAR_NEXT_PAGE 0x8000 /* Next Page ability supported */
982 /* Autoneg Expansion Register */
983 #define NWAY_ER_LP_NWAY_CAPS 0x0001 /* LP has Auto Neg Capability */
984 #define NWAY_ER_PAGE_RXD 0x0002 /* LP is 10T Half Duplex Capable */
985 #define NWAY_ER_NEXT_PAGE_CAPS 0x0004 /* LP is 10T Full Duplex Capable */
986 #define NWAY_ER_LP_NEXT_PAGE_CAPS 0x0008 /* LP is 100TX Half Duplex Capable */
987 #define NWAY_ER_PAR_DETECT_FAULT 0x0010 /* LP is 100TX Full Duplex Capable */
989 /* 1000BASE-T Control Register */
990 #define CR_1000T_ASYM_PAUSE 0x0080 /* Advertise asymmetric pause bit */
991 #define CR_1000T_HD_CAPS 0x0100 /* Advertise 1000T HD capability */
992 #define CR_1000T_FD_CAPS 0x0200 /* Advertise 1000T FD capability */
993 #define CR_1000T_REPEATER_DTE 0x0400 /* 1=Repeater/switch device port */
995 #define CR_1000T_MS_VALUE 0x0800 /* 1=Configure PHY as Master */
996 /* 0=Configure PHY as Slave */
997 #define CR_1000T_MS_ENABLE 0x1000 /* 1=Master/Slave manual config value */
998 /* 0=Automatic Master/Slave config */
999 #define CR_1000T_TEST_MODE_NORMAL 0x0000 /* Normal Operation */
1000 #define CR_1000T_TEST_MODE_1 0x2000 /* Transmit Waveform test */
1001 #define CR_1000T_TEST_MODE_2 0x4000 /* Master Transmit Jitter test */
1002 #define CR_1000T_TEST_MODE_3 0x6000 /* Slave Transmit Jitter test */
1003 #define CR_1000T_TEST_MODE_4 0x8000 /* Transmitter Distortion test */
1005 /* 1000BASE-T Status Register */
1006 #define SR_1000T_IDLE_ERROR_CNT 0x00FF /* Num idle errors since last read */
1007 #define SR_1000T_ASYM_PAUSE_DIR 0x0100 /* LP asymmetric pause direction bit */
1008 #define SR_1000T_LP_HD_CAPS 0x0400 /* LP is 1000T HD capable */
1009 #define SR_1000T_LP_FD_CAPS 0x0800 /* LP is 1000T FD capable */
1010 #define SR_1000T_REMOTE_RX_STATUS 0x1000 /* Remote receiver OK */
1011 #define SR_1000T_LOCAL_RX_STATUS 0x2000 /* Local receiver OK */
1012 #define SR_1000T_MS_CONFIG_RES 0x4000 /* 1=Local Tx is Master, 0=Slave */
1013 #define SR_1000T_MS_CONFIG_FAULT 0x8000 /* Master/Slave config fault */
1015 #define SR_1000T_PHY_EXCESSIVE_IDLE_ERR_COUNT 5
1017 /* PHY 1000 MII Register/Bit Definitions */
1018 /* PHY Registers defined by IEEE */
1019 #define PHY_CONTROL 0x00 /* Control Register */
1020 #define PHY_STATUS 0x01 /* Status Register */
1021 #define PHY_ID1 0x02 /* Phy Id Reg (word 1) */
1022 #define PHY_ID2 0x03 /* Phy Id Reg (word 2) */
1023 #define PHY_AUTONEG_ADV 0x04 /* Autoneg Advertisement */
1024 #define PHY_LP_ABILITY 0x05 /* Link Partner Ability (Base Page) */
1025 #define PHY_AUTONEG_EXP 0x06 /* Autoneg Expansion Reg */
1026 #define PHY_NEXT_PAGE_TX 0x07 /* Next Page Tx */
1027 #define PHY_LP_NEXT_PAGE 0x08 /* Link Partner Next Page */
1028 #define PHY_1000T_CTRL 0x09 /* 1000Base-T Control Reg */
1029 #define PHY_1000T_STATUS 0x0A /* 1000Base-T Status Reg */
1030 #define PHY_EXT_STATUS 0x0F /* Extended Status Reg */
1033 #define E1000_EECD_SK 0x00000001 /* NVM Clock */
1034 #define E1000_EECD_CS 0x00000002 /* NVM Chip Select */
1035 #define E1000_EECD_DI 0x00000004 /* NVM Data In */
1036 #define E1000_EECD_DO 0x00000008 /* NVM Data Out */
1037 #define E1000_EECD_FWE_MASK 0x00000030
1038 #define E1000_EECD_FWE_DIS 0x00000010 /* Disable FLASH writes */
1039 #define E1000_EECD_FWE_EN 0x00000020 /* Enable FLASH writes */
1040 #define E1000_EECD_FWE_SHIFT 4
1041 #define E1000_EECD_REQ 0x00000040 /* NVM Access Request */
1042 #define E1000_EECD_GNT 0x00000080 /* NVM Access Grant */
1043 #define E1000_EECD_PRES 0x00000100 /* NVM Present */
1044 #define E1000_EECD_SIZE 0x00000200 /* NVM Size (0=64 word 1=256 word) */
1045 /* NVM Addressing bits based on type 0=small, 1=large */
1046 #define E1000_EECD_ADDR_BITS 0x00000400
1047 #define E1000_EECD_TYPE 0x00002000 /* NVM Type (1-SPI, 0-Microwire) */
1048 #define E1000_NVM_GRANT_ATTEMPTS 1000 /* NVM # attempts to gain grant */
1049 #define E1000_EECD_AUTO_RD 0x00000200 /* NVM Auto Read done */
1050 #define E1000_EECD_SIZE_EX_MASK 0x00007800 /* NVM Size */
1051 #define E1000_EECD_SIZE_EX_SHIFT 11
1052 #define E1000_EECD_NVADDS 0x00018000 /* NVM Address Size */
1053 #define E1000_EECD_SELSHAD 0x00020000 /* Select Shadow RAM */
1054 #define E1000_EECD_INITSRAM 0x00040000 /* Initialize Shadow RAM */
1055 #define E1000_EECD_FLUPD 0x00080000 /* Update FLASH */
1056 #define E1000_EECD_AUPDEN 0x00100000 /* Enable Autonomous FLASH update */
1057 #define E1000_EECD_SHADV 0x00200000 /* Shadow RAM Data Valid */
1058 #define E1000_EECD_SEC1VAL 0x00400000 /* Sector One Valid */
1059 #define E1000_EECD_SECVAL_SHIFT 22
1060 #define E1000_EECD_SEC1VAL_VALID_MASK (E1000_EECD_AUTO_RD | E1000_EECD_PRES)
1062 #define E1000_NVM_SWDPIN0 0x0001 /* SWDPIN 0 NVM Value */
1063 #define E1000_NVM_LED_LOGIC 0x0020 /* Led Logic Word */
1064 #define E1000_NVM_RW_REG_DATA 16 /* Offset to data in NVM read/write regs */
1065 #define E1000_NVM_RW_REG_DONE 2 /* Offset to READ/WRITE done bit */
1066 #define E1000_NVM_RW_REG_START 1 /* Start operation */
1067 #define E1000_NVM_RW_ADDR_SHIFT 2 /* Shift to the address bits */
1068 #define E1000_NVM_POLL_WRITE 1 /* Flag for polling for write complete */
1069 #define E1000_NVM_POLL_READ 0 /* Flag for polling for read complete */
1070 #define E1000_FLASH_UPDATES 2000
1072 /* NVM Word Offsets */
1073 #define NVM_COMPAT 0x0003
1074 #define NVM_ID_LED_SETTINGS 0x0004
1075 #define NVM_VERSION 0x0005
1076 #define NVM_SERDES_AMPLITUDE 0x0006 /* SERDES output amplitude */
1077 #define NVM_PHY_CLASS_WORD 0x0007
1078 #define NVM_INIT_CONTROL1_REG 0x000A
1079 #define NVM_INIT_CONTROL2_REG 0x000F
1080 #define NVM_SWDEF_PINS_CTRL_PORT_1 0x0010
1081 #define NVM_INIT_CONTROL3_PORT_B 0x0014
1082 #define NVM_INIT_3GIO_3 0x001A
1083 #define NVM_SWDEF_PINS_CTRL_PORT_0 0x0020
1084 #define NVM_INIT_CONTROL3_PORT_A 0x0024
1085 #define NVM_CFG 0x0012
1086 #define NVM_FLASH_VERSION 0x0032
1087 #define NVM_ALT_MAC_ADDR_PTR 0x0037
1088 #define NVM_CHECKSUM_REG 0x003F
1090 #define E1000_NVM_CFG_DONE_PORT_0 0x40000 /* MNG config cycle done */
1091 #define E1000_NVM_CFG_DONE_PORT_1 0x80000 /* ...for second port */
1093 /* Mask bits for fields in Word 0x0f of the NVM */
1094 #define NVM_WORD0F_PAUSE_MASK 0x3000
1095 #define NVM_WORD0F_PAUSE 0x1000
1096 #define NVM_WORD0F_ASM_DIR 0x2000
1097 #define NVM_WORD0F_ANE 0x0800
1098 #define NVM_WORD0F_SWPDIO_EXT_MASK 0x00F0
1099 #define NVM_WORD0F_LPLU 0x0001
1101 /* Mask bits for fields in Word 0x1a of the NVM */
1102 #define NVM_WORD1A_ASPM_MASK 0x000C
1104 /* For checksumming, the sum of all words in the NVM should equal 0xBABA. */
1105 #define NVM_SUM 0xBABA
1107 #define NVM_MAC_ADDR_OFFSET 0
1108 #define NVM_PBA_OFFSET_0 8
1109 #define NVM_PBA_OFFSET_1 9
1110 #define NVM_RESERVED_WORD 0xFFFF
1111 #define NVM_PHY_CLASS_A 0x8000
1112 #define NVM_SERDES_AMPLITUDE_MASK 0x000F
1113 #define NVM_SIZE_MASK 0x1C00
1114 #define NVM_SIZE_SHIFT 10
1115 #define NVM_WORD_SIZE_BASE_SHIFT 6
1116 #define NVM_SWDPIO_EXT_SHIFT 4
1118 /* NVM Commands - Microwire */
1119 #define NVM_READ_OPCODE_MICROWIRE 0x6 /* NVM read opcode */
1120 #define NVM_WRITE_OPCODE_MICROWIRE 0x5 /* NVM write opcode */
1121 #define NVM_ERASE_OPCODE_MICROWIRE 0x7 /* NVM erase opcode */
1122 #define NVM_EWEN_OPCODE_MICROWIRE 0x13 /* NVM erase/write enable */
1123 #define NVM_EWDS_OPCODE_MICROWIRE 0x10 /* NVM erase/write disable */
1125 /* NVM Commands - SPI */
1126 #define NVM_MAX_RETRY_SPI 5000 /* Max wait of 5ms, for RDY signal */
1127 #define NVM_READ_OPCODE_SPI 0x03 /* NVM read opcode */
1128 #define NVM_WRITE_OPCODE_SPI 0x02 /* NVM write opcode */
1129 #define NVM_A8_OPCODE_SPI 0x08 /* opcode bit-3 = address bit-8 */
1130 #define NVM_WREN_OPCODE_SPI 0x06 /* NVM set Write Enable latch */
1131 #define NVM_WRDI_OPCODE_SPI 0x04 /* NVM reset Write Enable latch */
1132 #define NVM_RDSR_OPCODE_SPI 0x05 /* NVM read Status register */
1133 #define NVM_WRSR_OPCODE_SPI 0x01 /* NVM write Status register */
1135 /* SPI NVM Status Register */
1136 #define NVM_STATUS_RDY_SPI 0x01
1137 #define NVM_STATUS_WEN_SPI 0x02
1138 #define NVM_STATUS_BP0_SPI 0x04
1139 #define NVM_STATUS_BP1_SPI 0x08
1140 #define NVM_STATUS_WPEN_SPI 0x80
1142 /* Word definitions for ID LED Settings */
1143 #define ID_LED_RESERVED_0000 0x0000
1144 #define ID_LED_RESERVED_FFFF 0xFFFF
1145 #define ID_LED_DEFAULT ((ID_LED_OFF1_ON2 << 12) | \
1146 (ID_LED_OFF1_OFF2 << 8) | \
1147 (ID_LED_DEF1_DEF2 << 4) | \
1149 #define ID_LED_DEF1_DEF2 0x1
1150 #define ID_LED_DEF1_ON2 0x2
1151 #define ID_LED_DEF1_OFF2 0x3
1152 #define ID_LED_ON1_DEF2 0x4
1153 #define ID_LED_ON1_ON2 0x5
1154 #define ID_LED_ON1_OFF2 0x6
1155 #define ID_LED_OFF1_DEF2 0x7
1156 #define ID_LED_OFF1_ON2 0x8
1157 #define ID_LED_OFF1_OFF2 0x9
1159 #define IGP_ACTIVITY_LED_MASK 0xFFFFF0FF
1160 #define IGP_ACTIVITY_LED_ENABLE 0x0300
1161 #define IGP_LED3_MODE 0x07000000
1163 /* PCI/PCI-X/PCI-EX Config space */
1164 #define PCIX_COMMAND_REGISTER 0xE6
1165 #define PCIX_STATUS_REGISTER_LO 0xE8
1166 #define PCIX_STATUS_REGISTER_HI 0xEA
1167 #define PCI_HEADER_TYPE_REGISTER 0x0E
1168 #define PCIE_LINK_STATUS 0x12
1170 #define PCIX_COMMAND_MMRBC_MASK 0x000C
1171 #define PCIX_COMMAND_MMRBC_SHIFT 0x2
1172 #define PCIX_STATUS_HI_MMRBC_MASK 0x0060
1173 #define PCIX_STATUS_HI_MMRBC_SHIFT 0x5
1174 #define PCIX_STATUS_HI_MMRBC_4K 0x3
1175 #define PCIX_STATUS_HI_MMRBC_2K 0x2
1176 #define PCIX_STATUS_LO_FUNC_MASK 0x7
1177 #define PCI_HEADER_TYPE_MULTIFUNC 0x80
1178 #define PCIE_LINK_WIDTH_MASK 0x3F0
1179 #define PCIE_LINK_WIDTH_SHIFT 4
1181 #ifndef ETH_ADDR_LEN
1182 #define ETH_ADDR_LEN 6
1185 #define PHY_REVISION_MASK 0xFFFFFFF0
1186 #define MAX_PHY_REG_ADDRESS 0x1F /* 5 bit address bus (0-0x1F) */
1187 #define MAX_PHY_MULTI_PAGE_REG 0xF
1189 /* Bit definitions for valid PHY IDs. */
1194 #define M88E1000_E_PHY_ID 0x01410C50
1195 #define M88E1000_I_PHY_ID 0x01410C30
1196 #define M88E1011_I_PHY_ID 0x01410C20
1197 #define IGP01E1000_I_PHY_ID 0x02A80380
1198 #define M88E1011_I_REV_4 0x04
1199 #define M88E1111_I_PHY_ID 0x01410CC0
1200 #define GG82563_E_PHY_ID 0x01410CA0
1201 #define IGP03E1000_E_PHY_ID 0x02A80390
1202 #define IFE_E_PHY_ID 0x02A80330
1203 #define IFE_PLUS_E_PHY_ID 0x02A80320
1204 #define IFE_C_E_PHY_ID 0x02A80310
1205 #define M88_VENDOR 0x0141
1207 /* M88E1000 Specific Registers */
1208 #define M88E1000_PHY_SPEC_CTRL 0x10 /* PHY Specific Control Register */
1209 #define M88E1000_PHY_SPEC_STATUS 0x11 /* PHY Specific Status Register */
1210 #define M88E1000_INT_ENABLE 0x12 /* Interrupt Enable Register */
1211 #define M88E1000_INT_STATUS 0x13 /* Interrupt Status Register */
1212 #define M88E1000_EXT_PHY_SPEC_CTRL 0x14 /* Extended PHY Specific Control */
1213 #define M88E1000_RX_ERR_CNTR 0x15 /* Receive Error Counter */
1215 #define M88E1000_PHY_EXT_CTRL 0x1A /* PHY extend control register */
1216 #define M88E1000_PHY_PAGE_SELECT 0x1D /* Reg 29 for page number setting */
1217 #define M88E1000_PHY_GEN_CONTROL 0x1E /* Its meaning depends on reg 29 */
1218 #define M88E1000_PHY_VCO_REG_BIT8 0x100 /* Bits 8 & 11 are adjusted for */
1219 #define M88E1000_PHY_VCO_REG_BIT11 0x800 /* improved BER performance */
1221 /* M88E1000 PHY Specific Control Register */
1222 #define M88E1000_PSCR_JABBER_DISABLE 0x0001 /* 1=Jabber Function disabled */
1223 #define M88E1000_PSCR_POLARITY_REVERSAL 0x0002 /* 1=Polarity Reverse enabled */
1224 #define M88E1000_PSCR_SQE_TEST 0x0004 /* 1=SQE Test enabled */
1225 /* 1=CLK125 low, 0=CLK125 toggling */
1226 #define M88E1000_PSCR_CLK125_DISABLE 0x0010
1227 #define M88E1000_PSCR_MDI_MANUAL_MODE 0x0000 /* MDI Crossover Mode bits 6:5 */
1228 /* Manual MDI configuration */
1229 #define M88E1000_PSCR_MDIX_MANUAL_MODE 0x0020 /* Manual MDIX configuration */
1230 /* 1000BASE-T: Auto crossover, 100BASE-TX/10BASE-T: MDI Mode */
1231 #define M88E1000_PSCR_AUTO_X_1000T 0x0040
1232 /* Auto crossover enabled all speeds */
1233 #define M88E1000_PSCR_AUTO_X_MODE 0x0060
1235 * 1=Enable Extended 10BASE-T distance (Lower 10BASE-T Rx Threshold
1236 * 0=Normal 10BASE-T Rx Threshold
1238 #define M88E1000_PSCR_EN_10BT_EXT_DIST 0x0080
1239 /* 1=5-bit interface in 100BASE-TX, 0=MII interface in 100BASE-TX */
1240 #define M88E1000_PSCR_MII_5BIT_ENABLE 0x0100
1241 #define M88E1000_PSCR_SCRAMBLER_DISABLE 0x0200 /* 1=Scrambler disable */
1242 #define M88E1000_PSCR_FORCE_LINK_GOOD 0x0400 /* 1=Force link good */
1243 #define M88E1000_PSCR_ASSERT_CRS_ON_TX 0x0800 /* 1=Assert CRS on Tx */
1245 /* M88E1000 PHY Specific Status Register */
1246 #define M88E1000_PSSR_JABBER 0x0001 /* 1=Jabber */
1247 #define M88E1000_PSSR_REV_POLARITY 0x0002 /* 1=Polarity reversed */
1248 #define M88E1000_PSSR_DOWNSHIFT 0x0020 /* 1=Downshifted */
1249 #define M88E1000_PSSR_MDIX 0x0040 /* 1=MDIX; 0=MDI */
1257 #define M88E1000_PSSR_CABLE_LENGTH 0x0380
1258 #define M88E1000_PSSR_LINK 0x0400 /* 1=Link up, 0=Link down */
1259 #define M88E1000_PSSR_SPD_DPLX_RESOLVED 0x0800 /* 1=Speed & Duplex resolved */
1260 #define M88E1000_PSSR_PAGE_RCVD 0x1000 /* 1=Page received */
1261 #define M88E1000_PSSR_DPLX 0x2000 /* 1=Duplex 0=Half Duplex */
1262 #define M88E1000_PSSR_SPEED 0xC000 /* Speed, bits 14:15 */
1263 #define M88E1000_PSSR_10MBS 0x0000 /* 00=10Mbs */
1264 #define M88E1000_PSSR_100MBS 0x4000 /* 01=100Mbs */
1265 #define M88E1000_PSSR_1000MBS 0x8000 /* 10=1000Mbs */
1267 #define M88E1000_PSSR_CABLE_LENGTH_SHIFT 7
1269 /* M88E1000 Extended PHY Specific Control Register */
1270 #define M88E1000_EPSCR_FIBER_LOOPBACK 0x4000 /* 1=Fiber loopback */
1272 * 1 = Lost lock detect enabled.
1273 * Will assert lost lock and bring
1274 * link down if idle not seen
1275 * within 1ms in 1000BASE-T
1277 #define M88E1000_EPSCR_DOWN_NO_IDLE 0x8000
1279 * Number of times we will attempt to autonegotiate before downshifting if we
1282 #define M88E1000_EPSCR_MASTER_DOWNSHIFT_MASK 0x0C00
1283 #define M88E1000_EPSCR_MASTER_DOWNSHIFT_1X 0x0000
1284 #define M88E1000_EPSCR_MASTER_DOWNSHIFT_2X 0x0400
1285 #define M88E1000_EPSCR_MASTER_DOWNSHIFT_3X 0x0800
1286 #define M88E1000_EPSCR_MASTER_DOWNSHIFT_4X 0x0C00
1288 * Number of times we will attempt to autonegotiate before downshifting if we
1291 #define M88E1000_EPSCR_SLAVE_DOWNSHIFT_MASK 0x0300
1292 #define M88E1000_EPSCR_SLAVE_DOWNSHIFT_DIS 0x0000
1293 #define M88E1000_EPSCR_SLAVE_DOWNSHIFT_1X 0x0100
1294 #define M88E1000_EPSCR_SLAVE_DOWNSHIFT_2X 0x0200
1295 #define M88E1000_EPSCR_SLAVE_DOWNSHIFT_3X 0x0300
1296 #define M88E1000_EPSCR_TX_CLK_2_5 0x0060 /* 2.5 MHz TX_CLK */
1297 #define M88E1000_EPSCR_TX_CLK_25 0x0070 /* 25 MHz TX_CLK */
1298 #define M88E1000_EPSCR_TX_CLK_0 0x0000 /* NO TX_CLK */
1300 /* M88EC018 Rev 2 specific DownShift settings */
1301 #define M88EC018_EPSCR_DOWNSHIFT_COUNTER_MASK 0x0E00
1302 #define M88EC018_EPSCR_DOWNSHIFT_COUNTER_1X 0x0000
1303 #define M88EC018_EPSCR_DOWNSHIFT_COUNTER_2X 0x0200
1304 #define M88EC018_EPSCR_DOWNSHIFT_COUNTER_3X 0x0400
1305 #define M88EC018_EPSCR_DOWNSHIFT_COUNTER_4X 0x0600
1306 #define M88EC018_EPSCR_DOWNSHIFT_COUNTER_5X 0x0800
1307 #define M88EC018_EPSCR_DOWNSHIFT_COUNTER_6X 0x0A00
1308 #define M88EC018_EPSCR_DOWNSHIFT_COUNTER_7X 0x0C00
1309 #define M88EC018_EPSCR_DOWNSHIFT_COUNTER_8X 0x0E00
1314 * 4-0: register offset
1316 #define GG82563_PAGE_SHIFT 5
1317 #define GG82563_REG(page, reg) \
1318 (((page) << GG82563_PAGE_SHIFT) | ((reg) & MAX_PHY_REG_ADDRESS))
1319 #define GG82563_MIN_ALT_REG 30
1321 /* GG82563 Specific Registers */
1322 #define GG82563_PHY_SPEC_CTRL \
1323 GG82563_REG(0, 16) /* PHY Specific Control */
1324 #define GG82563_PHY_SPEC_STATUS \
1325 GG82563_REG(0, 17) /* PHY Specific Status */
1326 #define GG82563_PHY_INT_ENABLE \
1327 GG82563_REG(0, 18) /* Interrupt Enable */
1328 #define GG82563_PHY_SPEC_STATUS_2 \
1329 GG82563_REG(0, 19) /* PHY Specific Status 2 */
1330 #define GG82563_PHY_RX_ERR_CNTR \
1331 GG82563_REG(0, 21) /* Receive Error Counter */
1332 #define GG82563_PHY_PAGE_SELECT \
1333 GG82563_REG(0, 22) /* Page Select */
1334 #define GG82563_PHY_SPEC_CTRL_2 \
1335 GG82563_REG(0, 26) /* PHY Specific Control 2 */
1336 #define GG82563_PHY_PAGE_SELECT_ALT \
1337 GG82563_REG(0, 29) /* Alternate Page Select */
1338 #define GG82563_PHY_TEST_CLK_CTRL \
1339 GG82563_REG(0, 30) /* Test Clock Control (use reg. 29 to select) */
1341 #define GG82563_PHY_MAC_SPEC_CTRL \
1342 GG82563_REG(2, 21) /* MAC Specific Control Register */
1343 #define GG82563_PHY_MAC_SPEC_CTRL_2 \
1344 GG82563_REG(2, 26) /* MAC Specific Control 2 */
1346 #define GG82563_PHY_DSP_DISTANCE \
1347 GG82563_REG(5, 26) /* DSP Distance */
1349 /* Page 193 - Port Control Registers */
1350 #define GG82563_PHY_KMRN_MODE_CTRL \
1351 GG82563_REG(193, 16) /* Kumeran Mode Control */
1352 #define GG82563_PHY_PORT_RESET \
1353 GG82563_REG(193, 17) /* Port Reset */
1354 #define GG82563_PHY_REVISION_ID \
1355 GG82563_REG(193, 18) /* Revision ID */
1356 #define GG82563_PHY_DEVICE_ID \
1357 GG82563_REG(193, 19) /* Device ID */
1358 #define GG82563_PHY_PWR_MGMT_CTRL \
1359 GG82563_REG(193, 20) /* Power Management Control */
1360 #define GG82563_PHY_RATE_ADAPT_CTRL \
1361 GG82563_REG(193, 25) /* Rate Adaptation Control */
1363 /* Page 194 - KMRN Registers */
1364 #define GG82563_PHY_KMRN_FIFO_CTRL_STAT \
1365 GG82563_REG(194, 16) /* FIFO's Control/Status */
1366 #define GG82563_PHY_KMRN_CTRL \
1367 GG82563_REG(194, 17) /* Control */
1368 #define GG82563_PHY_INBAND_CTRL \
1369 GG82563_REG(194, 18) /* Inband Control */
1370 #define GG82563_PHY_KMRN_DIAGNOSTIC \
1371 GG82563_REG(194, 19) /* Diagnostic */
1372 #define GG82563_PHY_ACK_TIMEOUTS \
1373 GG82563_REG(194, 20) /* Acknowledge Timeouts */
1374 #define GG82563_PHY_ADV_ABILITY \
1375 GG82563_REG(194, 21) /* Advertised Ability */
1376 #define GG82563_PHY_LINK_PARTNER_ADV_ABILITY \
1377 GG82563_REG(194, 23) /* Link Partner Advertised Ability */
1378 #define GG82563_PHY_ADV_NEXT_PAGE \
1379 GG82563_REG(194, 24) /* Advertised Next Page */
1380 #define GG82563_PHY_LINK_PARTNER_ADV_NEXT_PAGE \
1381 GG82563_REG(194, 25) /* Link Partner Advertised Next page */
1382 #define GG82563_PHY_KMRN_MISC \
1383 GG82563_REG(194, 26) /* Misc. */
1386 #define E1000_MDIC_DATA_MASK 0x0000FFFF
1387 #define E1000_MDIC_REG_MASK 0x001F0000
1388 #define E1000_MDIC_REG_SHIFT 16
1389 #define E1000_MDIC_PHY_MASK 0x03E00000
1390 #define E1000_MDIC_PHY_SHIFT 21
1391 #define E1000_MDIC_OP_WRITE 0x04000000
1392 #define E1000_MDIC_OP_READ 0x08000000
1393 #define E1000_MDIC_READY 0x10000000
1394 #define E1000_MDIC_INT_EN 0x20000000
1395 #define E1000_MDIC_ERROR 0x40000000
1397 /* SerDes Control */
1398 #define E1000_GEN_CTL_READY 0x80000000
1399 #define E1000_GEN_CTL_ADDRESS_SHIFT 8
1400 #define E1000_GEN_POLL_TIMEOUT 640
1404 #endif /* _E1000_DEFINES_H_ */