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Check for SYS/GL during library init. Reason is that
[AROS.git] / workbench / devs / networks / e1000 / e1000_mac.c
blob7e46d0549d707c74ef16a542178f10d61d0a08b5
1 /*******************************************************************************
2
3 Intel PRO/1000 Linux driver
4 Copyright(c) 1999 - 2008 Intel Corporation.
5
6 This program is free software; you can redistribute it and/or modify it
7 under the terms and conditions of the GNU General Public License,
8 version 2, as published by the Free Software Foundation.
9
10 This program is distributed in the hope it will be useful, but WITHOUT
11 ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
12 FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
13 more details.
14
15 You should have received a copy of the GNU General Public License along with
16 this program; if not, write to the Free Software Foundation, Inc.,
17 51 Franklin St - Fifth Floor, Boston, MA 02110-1301 USA.
18
19 The full GNU General Public License is included in this distribution in
20 the file called "COPYING".
21
22 Contact Information:
23 Linux NICS <linux.nics@intel.com>
24 e1000-devel Mailing List <e1000-devel@lists.sourceforge.net>
25 Intel Corporation, 5200 N.E. Elam Young Parkway, Hillsboro, OR 97124-6497
26
27 *******************************************************************************/
28
29 #include "e1000_api.h"
30
31 static s32 e1000_validate_mdi_setting_generic(struct e1000_hw *hw);
32 static void e1000_set_lan_id_multi_port_pcie(struct e1000_hw *hw);
33
34 /**
35 * e1000_init_mac_ops_generic - Initialize MAC function pointers
36 * @hw: pointer to the HW structure
37 *
38 * Setups up the function pointers to no-op functions
39 **/
40 void e1000_init_mac_ops_generic(struct e1000_hw *hw)
41 {
42 struct e1000_mac_info *mac = &hw->mac;
43 DEBUGFUNC("e1000_init_mac_ops_generic");
44
45 /* General Setup */
46 mac->ops.init_params = e1000_null_ops_generic;
47 mac->ops.init_hw = e1000_null_ops_generic;
48 mac->ops.reset_hw = e1000_null_ops_generic;
49 mac->ops.setup_physical_interface = e1000_null_ops_generic;
50 mac->ops.get_bus_info = e1000_null_ops_generic;
51 mac->ops.set_lan_id = e1000_set_lan_id_multi_port_pcie;
52 mac->ops.read_mac_addr = e1000_read_mac_addr_generic;
53 mac->ops.config_collision_dist = e1000_config_collision_dist_generic;
54 mac->ops.clear_hw_cntrs = e1000_null_mac_generic;
55 /* LED */
56 mac->ops.cleanup_led = e1000_null_ops_generic;
57 mac->ops.setup_led = e1000_null_ops_generic;
58 mac->ops.blink_led = e1000_null_ops_generic;
59 mac->ops.led_on = e1000_null_ops_generic;
60 mac->ops.led_off = e1000_null_ops_generic;
61 /* LINK */
62 mac->ops.setup_link = e1000_null_ops_generic;
63 mac->ops.get_link_up_info = e1000_null_link_info;
64 mac->ops.check_for_link = e1000_null_ops_generic;
65 mac->ops.wait_autoneg = e1000_wait_autoneg_generic;
66 /* Management */
67 mac->ops.check_mng_mode = e1000_null_mng_mode;
68 mac->ops.mng_host_if_write = e1000_mng_host_if_write_generic;
69 mac->ops.mng_write_cmd_header = e1000_mng_write_cmd_header_generic;
70 mac->ops.mng_enable_host_if = e1000_mng_enable_host_if_generic;
71 /* VLAN, MC, etc. */
72 mac->ops.update_mc_addr_list = e1000_null_update_mc;
73 mac->ops.clear_vfta = e1000_null_mac_generic;
74 mac->ops.write_vfta = e1000_null_write_vfta;
75 mac->ops.mta_set = e1000_null_mta_set;
76 mac->ops.rar_set = e1000_rar_set_generic;
77 mac->ops.validate_mdi_setting = e1000_validate_mdi_setting_generic;
78 }
79
80 /**
81 * e1000_null_ops_generic - No-op function, returns 0
82 * @hw: pointer to the HW structure
83 **/
84 s32 e1000_null_ops_generic(struct e1000_hw *hw)
85 {
86 DEBUGFUNC("e1000_null_ops_generic");
87 return E1000_SUCCESS;
88 }
89
90 /**
91 * e1000_null_mac_generic - No-op function, return void
92 * @hw: pointer to the HW structure
93 **/
94 void e1000_null_mac_generic(struct e1000_hw *hw)
95 {
96 DEBUGFUNC("e1000_null_mac_generic");
97 return;
98 }
99
100 /**
101 * e1000_null_link_info - No-op function, return 0
102 * @hw: pointer to the HW structure
103 **/
104 s32 e1000_null_link_info(struct e1000_hw *hw, u16 *s, u16 *d)
105 {
106 DEBUGFUNC("e1000_null_link_info");
107 return E1000_SUCCESS;
108 }
109
110 /**
111 * e1000_null_mng_mode - No-op function, return false
112 * @hw: pointer to the HW structure
113 **/
114 bool e1000_null_mng_mode(struct e1000_hw *hw)
115 {
116 DEBUGFUNC("e1000_null_mng_mode");
117 return false;
118 }
119
120 /**
121 * e1000_null_update_mc - No-op function, return void
122 * @hw: pointer to the HW structure
123 **/
124 void e1000_null_update_mc(struct e1000_hw *hw, u8 *h, u32 a)
125 {
126 DEBUGFUNC("e1000_null_update_mc");
127 return;
128 }
129
130 /**
131 * e1000_null_write_vfta - No-op function, return void
132 * @hw: pointer to the HW structure
133 **/
134 void e1000_null_write_vfta(struct e1000_hw *hw, u32 a, u32 b)
135 {
136 DEBUGFUNC("e1000_null_write_vfta");
137 return;
138 }
139
140 /**
141 * e1000_null_set_mta - No-op function, return void
142 * @hw: pointer to the HW structure
143 **/
144 void e1000_null_mta_set(struct e1000_hw *hw, u32 a)
145 {
146 DEBUGFUNC("e1000_null_mta_set");
147 return;
148 }
149
150 /**
151 * e1000_null_rar_set - No-op function, return void
152 * @hw: pointer to the HW structure
153 **/
154 void e1000_null_rar_set(struct e1000_hw *hw, u8 *h, u32 a)
155 {
156 DEBUGFUNC("e1000_null_rar_set");
157 return;
158 }
159
160 /**
161 * e1000_get_bus_info_pci_generic - Get PCI(x) bus information
162 * @hw: pointer to the HW structure
163 *
164 * Determines and stores the system bus information for a particular
165 * network interface. The following bus information is determined and stored:
166 * bus speed, bus width, type (PCI/PCIx), and PCI(-x) function.
167 **/
168 s32 e1000_get_bus_info_pci_generic(struct e1000_hw *hw)
169 {
170 struct e1000_mac_info *mac = &hw->mac;
171 struct e1000_bus_info *bus = &hw->bus;
172 u32 status = E1000_READ_REG(hw, E1000_STATUS);
173 s32 ret_val = E1000_SUCCESS;
174
175 DEBUGFUNC("e1000_get_bus_info_pci_generic");
176
177 /* PCI or PCI-X? */
178 bus->type = (status & E1000_STATUS_PCIX_MODE)
179 ? e1000_bus_type_pcix
180 : e1000_bus_type_pci;
181
182 /* Bus speed */
183 if (bus->type == e1000_bus_type_pci) {
184 bus->speed = (status & E1000_STATUS_PCI66)
185 ? e1000_bus_speed_66
186 : e1000_bus_speed_33;
187 } else {
188 switch (status & E1000_STATUS_PCIX_SPEED) {
189 case E1000_STATUS_PCIX_SPEED_66:
190 bus->speed = e1000_bus_speed_66;
191 break;
192 case E1000_STATUS_PCIX_SPEED_100:
193 bus->speed = e1000_bus_speed_100;
194 break;
195 case E1000_STATUS_PCIX_SPEED_133:
196 bus->speed = e1000_bus_speed_133;
197 break;
198 default:
199 bus->speed = e1000_bus_speed_reserved;
200 break;
201 }
202 }
203
204 /* Bus width */
205 bus->width = (status & E1000_STATUS_BUS64)
206 ? e1000_bus_width_64
207 : e1000_bus_width_32;
208
209 /* Which PCI(-X) function? */
210 mac->ops.set_lan_id(hw);
211
212 return ret_val;
213 }
214
215 /**
216 * e1000_get_bus_info_pcie_generic - Get PCIe bus information
217 * @hw: pointer to the HW structure
218 *
219 * Determines and stores the system bus information for a particular
220 * network interface. The following bus information is determined and stored:
221 * bus speed, bus width, type (PCIe), and PCIe function.
222 **/
223 s32 e1000_get_bus_info_pcie_generic(struct e1000_hw *hw)
224 {
225 struct e1000_mac_info *mac = &hw->mac;
226 struct e1000_bus_info *bus = &hw->bus;
227
228 s32 ret_val;
229 u16 pcie_link_status;
230
231 DEBUGFUNC("e1000_get_bus_info_pcie_generic");
232
233 bus->type = e1000_bus_type_pci_express;
234 bus->speed = e1000_bus_speed_2500;
235
236 ret_val = e1000_read_pcie_cap_reg(hw,
237 PCIE_LINK_STATUS,
238 &pcie_link_status);
239 if (ret_val)
240 bus->width = e1000_bus_width_unknown;
241 else
242 bus->width = (enum e1000_bus_width)((pcie_link_status &
243 PCIE_LINK_WIDTH_MASK) >>
244 PCIE_LINK_WIDTH_SHIFT);
245
246 mac->ops.set_lan_id(hw);
247
248 return E1000_SUCCESS;
249 }
250
251 /**
252 * e1000_set_lan_id_multi_port_pcie - Set LAN id for PCIe multiple port devices
253 *
254 * @hw: pointer to the HW structure
255 *
256 * Determines the LAN function id by reading memory-mapped registers
257 * and swaps the port value if requested.
258 **/
259 static void e1000_set_lan_id_multi_port_pcie(struct e1000_hw *hw)
260 {
261 struct e1000_bus_info *bus = &hw->bus;
262 u32 reg;
263
264 /*
265 * The status register reports the correct function number
266 * for the device regardless of function swap state.
267 */
268 reg = E1000_READ_REG(hw, E1000_STATUS);
269 bus->func = (reg & E1000_STATUS_FUNC_MASK) >> E1000_STATUS_FUNC_SHIFT;
270 }
271
272 /**
273 * e1000_set_lan_id_multi_port_pci - Set LAN id for PCI multiple port devices
274 * @hw: pointer to the HW structure
275 *
276 * Determines the LAN function id by reading PCI config space.
277 **/
278 void e1000_set_lan_id_multi_port_pci(struct e1000_hw *hw)
279 {
280 struct e1000_bus_info *bus = &hw->bus;
281 u16 pci_header_type;
282 u32 status;
283
284 e1000_read_pci_cfg(hw, PCI_HEADER_TYPE_REGISTER, &pci_header_type);
285 if (pci_header_type & PCI_HEADER_TYPE_MULTIFUNC) {
286 status = E1000_READ_REG(hw, E1000_STATUS);
287 bus->func = (status & E1000_STATUS_FUNC_MASK)
288 >> E1000_STATUS_FUNC_SHIFT;
289 } else {
290 bus->func = 0;
291 }
292 }
293
294 /**
295 * e1000_set_lan_id_single_port - Set LAN id for a single port device
296 * @hw: pointer to the HW structure
297 *
298 * Sets the LAN function id to zero for a single port device.
299 **/
300 void e1000_set_lan_id_single_port(struct e1000_hw *hw)
301 {
302 struct e1000_bus_info *bus = &hw->bus;
303
304 bus->func = 0;
305 }
306
307 /**
308 * e1000_clear_vfta_generic - Clear VLAN filter table
309 * @hw: pointer to the HW structure
310 *
311 * Clears the register array which contains the VLAN filter table by
312 * setting all the values to 0.
313 **/
314 void e1000_clear_vfta_generic(struct e1000_hw *hw)
315 {
316 u32 offset;
317
318 DEBUGFUNC("e1000_clear_vfta_generic");
319
320 for (offset = 0; offset < E1000_VLAN_FILTER_TBL_SIZE; offset++) {
321 E1000_WRITE_REG_ARRAY(hw, E1000_VFTA, offset, 0);
322 E1000_WRITE_FLUSH(hw);
323 }
324 }
325
326 /**
327 * e1000_write_vfta_generic - Write value to VLAN filter table
328 * @hw: pointer to the HW structure
329 * @offset: register offset in VLAN filter table
330 * @value: register value written to VLAN filter table
331 *
332 * Writes value at the given offset in the register array which stores
333 * the VLAN filter table.
334 **/
335 void e1000_write_vfta_generic(struct e1000_hw *hw, u32 offset, u32 value)
336 {
337 DEBUGFUNC("e1000_write_vfta_generic");
338
339 E1000_WRITE_REG_ARRAY(hw, E1000_VFTA, offset, value);
340 E1000_WRITE_FLUSH(hw);
341 }
342
343 /**
344 * e1000_init_rx_addrs_generic - Initialize receive address's
345 * @hw: pointer to the HW structure
346 * @rar_count: receive address registers
347 *
348 * Setups the receive address registers by setting the base receive address
349 * register to the devices MAC address and clearing all the other receive
350 * address registers to 0.
351 **/
352 void e1000_init_rx_addrs_generic(struct e1000_hw *hw, u16 rar_count)
353 {
354 u32 i;
355 u8 mac_addr[ETH_ADDR_LEN] = {0};
356
357 DEBUGFUNC("e1000_init_rx_addrs_generic");
358
359 /* Setup the receive address */
360 DEBUGOUT("Programming MAC Address into RAR[0]\n");
361
362 hw->mac.ops.rar_set(hw, hw->mac.addr, 0);
363
364 /* Zero out the other (rar_entry_count - 1) receive addresses */
365 DEBUGOUT1("Clearing RAR[1-%u]\n", rar_count-1);
366 for (i = 1; i < rar_count; i++)
367 hw->mac.ops.rar_set(hw, mac_addr, i);
368 }
369
370 /**
371 * e1000_check_alt_mac_addr_generic - Check for alternate MAC addr
372 * @hw: pointer to the HW structure
373 *
374 * Checks the nvm for an alternate MAC address. An alternate MAC address
375 * can be setup by pre-boot software and must be treated like a permanent
376 * address and must override the actual permanent MAC address. If an
377 * alternate MAC address is found it is programmed into RAR0, replacing
378 * the permanent address that was installed into RAR0 by the Si on reset.
379 * This function will return SUCCESS unless it encounters an error while
380 * reading the EEPROM.
381 **/
382 s32 e1000_check_alt_mac_addr_generic(struct e1000_hw *hw)
383 {
384 u32 i;
385 s32 ret_val = E1000_SUCCESS;
386 u16 offset, nvm_alt_mac_addr_offset, nvm_data;
387 u8 alt_mac_addr[ETH_ADDR_LEN];
388
389 DEBUGFUNC("e1000_check_alt_mac_addr_generic");
390
391 ret_val = hw->nvm.ops.read(hw, NVM_ALT_MAC_ADDR_PTR, 1,
392 &nvm_alt_mac_addr_offset);
393 if (ret_val) {
394 DEBUGOUT("NVM Read Error\n");
395 goto out;
396 }
397
398 if (nvm_alt_mac_addr_offset == 0xFFFF) {
399 /* There is no Alternate MAC Address */
400 goto out;
401 }
402
403 if (hw->bus.func == E1000_FUNC_1)
404 nvm_alt_mac_addr_offset += E1000_ALT_MAC_ADDRESS_OFFSET_LAN1;
405 for (i = 0; i < ETH_ADDR_LEN; i += 2) {
406 offset = nvm_alt_mac_addr_offset + (i >> 1);
407 ret_val = hw->nvm.ops.read(hw, offset, 1, &nvm_data);
408 if (ret_val) {
409 DEBUGOUT("NVM Read Error\n");
410 goto out;
411 }
412
413 alt_mac_addr[i] = (u8)(nvm_data & 0xFF);
414 alt_mac_addr[i + 1] = (u8)(nvm_data >> 8);
415 }
416
417 /* if multicast bit is set, the alternate address will not be used */
418 if (alt_mac_addr[0] & 0x01) {
419 DEBUGOUT("Ignoring Alternate Mac Address with MC bit set\n");
420 goto out;
421 }
422
423 /*
424 * We have a valid alternate MAC address, and we want to treat it the
425 * same as the normal permanent MAC address stored by the HW into the
426 * RAR. Do this by mapping this address into RAR0.
427 */
428 hw->mac.ops.rar_set(hw, alt_mac_addr, 0);
429
430 out:
431 return ret_val;
432 }
433
434 /**
435 * e1000_rar_set_generic - Set receive address register
436 * @hw: pointer to the HW structure
437 * @addr: pointer to the receive address
438 * @index: receive address array register
439 *
440 * Sets the receive address array register at index to the address passed
441 * in by addr.
442 **/
443 void e1000_rar_set_generic(struct e1000_hw *hw, u8 *addr, u32 index)
444 {
445 u32 rar_low, rar_high;
446
447 DEBUGFUNC("e1000_rar_set_generic");
448
449 /*
450 * HW expects these in little endian so we reverse the byte order
451 * from network order (big endian) to little endian
452 */
453 rar_low = ((u32) addr[0] |
454 ((u32) addr[1] << 8) |
455 ((u32) addr[2] << 16) | ((u32) addr[3] << 24));
456
457 rar_high = ((u32) addr[4] | ((u32) addr[5] << 8));
458
459 /* If MAC address zero, no need to set the AV bit */
460 if (rar_low || rar_high)
461 rar_high |= E1000_RAH_AV;
462
463 /*
464 * Some bridges will combine consecutive 32-bit writes into
465 * a single burst write, which will malfunction on some parts.
466 * The flushes avoid this.
467 */
468 E1000_WRITE_REG(hw, E1000_RAL(index), rar_low);
469 E1000_WRITE_FLUSH(hw);
470 E1000_WRITE_REG(hw, E1000_RAH(index), rar_high);
471 E1000_WRITE_FLUSH(hw);
472 }
473
474 /**
475 * e1000_mta_set_generic - Set multicast filter table address
476 * @hw: pointer to the HW structure
477 * @hash_value: determines the MTA register and bit to set
478 *
479 * The multicast table address is a register array of 32-bit registers.
480 * The hash_value is used to determine what register the bit is in, the
481 * current value is read, the new bit is OR'd in and the new value is
482 * written back into the register.
483 **/
484 void e1000_mta_set_generic(struct e1000_hw *hw, u32 hash_value)
485 {
486 u32 hash_bit, hash_reg, mta;
487
488 DEBUGFUNC("e1000_mta_set_generic");
489 /*
490 * The MTA is a register array of 32-bit registers. It is
491 * treated like an array of (32*mta_reg_count) bits. We want to
492 * set bit BitArray[hash_value]. So we figure out what register
493 * the bit is in, read it, OR in the new bit, then write
494 * back the new value. The (hw->mac.mta_reg_count - 1) serves as a
495 * mask to bits 31:5 of the hash value which gives us the
496 * register we're modifying. The hash bit within that register
497 * is determined by the lower 5 bits of the hash value.
498 */
499 hash_reg = (hash_value >> 5) & (hw->mac.mta_reg_count - 1);
500 hash_bit = hash_value & 0x1F;
501
502 mta = E1000_READ_REG_ARRAY(hw, E1000_MTA, hash_reg);
503
504 mta |= (1 << hash_bit);
505
506 E1000_WRITE_REG_ARRAY(hw, E1000_MTA, hash_reg, mta);
507 E1000_WRITE_FLUSH(hw);
508 }
509
510 /**
511 * e1000_update_mc_addr_list_generic - Update Multicast addresses
512 * @hw: pointer to the HW structure
513 * @mc_addr_list: array of multicast addresses to program
514 * @mc_addr_count: number of multicast addresses to program
515 *
516 * Updates entire Multicast Table Array.
517 * The caller must have a packed mc_addr_list of multicast addresses.
518 **/
519 void e1000_update_mc_addr_list_generic(struct e1000_hw *hw,
520 u8 *mc_addr_list, u32 mc_addr_count)
521 {
522 u32 hash_value, hash_bit, hash_reg;
523 int i;
524
525 DEBUGFUNC("e1000_update_mc_addr_list_generic");
526
527 /* clear mta_shadow */
528 memset(&hw->mac.mta_shadow, 0, sizeof(hw->mac.mta_shadow));
529
530 /* update mta_shadow from mc_addr_list */
531 for (i = 0; (u32) i < mc_addr_count; i++) {
532 hash_value = e1000_hash_mc_addr_generic(hw, mc_addr_list);
533
534 hash_reg = (hash_value >> 5) & (hw->mac.mta_reg_count - 1);
535 hash_bit = hash_value & 0x1F;
536
537 hw->mac.mta_shadow[hash_reg] |= (1 << hash_bit);
538 mc_addr_list += (ETH_ADDR_LEN);
539 }
540
541 /* replace the entire MTA table */
542 for (i = hw->mac.mta_reg_count - 1; i >= 0; i--)
543 E1000_WRITE_REG_ARRAY(hw, E1000_MTA, i, hw->mac.mta_shadow[i]);
544 E1000_WRITE_FLUSH(hw);
545 }
546
547 /**
548 * e1000_hash_mc_addr_generic - Generate a multicast hash value
549 * @hw: pointer to the HW structure
550 * @mc_addr: pointer to a multicast address
551 *
552 * Generates a multicast address hash value which is used to determine
553 * the multicast filter table array address and new table value. See
554 * e1000_mta_set_generic()
555 **/
556 u32 e1000_hash_mc_addr_generic(struct e1000_hw *hw, u8 *mc_addr)
557 {
558 u32 hash_value, hash_mask;
559 u8 bit_shift = 0;
560
561 DEBUGFUNC("e1000_hash_mc_addr_generic");
562
563 /* Register count multiplied by bits per register */
564 hash_mask = (hw->mac.mta_reg_count * 32) - 1;
565
566 /*
567 * For a mc_filter_type of 0, bit_shift is the number of left-shifts
568 * where 0xFF would still fall within the hash mask.
569 */
570 while (hash_mask >> bit_shift != 0xFF)
571 bit_shift++;
572
573 /*
574 * The portion of the address that is used for the hash table
575 * is determined by the mc_filter_type setting.
576 * The algorithm is such that there is a total of 8 bits of shifting.
577 * The bit_shift for a mc_filter_type of 0 represents the number of
578 * left-shifts where the MSB of mc_addr[5] would still fall within
579 * the hash_mask. Case 0 does this exactly. Since there are a total
580 * of 8 bits of shifting, then mc_addr[4] will shift right the
581 * remaining number of bits. Thus 8 - bit_shift. The rest of the
582 * cases are a variation of this algorithm...essentially raising the
583 * number of bits to shift mc_addr[5] left, while still keeping the
584 * 8-bit shifting total.
585 *
586 * For example, given the following Destination MAC Address and an
587 * mta register count of 128 (thus a 4096-bit vector and 0xFFF mask),
588 * we can see that the bit_shift for case 0 is 4. These are the hash
589 * values resulting from each mc_filter_type...
590 * [0] [1] [2] [3] [4] [5]
591 * 01 AA 00 12 34 56
592 * LSB MSB
593 *
594 * case 0: hash_value = ((0x34 >> 4) | (0x56 << 4)) & 0xFFF = 0x563
595 * case 1: hash_value = ((0x34 >> 3) | (0x56 << 5)) & 0xFFF = 0xAC6
596 * case 2: hash_value = ((0x34 >> 2) | (0x56 << 6)) & 0xFFF = 0x163
597 * case 3: hash_value = ((0x34 >> 0) | (0x56 << 8)) & 0xFFF = 0x634
598 */
599 switch (hw->mac.mc_filter_type) {
600 default:
601 case 0:
602 break;
603 case 1:
604 bit_shift += 1;
605 break;
606 case 2:
607 bit_shift += 2;
608 break;
609 case 3:
610 bit_shift += 4;
611 break;
612 }
613
614 hash_value = hash_mask & (((mc_addr[4] >> (8 - bit_shift)) |
615 (((u16) mc_addr[5]) << bit_shift)));
616
617 return hash_value;
618 }
619
620 /**
621 * e1000_pcix_mmrbc_workaround_generic - Fix incorrect MMRBC value
622 * @hw: pointer to the HW structure
623 *
624 * In certain situations, a system BIOS may report that the PCIx maximum
625 * memory read byte count (MMRBC) value is higher than than the actual
626 * value. We check the PCIx command register with the current PCIx status
627 * register.
628 **/
629 void e1000_pcix_mmrbc_workaround_generic(struct e1000_hw *hw)
630 {
631 u16 cmd_mmrbc;
632 u16 pcix_cmd;
633 u16 pcix_stat_hi_word;
634 u16 stat_mmrbc;
635
636 DEBUGFUNC("e1000_pcix_mmrbc_workaround_generic");
637
638 /* Workaround for PCI-X issue when BIOS sets MMRBC incorrectly */
639 if (hw->bus.type != e1000_bus_type_pcix)
640 return;
641
642 e1000_read_pci_cfg(hw, PCIX_COMMAND_REGISTER, &pcix_cmd);
643 e1000_read_pci_cfg(hw, PCIX_STATUS_REGISTER_HI, &pcix_stat_hi_word);
644 cmd_mmrbc = (pcix_cmd & PCIX_COMMAND_MMRBC_MASK) >>
645 PCIX_COMMAND_MMRBC_SHIFT;
646 stat_mmrbc = (pcix_stat_hi_word & PCIX_STATUS_HI_MMRBC_MASK) >>
647 PCIX_STATUS_HI_MMRBC_SHIFT;
648 if (stat_mmrbc == PCIX_STATUS_HI_MMRBC_4K)
649 stat_mmrbc = PCIX_STATUS_HI_MMRBC_2K;
650 if (cmd_mmrbc > stat_mmrbc) {
651 pcix_cmd &= ~PCIX_COMMAND_MMRBC_MASK;
652 pcix_cmd |= stat_mmrbc << PCIX_COMMAND_MMRBC_SHIFT;
653 e1000_write_pci_cfg(hw, PCIX_COMMAND_REGISTER, &pcix_cmd);
654 }
655 }
656
657 /**
658 * e1000_clear_hw_cntrs_base_generic - Clear base hardware counters
659 * @hw: pointer to the HW structure
660 *
661 * Clears the base hardware counters by reading the counter registers.
662 **/
663 void e1000_clear_hw_cntrs_base_generic(struct e1000_hw *hw)
664 {
665 DEBUGFUNC("e1000_clear_hw_cntrs_base_generic");
666
667 E1000_READ_REG(hw, E1000_CRCERRS);
668 E1000_READ_REG(hw, E1000_SYMERRS);
669 E1000_READ_REG(hw, E1000_MPC);
670 E1000_READ_REG(hw, E1000_SCC);
671 E1000_READ_REG(hw, E1000_ECOL);
672 E1000_READ_REG(hw, E1000_MCC);
673 E1000_READ_REG(hw, E1000_LATECOL);
674 E1000_READ_REG(hw, E1000_COLC);
675 E1000_READ_REG(hw, E1000_DC);
676 E1000_READ_REG(hw, E1000_SEC);
677 E1000_READ_REG(hw, E1000_RLEC);
678 E1000_READ_REG(hw, E1000_XONRXC);
679 E1000_READ_REG(hw, E1000_XONTXC);
680 E1000_READ_REG(hw, E1000_XOFFRXC);
681 E1000_READ_REG(hw, E1000_XOFFTXC);
682 E1000_READ_REG(hw, E1000_FCRUC);
683 E1000_READ_REG(hw, E1000_GPRC);
684 E1000_READ_REG(hw, E1000_BPRC);
685 E1000_READ_REG(hw, E1000_MPRC);
686 E1000_READ_REG(hw, E1000_GPTC);
687 E1000_READ_REG(hw, E1000_GORCL);
688 E1000_READ_REG(hw, E1000_GORCH);
689 E1000_READ_REG(hw, E1000_GOTCL);
690 E1000_READ_REG(hw, E1000_GOTCH);
691 E1000_READ_REG(hw, E1000_RNBC);
692 E1000_READ_REG(hw, E1000_RUC);
693 E1000_READ_REG(hw, E1000_RFC);
694 E1000_READ_REG(hw, E1000_ROC);
695 E1000_READ_REG(hw, E1000_RJC);
696 E1000_READ_REG(hw, E1000_TORL);
697 E1000_READ_REG(hw, E1000_TORH);
698 E1000_READ_REG(hw, E1000_TOTL);
699 E1000_READ_REG(hw, E1000_TOTH);
700 E1000_READ_REG(hw, E1000_TPR);
701 E1000_READ_REG(hw, E1000_TPT);
702 E1000_READ_REG(hw, E1000_MPTC);
703 E1000_READ_REG(hw, E1000_BPTC);
704 }
705
706 /**
707 * e1000_check_for_copper_link_generic - Check for link (Copper)
708 * @hw: pointer to the HW structure
709 *
710 * Checks to see of the link status of the hardware has changed. If a
711 * change in link status has been detected, then we read the PHY registers
712 * to get the current speed/duplex if link exists.
713 **/
714 s32 e1000_check_for_copper_link_generic(struct e1000_hw *hw)
715 {
716 struct e1000_mac_info *mac = &hw->mac;
717 s32 ret_val;
718 bool link;
719
720 DEBUGFUNC("e1000_check_for_copper_link");
721
722 /*
723 * We only want to go out to the PHY registers to see if Auto-Neg
724 * has completed and/or if our link status has changed. The
725 * get_link_status flag is set upon receiving a Link Status
726 * Change or Rx Sequence Error interrupt.
727 */
728 if (!mac->get_link_status) {
729 ret_val = E1000_SUCCESS;
730 goto out;
731 }
732
733 /*
734 * First we want to see if the MII Status Register reports
735 * link. If so, then we want to get the current speed/duplex
736 * of the PHY.
737 */
738 ret_val = e1000_phy_has_link_generic(hw, 1, 0, &link);
739 if (ret_val)
740 goto out;
741
742 if (!link)
743 goto out; /* No link detected */
744
745 mac->get_link_status = false;
746
747 /*
748 * Check if there was DownShift, must be checked
749 * immediately after link-up
750 */
751 e1000_check_downshift_generic(hw);
752
753 /*
754 * If we are forcing speed/duplex, then we simply return since
755 * we have already determined whether we have link or not.
756 */
757 if (!mac->autoneg) {
758 ret_val = -E1000_ERR_CONFIG;
759 goto out;
760 }
761
762 /*
763 * Auto-Neg is enabled. Auto Speed Detection takes care
764 * of MAC speed/duplex configuration. So we only need to
765 * configure Collision Distance in the MAC.
766 */
767 e1000_config_collision_dist_generic(hw);
768
769 /*
770 * Configure Flow Control now that Auto-Neg has completed.
771 * First, we need to restore the desired flow control
772 * settings because we may have had to re-autoneg with a
773 * different link partner.
774 */
775 ret_val = e1000_config_fc_after_link_up_generic(hw);
776 if (ret_val)
777 DEBUGOUT("Error configuring flow control\n");
778
779 out:
780 return ret_val;
781 }
782
783 /**
784 * e1000_check_for_fiber_link_generic - Check for link (Fiber)
785 * @hw: pointer to the HW structure
786 *
787 * Checks for link up on the hardware. If link is not up and we have
788 * a signal, then we need to force link up.
789 **/
790 s32 e1000_check_for_fiber_link_generic(struct e1000_hw *hw)
791 {
792 struct e1000_mac_info *mac = &hw->mac;
793 u32 rxcw;
794 u32 ctrl;
795 u32 status;
796 s32 ret_val = E1000_SUCCESS;
797
798 DEBUGFUNC("e1000_check_for_fiber_link_generic");
799
800 ctrl = E1000_READ_REG(hw, E1000_CTRL);
801 status = E1000_READ_REG(hw, E1000_STATUS);
802 rxcw = E1000_READ_REG(hw, E1000_RXCW);
803
804 /*
805 * If we don't have link (auto-negotiation failed or link partner
806 * cannot auto-negotiate), the cable is plugged in (we have signal),
807 * and our link partner is not trying to auto-negotiate with us (we
808 * are receiving idles or data), we need to force link up. We also
809 * need to give auto-negotiation time to complete, in case the cable
810 * was just plugged in. The autoneg_failed flag does this.
811 */
812 /* (ctrl & E1000_CTRL_SWDPIN1) == 1 == have signal */
813 if ((ctrl & E1000_CTRL_SWDPIN1) && (!(status & E1000_STATUS_LU)) &&
814 (!(rxcw & E1000_RXCW_C))) {
815 if (mac->autoneg_failed == 0) {
816 mac->autoneg_failed = 1;
817 goto out;
818 }
819 DEBUGOUT("NOT RXing /C/, disable AutoNeg and force link.\n");
820
821 /* Disable auto-negotiation in the TXCW register */
822 E1000_WRITE_REG(hw, E1000_TXCW, (mac->txcw & ~E1000_TXCW_ANE));
823
824 /* Force link-up and also force full-duplex. */
825 ctrl = E1000_READ_REG(hw, E1000_CTRL);
826 ctrl |= (E1000_CTRL_SLU | E1000_CTRL_FD);
827 E1000_WRITE_REG(hw, E1000_CTRL, ctrl);
828
829 /* Configure Flow Control after forcing link up. */
830 ret_val = e1000_config_fc_after_link_up_generic(hw);
831 if (ret_val) {
832 DEBUGOUT("Error configuring flow control\n");
833 goto out;
834 }
835 } else if ((ctrl & E1000_CTRL_SLU) && (rxcw & E1000_RXCW_C)) {
836 /*
837 * If we are forcing link and we are receiving /C/ ordered
838 * sets, re-enable auto-negotiation in the TXCW register
839 * and disable forced link in the Device Control register
840 * in an attempt to auto-negotiate with our link partner.
841 */
842 DEBUGOUT("RXing /C/, enable AutoNeg and stop forcing link.\n");
843 E1000_WRITE_REG(hw, E1000_TXCW, mac->txcw);
844 E1000_WRITE_REG(hw, E1000_CTRL, (ctrl & ~E1000_CTRL_SLU));
845
846 mac->serdes_has_link = true;
847 }
848
849 out:
850 return ret_val;
851 }
852
853 /**
854 * e1000_check_for_serdes_link_generic - Check for link (Serdes)
855 * @hw: pointer to the HW structure
856 *
857 * Checks for link up on the hardware. If link is not up and we have
858 * a signal, then we need to force link up.
859 **/
860 s32 e1000_check_for_serdes_link_generic(struct e1000_hw *hw)
861 {
862 struct e1000_mac_info *mac = &hw->mac;
863 u32 rxcw;
864 u32 ctrl;
865 u32 status;
866 s32 ret_val = E1000_SUCCESS;
867
868 DEBUGFUNC("e1000_check_for_serdes_link_generic");
869
870 ctrl = E1000_READ_REG(hw, E1000_CTRL);
871 status = E1000_READ_REG(hw, E1000_STATUS);
872 rxcw = E1000_READ_REG(hw, E1000_RXCW);
873
874 /*
875 * If we don't have link (auto-negotiation failed or link partner
876 * cannot auto-negotiate), and our link partner is not trying to
877 * auto-negotiate with us (we are receiving idles or data),
878 * we need to force link up. We also need to give auto-negotiation
879 * time to complete.
880 */
881 /* (ctrl & E1000_CTRL_SWDPIN1) == 1 == have signal */
882 if ((!(status & E1000_STATUS_LU)) && (!(rxcw & E1000_RXCW_C))) {
883 if (mac->autoneg_failed == 0) {
884 mac->autoneg_failed = 1;
885 goto out;
886 }
887 DEBUGOUT("NOT RXing /C/, disable AutoNeg and force link.\n");
888
889 /* Disable auto-negotiation in the TXCW register */
890 E1000_WRITE_REG(hw, E1000_TXCW, (mac->txcw & ~E1000_TXCW_ANE));
891
892 /* Force link-up and also force full-duplex. */
893 ctrl = E1000_READ_REG(hw, E1000_CTRL);
894 ctrl |= (E1000_CTRL_SLU | E1000_CTRL_FD);
895 E1000_WRITE_REG(hw, E1000_CTRL, ctrl);
896
897 /* Configure Flow Control after forcing link up. */
898 ret_val = e1000_config_fc_after_link_up_generic(hw);
899 if (ret_val) {
900 DEBUGOUT("Error configuring flow control\n");
901 goto out;
902 }
903 } else if ((ctrl & E1000_CTRL_SLU) && (rxcw & E1000_RXCW_C)) {
904 /*
905 * If we are forcing link and we are receiving /C/ ordered
906 * sets, re-enable auto-negotiation in the TXCW register
907 * and disable forced link in the Device Control register
908 * in an attempt to auto-negotiate with our link partner.
909 */
910 DEBUGOUT("RXing /C/, enable AutoNeg and stop forcing link.\n");
911 E1000_WRITE_REG(hw, E1000_TXCW, mac->txcw);
912 E1000_WRITE_REG(hw, E1000_CTRL, (ctrl & ~E1000_CTRL_SLU));
913
914 mac->serdes_has_link = true;
915 } else if (!(E1000_TXCW_ANE & E1000_READ_REG(hw, E1000_TXCW))) {
916 /*
917 * If we force link for non-auto-negotiation switch, check
918 * link status based on MAC synchronization for internal
919 * serdes media type.
920 */
921 /* SYNCH bit and IV bit are sticky. */
922 usec_delay(10);
923 rxcw = E1000_READ_REG(hw, E1000_RXCW);
924 if (rxcw & E1000_RXCW_SYNCH) {
925 if (!(rxcw & E1000_RXCW_IV)) {
926 mac->serdes_has_link = true;
927 DEBUGOUT("SERDES: Link up - forced.\n");
928 }
929 } else {
930 mac->serdes_has_link = false;
931 DEBUGOUT("SERDES: Link down - force failed.\n");
932 }
933 }
934
935 if (E1000_TXCW_ANE & E1000_READ_REG(hw, E1000_TXCW)) {
936 status = E1000_READ_REG(hw, E1000_STATUS);
937 if (status & E1000_STATUS_LU) {
938 /* SYNCH bit and IV bit are sticky, so reread rxcw. */
939 usec_delay(10);
940 rxcw = E1000_READ_REG(hw, E1000_RXCW);
941 if (rxcw & E1000_RXCW_SYNCH) {
942 if (!(rxcw & E1000_RXCW_IV)) {
943 mac->serdes_has_link = true;
944 DEBUGOUT("SERDES: Link up - autoneg "
945 "completed sucessfully.\n");
946 } else {
947 mac->serdes_has_link = false;
948 DEBUGOUT("SERDES: Link down - invalid"
949 "codewords detected in autoneg.\n");
950 }
951 } else {
952 mac->serdes_has_link = false;
953 DEBUGOUT("SERDES: Link down - no sync.\n");
954 }
955 } else {
956 mac->serdes_has_link = false;
957 DEBUGOUT("SERDES: Link down - autoneg failed\n");
958 }
959 }
960
961 out:
962 return ret_val;
963 }
964
965 /**
966 * e1000_setup_link_generic - Setup flow control and link settings
967 * @hw: pointer to the HW structure
968 *
969 * Determines which flow control settings to use, then configures flow
970 * control. Calls the appropriate media-specific link configuration
971 * function. Assuming the adapter has a valid link partner, a valid link
972 * should be established. Assumes the hardware has previously been reset
973 * and the transmitter and receiver are not enabled.
974 **/
975 s32 e1000_setup_link_generic(struct e1000_hw *hw)
976 {
977 s32 ret_val = E1000_SUCCESS;
978
979 DEBUGFUNC("e1000_setup_link_generic");
980
981 /*
982 * In the case of the phy reset being blocked, we already have a link.
983 * We do not need to set it up again.
984 */
985 if (hw->phy.ops.check_reset_block)
986 if (hw->phy.ops.check_reset_block(hw))
987 goto out;
988
989 /*
990 * If requested flow control is set to default, set flow control
991 * based on the EEPROM flow control settings.
992 */
993 if (hw->fc.requested_mode == e1000_fc_default) {
994 ret_val = e1000_set_default_fc_generic(hw);
995 if (ret_val)
996 goto out;
997 }
998
999 /*
1000 * Save off the requested flow control mode for use later. Depending
1001 * on the link partner's capabilities, we may or may not use this mode.
1002 */
1003 hw->fc.current_mode = hw->fc.requested_mode;
1004
1005 DEBUGOUT1("After fix-ups FlowControl is now = %x\n",
1006 hw->fc.current_mode);
1007
1008 /* Call the necessary media_type subroutine to configure the link. */
1009 ret_val = hw->mac.ops.setup_physical_interface(hw);
1010 if (ret_val)
1011 goto out;
1012
1013 /*
1014 * Initialize the flow control address, type, and PAUSE timer
1015 * registers to their default values. This is done even if flow
1016 * control is disabled, because it does not hurt anything to
1017 * initialize these registers.
1018 */
1019 DEBUGOUT("Initializing the Flow Control address, type and timer regs\n");
1020 E1000_WRITE_REG(hw, E1000_FCT, FLOW_CONTROL_TYPE);
1021 E1000_WRITE_REG(hw, E1000_FCAH, FLOW_CONTROL_ADDRESS_HIGH);
1022 E1000_WRITE_REG(hw, E1000_FCAL, FLOW_CONTROL_ADDRESS_LOW);
1023
1024 E1000_WRITE_REG(hw, E1000_FCTTV, hw->fc.pause_time);
1025
1026 ret_val = e1000_set_fc_watermarks_generic(hw);
1027
1028 out:
1029 return ret_val;
1030 }
1031
1032 /**
1033 * e1000_setup_fiber_serdes_link_generic - Setup link for fiber/serdes
1034 * @hw: pointer to the HW structure
1035 *
1036 * Configures collision distance and flow control for fiber and serdes
1037 * links. Upon successful setup, poll for link.
1038 **/
1039 s32 e1000_setup_fiber_serdes_link_generic(struct e1000_hw *hw)
1040 {
1041 u32 ctrl;
1042 s32 ret_val = E1000_SUCCESS;
1043
1044 DEBUGFUNC("e1000_setup_fiber_serdes_link_generic");
1045
1046 ctrl = E1000_READ_REG(hw, E1000_CTRL);
1047
1048 /* Take the link out of reset */
1049 ctrl &= ~E1000_CTRL_LRST;
1050
1051 e1000_config_collision_dist_generic(hw);
1052
1053 ret_val = e1000_commit_fc_settings_generic(hw);
1054 if (ret_val)
1055 goto out;
1056
1057 /*
1058 * Since auto-negotiation is enabled, take the link out of reset (the
1059 * link will be in reset, because we previously reset the chip). This
1060 * will restart auto-negotiation. If auto-negotiation is successful
1061 * then the link-up status bit will be set and the flow control enable
1062 * bits (RFCE and TFCE) will be set according to their negotiated value.
1063 */
1064 DEBUGOUT("Auto-negotiation enabled\n");
1065
1066 E1000_WRITE_REG(hw, E1000_CTRL, ctrl);
1067 E1000_WRITE_FLUSH(hw);
1068 msec_delay(1);
1069
1070 /*
1071 * For these adapters, the SW definable pin 1 is set when the optics
1072 * detect a signal. If we have a signal, then poll for a "Link-Up"
1073 * indication.
1074 */
1075 if (hw->phy.media_type == e1000_media_type_internal_serdes ||
1076 (E1000_READ_REG(hw, E1000_CTRL) & E1000_CTRL_SWDPIN1)) {
1077 ret_val = e1000_poll_fiber_serdes_link_generic(hw);
1078 } else {
1079 DEBUGOUT("No signal detected\n");
1080 }
1081
1082 out:
1083 return ret_val;
1084 }
1085
1086 /**
1087 * e1000_config_collision_dist_generic - Configure collision distance
1088 * @hw: pointer to the HW structure
1089 *
1090 * Configures the collision distance to the default value and is used
1091 * during link setup. Currently no func pointer exists and all
1092 * implementations are handled in the generic version of this function.
1093 **/
1094 void e1000_config_collision_dist_generic(struct e1000_hw *hw)
1095 {
1096 u32 tctl;
1097
1098 DEBUGFUNC("e1000_config_collision_dist_generic");
1099
1100 tctl = E1000_READ_REG(hw, E1000_TCTL);
1101
1102 tctl &= ~E1000_TCTL_COLD;
1103 tctl |= E1000_COLLISION_DISTANCE << E1000_COLD_SHIFT;
1104
1105 E1000_WRITE_REG(hw, E1000_TCTL, tctl);
1106 E1000_WRITE_FLUSH(hw);
1107 }
1108
1109 /**
1110 * e1000_poll_fiber_serdes_link_generic - Poll for link up
1111 * @hw: pointer to the HW structure
1112 *
1113 * Polls for link up by reading the status register, if link fails to come
1114 * up with auto-negotiation, then the link is forced if a signal is detected.
1115 **/
1116 s32 e1000_poll_fiber_serdes_link_generic(struct e1000_hw *hw)
1117 {
1118 struct e1000_mac_info *mac = &hw->mac;
1119 u32 i, status;
1120 s32 ret_val = E1000_SUCCESS;
1121
1122 DEBUGFUNC("e1000_poll_fiber_serdes_link_generic");
1123
1124 /*
1125 * If we have a signal (the cable is plugged in, or assumed true for
1126 * serdes media) then poll for a "Link-Up" indication in the Device
1127 * Status Register. Time-out if a link isn't seen in 500 milliseconds
1128 * seconds (Auto-negotiation should complete in less than 500
1129 * milliseconds even if the other end is doing it in SW).
1130 */
1131 for (i = 0; i < FIBER_LINK_UP_LIMIT; i++) {
1132 msec_delay(10);
1133 status = E1000_READ_REG(hw, E1000_STATUS);
1134 if (status & E1000_STATUS_LU)
1135 break;
1136 }
1137 if (i == FIBER_LINK_UP_LIMIT) {
1138 DEBUGOUT("Never got a valid link from auto-neg!!!\n");
1139 mac->autoneg_failed = 1;
1140 /*
1141 * AutoNeg failed to achieve a link, so we'll call
1142 * mac->check_for_link. This routine will force the
1143 * link up if we detect a signal. This will allow us to
1144 * communicate with non-autonegotiating link partners.
1145 */
1146 ret_val = hw->mac.ops.check_for_link(hw);
1147 if (ret_val) {
1148 DEBUGOUT("Error while checking for link\n");
1149 goto out;
1150 }
1151 mac->autoneg_failed = 0;
1152 } else {
1153 mac->autoneg_failed = 0;
1154 DEBUGOUT("Valid Link Found\n");
1155 }
1156
1157 out:
1158 return ret_val;
1159 }
1160
1161 /**
1162 * e1000_commit_fc_settings_generic - Configure flow control
1163 * @hw: pointer to the HW structure
1164 *
1165 * Write the flow control settings to the Transmit Config Word Register (TXCW)
1166 * base on the flow control settings in e1000_mac_info.
1167 **/
1168 s32 e1000_commit_fc_settings_generic(struct e1000_hw *hw)
1169 {
1170 struct e1000_mac_info *mac = &hw->mac;
1171 u32 txcw;
1172 s32 ret_val = E1000_SUCCESS;
1173
1174 DEBUGFUNC("e1000_commit_fc_settings_generic");
1175
1176 /*
1177 * Check for a software override of the flow control settings, and
1178 * setup the device accordingly. If auto-negotiation is enabled, then
1179 * software will have to set the "PAUSE" bits to the correct value in
1180 * the Transmit Config Word Register (TXCW) and re-start auto-
1181 * negotiation. However, if auto-negotiation is disabled, then
1182 * software will have to manually configure the two flow control enable
1183 * bits in the CTRL register.
1184 *
1185 * The possible values of the "fc" parameter are:
1186 * 0: Flow control is completely disabled
1187 * 1: Rx flow control is enabled (we can receive pause frames,
1188 * but not send pause frames).
1189 * 2: Tx flow control is enabled (we can send pause frames but we
1190 * do not support receiving pause frames).
1191 * 3: Both Rx and Tx flow control (symmetric) are enabled.
1192 */
1193 switch (hw->fc.current_mode) {
1194 case e1000_fc_none:
1195 /* Flow control completely disabled by a software over-ride. */
1196 txcw = (E1000_TXCW_ANE | E1000_TXCW_FD);
1197 break;
1198 case e1000_fc_rx_pause:
1199 /*
1200 * Rx Flow control is enabled and Tx Flow control is disabled
1201 * by a software over-ride. Since there really isn't a way to
1202 * advertise that we are capable of Rx Pause ONLY, we will
1203 * advertise that we support both symmetric and asymmetric RX
1204 * PAUSE. Later, we will disable the adapter's ability to send
1205 * PAUSE frames.
1206 */
1207 txcw = (E1000_TXCW_ANE | E1000_TXCW_FD | E1000_TXCW_PAUSE_MASK);
1208 break;
1209 case e1000_fc_tx_pause:
1210 /*
1211 * Tx Flow control is enabled, and Rx Flow control is disabled,
1212 * by a software over-ride.
1213 */
1214 txcw = (E1000_TXCW_ANE | E1000_TXCW_FD | E1000_TXCW_ASM_DIR);
1215 break;
1216 case e1000_fc_full:
1217 /*
1218 * Flow control (both Rx and Tx) is enabled by a software
1219 * over-ride.
1220 */
1221 txcw = (E1000_TXCW_ANE | E1000_TXCW_FD | E1000_TXCW_PAUSE_MASK);
1222 break;
1223 default:
1224 DEBUGOUT("Flow control param set incorrectly\n");
1225 ret_val = -E1000_ERR_CONFIG;
1226 goto out;
1227 break;
1228 }
1229
1230 E1000_WRITE_REG(hw, E1000_TXCW, txcw);
1231 mac->txcw = txcw;
1232
1233 out:
1234 return ret_val;
1235 }
1236
1237 /**
1238 * e1000_set_fc_watermarks_generic - Set flow control high/low watermarks
1239 * @hw: pointer to the HW structure
1240 *
1241 * Sets the flow control high/low threshold (watermark) registers. If
1242 * flow control XON frame transmission is enabled, then set XON frame
1243 * transmission as well.
1244 **/
1245 s32 e1000_set_fc_watermarks_generic(struct e1000_hw *hw)
1246 {
1247 s32 ret_val = E1000_SUCCESS;
1248 u32 fcrtl = 0, fcrth = 0;
1249
1250 DEBUGFUNC("e1000_set_fc_watermarks_generic");
1251
1252 /*
1253 * Set the flow control receive threshold registers. Normally,
1254 * these registers will be set to a default threshold that may be
1255 * adjusted later by the driver's runtime code. However, if the
1256 * ability to transmit pause frames is not enabled, then these
1257 * registers will be set to 0.
1258 */
1259 if (hw->fc.current_mode & e1000_fc_tx_pause) {
1260 /*
1261 * We need to set up the Receive Threshold high and low water
1262 * marks as well as (optionally) enabling the transmission of
1263 * XON frames.
1264 */
1265 fcrtl = hw->fc.low_water;
1266 if (hw->fc.send_xon)
1267 fcrtl |= E1000_FCRTL_XONE;
1268
1269 fcrth = hw->fc.high_water;
1270 }
1271 E1000_WRITE_REG(hw, E1000_FCRTL, fcrtl);
1272 E1000_WRITE_REG(hw, E1000_FCRTH, fcrth);
1273
1274 return ret_val;
1275 }
1276
1277 /**
1278 * e1000_set_default_fc_generic - Set flow control default values
1279 * @hw: pointer to the HW structure
1280 *
1281 * Read the EEPROM for the default values for flow control and store the
1282 * values.
1283 **/
1284 s32 e1000_set_default_fc_generic(struct e1000_hw *hw)
1285 {
1286 s32 ret_val = E1000_SUCCESS;
1287 u16 nvm_data;
1288
1289 DEBUGFUNC("e1000_set_default_fc_generic");
1290
1291 /*
1292 * Read and store word 0x0F of the EEPROM. This word contains bits
1293 * that determine the hardware's default PAUSE (flow control) mode,
1294 * a bit that determines whether the HW defaults to enabling or
1295 * disabling auto-negotiation, and the direction of the
1296 * SW defined pins. If there is no SW over-ride of the flow
1297 * control setting, then the variable hw->fc will
1298 * be initialized based on a value in the EEPROM.
1299 */
1300 ret_val = hw->nvm.ops.read(hw, NVM_INIT_CONTROL2_REG, 1, &nvm_data);
1301
1302 if (ret_val) {
1303 DEBUGOUT("NVM Read Error\n");
1304 goto out;
1305 }
1306
1307 if ((nvm_data & NVM_WORD0F_PAUSE_MASK) == 0)
1308 hw->fc.requested_mode = e1000_fc_none;
1309 else if ((nvm_data & NVM_WORD0F_PAUSE_MASK) ==
1310 NVM_WORD0F_ASM_DIR)
1311 hw->fc.requested_mode = e1000_fc_tx_pause;
1312 else
1313 hw->fc.requested_mode = e1000_fc_full;
1314
1315 out:
1316 return ret_val;
1317 }
1318
1319 /**
1320 * e1000_force_mac_fc_generic - Force the MAC's flow control settings
1321 * @hw: pointer to the HW structure
1322 *
1323 * Force the MAC's flow control settings. Sets the TFCE and RFCE bits in the
1324 * device control register to reflect the adapter settings. TFCE and RFCE
1325 * need to be explicitly set by software when a copper PHY is used because
1326 * autonegotiation is managed by the PHY rather than the MAC. Software must
1327 * also configure these bits when link is forced on a fiber connection.
1328 **/
1329 s32 e1000_force_mac_fc_generic(struct e1000_hw *hw)
1330 {
1331 u32 ctrl;
1332 s32 ret_val = E1000_SUCCESS;
1333
1334 DEBUGFUNC("e1000_force_mac_fc_generic");
1335
1336 ctrl = E1000_READ_REG(hw, E1000_CTRL);
1337
1338 /*
1339 * Because we didn't get link via the internal auto-negotiation
1340 * mechanism (we either forced link or we got link via PHY
1341 * auto-neg), we have to manually enable/disable transmit an
1342 * receive flow control.
1343 *
1344 * The "Case" statement below enables/disable flow control
1345 * according to the "hw->fc.current_mode" parameter.
1346 *
1347 * The possible values of the "fc" parameter are:
1348 * 0: Flow control is completely disabled
1349 * 1: Rx flow control is enabled (we can receive pause
1350 * frames but not send pause frames).
1351 * 2: Tx flow control is enabled (we can send pause frames
1352 * frames but we do not receive pause frames).
1353 * 3: Both Rx and Tx flow control (symmetric) is enabled.
1354 * other: No other values should be possible at this point.
1355 */
1356 DEBUGOUT1("hw->fc.current_mode = %u\n", hw->fc.current_mode);
1357
1358 switch (hw->fc.current_mode) {
1359 case e1000_fc_none:
1360 ctrl &= (~(E1000_CTRL_TFCE | E1000_CTRL_RFCE));
1361 break;
1362 case e1000_fc_rx_pause:
1363 ctrl &= (~E1000_CTRL_TFCE);
1364 ctrl |= E1000_CTRL_RFCE;
1365 break;
1366 case e1000_fc_tx_pause:
1367 ctrl &= (~E1000_CTRL_RFCE);
1368 ctrl |= E1000_CTRL_TFCE;
1369 break;
1370 case e1000_fc_full:
1371 ctrl |= (E1000_CTRL_TFCE | E1000_CTRL_RFCE);
1372 break;
1373 default:
1374 DEBUGOUT("Flow control param set incorrectly\n");
1375 ret_val = -E1000_ERR_CONFIG;
1376 goto out;
1377 }
1378
1379 E1000_WRITE_REG(hw, E1000_CTRL, ctrl);
1380
1381 out:
1382 return ret_val;
1383 }
1384
1385 /**
1386 * e1000_config_fc_after_link_up_generic - Configures flow control after link
1387 * @hw: pointer to the HW structure
1388 *
1389 * Checks the status of auto-negotiation after link up to ensure that the
1390 * speed and duplex were not forced. If the link needed to be forced, then
1391 * flow control needs to be forced also. If auto-negotiation is enabled
1392 * and did not fail, then we configure flow control based on our link
1393 * partner.
1394 **/
1395 s32 e1000_config_fc_after_link_up_generic(struct e1000_hw *hw)
1396 {
1397 struct e1000_mac_info *mac = &hw->mac;
1398 s32 ret_val = E1000_SUCCESS;
1399 u16 mii_status_reg, mii_nway_adv_reg, mii_nway_lp_ability_reg;
1400 u16 speed, duplex;
1401
1402 DEBUGFUNC("e1000_config_fc_after_link_up_generic");
1403
1404 /*
1405 * Check for the case where we have fiber media and auto-neg failed
1406 * so we had to force link. In this case, we need to force the
1407 * configuration of the MAC to match the "fc" parameter.
1408 */
1409 if (mac->autoneg_failed) {
1410 if (hw->phy.media_type == e1000_media_type_fiber ||
1411 hw->phy.media_type == e1000_media_type_internal_serdes)
1412 ret_val = e1000_force_mac_fc_generic(hw);
1413 } else {
1414 if (hw->phy.media_type == e1000_media_type_copper)
1415 ret_val = e1000_force_mac_fc_generic(hw);
1416 }
1417
1418 if (ret_val) {
1419 DEBUGOUT("Error forcing flow control settings\n");
1420 goto out;
1421 }
1422
1423 /*
1424 * Check for the case where we have copper media and auto-neg is
1425 * enabled. In this case, we need to check and see if Auto-Neg
1426 * has completed, and if so, how the PHY and link partner has
1427 * flow control configured.
1428 */
1429 if ((hw->phy.media_type == e1000_media_type_copper) && mac->autoneg) {
1430 /*
1431 * Read the MII Status Register and check to see if AutoNeg
1432 * has completed. We read this twice because this reg has
1433 * some "sticky" (latched) bits.
1434 */
1435 ret_val = hw->phy.ops.read_reg(hw, PHY_STATUS, &mii_status_reg);
1436 if (ret_val)
1437 goto out;
1438 ret_val = hw->phy.ops.read_reg(hw, PHY_STATUS, &mii_status_reg);
1439 if (ret_val)
1440 goto out;
1441
1442 if (!(mii_status_reg & MII_SR_AUTONEG_COMPLETE)) {
1443 DEBUGOUT("Copper PHY and Auto Neg "
1444 "has not completed.\n");
1445 goto out;
1446 }
1447
1448 /*
1449 * The AutoNeg process has completed, so we now need to
1450 * read both the Auto Negotiation Advertisement
1451 * Register (Address 4) and the Auto_Negotiation Base
1452 * Page Ability Register (Address 5) to determine how
1453 * flow control was negotiated.
1454 */
1455 ret_val = hw->phy.ops.read_reg(hw, PHY_AUTONEG_ADV,
1456 &mii_nway_adv_reg);
1457 if (ret_val)
1458 goto out;
1459 ret_val = hw->phy.ops.read_reg(hw, PHY_LP_ABILITY,
1460 &mii_nway_lp_ability_reg);
1461 if (ret_val)
1462 goto out;
1463
1464 /*
1465 * Two bits in the Auto Negotiation Advertisement Register
1466 * (Address 4) and two bits in the Auto Negotiation Base
1467 * Page Ability Register (Address 5) determine flow control
1468 * for both the PHY and the link partner. The following
1469 * table, taken out of the IEEE 802.3ab/D6.0 dated March 25,
1470 * 1999, describes these PAUSE resolution bits and how flow
1471 * control is determined based upon these settings.
1472 * NOTE: DC = Don't Care
1473 *
1474 * LOCAL DEVICE | LINK PARTNER
1475 * PAUSE | ASM_DIR | PAUSE | ASM_DIR | NIC Resolution
1476 *-------|---------|-------|---------|--------------------
1477 * 0 | 0 | DC | DC | e1000_fc_none
1478 * 0 | 1 | 0 | DC | e1000_fc_none
1479 * 0 | 1 | 1 | 0 | e1000_fc_none
1480 * 0 | 1 | 1 | 1 | e1000_fc_tx_pause
1481 * 1 | 0 | 0 | DC | e1000_fc_none
1482 * 1 | DC | 1 | DC | e1000_fc_full
1483 * 1 | 1 | 0 | 0 | e1000_fc_none
1484 * 1 | 1 | 0 | 1 | e1000_fc_rx_pause
1485 *
1486 * Are both PAUSE bits set to 1? If so, this implies
1487 * Symmetric Flow Control is enabled at both ends. The
1488 * ASM_DIR bits are irrelevant per the spec.
1489 *
1490 * For Symmetric Flow Control:
1491 *
1492 * LOCAL DEVICE | LINK PARTNER
1493 * PAUSE | ASM_DIR | PAUSE | ASM_DIR | Result
1494 *-------|---------|-------|---------|--------------------
1495 * 1 | DC | 1 | DC | E1000_fc_full
1496 *
1497 */
1498 if ((mii_nway_adv_reg & NWAY_AR_PAUSE) &&
1499 (mii_nway_lp_ability_reg & NWAY_LPAR_PAUSE)) {
1500 /*
1501 * Now we need to check if the user selected Rx ONLY
1502 * of pause frames. In this case, we had to advertise
1503 * FULL flow control because we could not advertise RX
1504 * ONLY. Hence, we must now check to see if we need to
1505 * turn OFF the TRANSMISSION of PAUSE frames.
1506 */
1507 if (hw->fc.requested_mode == e1000_fc_full) {
1508 hw->fc.current_mode = e1000_fc_full;
1509 DEBUGOUT("Flow Control = FULL.\r\n");
1510 } else {
1511 hw->fc.current_mode = e1000_fc_rx_pause;
1512 DEBUGOUT("Flow Control = "
1513 "RX PAUSE frames only.\r\n");
1514 }
1515 }
1516 /*
1517 * For receiving PAUSE frames ONLY.
1518 *
1519 * LOCAL DEVICE | LINK PARTNER
1520 * PAUSE | ASM_DIR | PAUSE | ASM_DIR | Result
1521 *-------|---------|-------|---------|--------------------
1522 * 0 | 1 | 1 | 1 | e1000_fc_tx_pause
1523 */
1524 else if (!(mii_nway_adv_reg & NWAY_AR_PAUSE) &&
1525 (mii_nway_adv_reg & NWAY_AR_ASM_DIR) &&
1526 (mii_nway_lp_ability_reg & NWAY_LPAR_PAUSE) &&
1527 (mii_nway_lp_ability_reg & NWAY_LPAR_ASM_DIR)) {
1528 hw->fc.current_mode = e1000_fc_tx_pause;
1529 DEBUGOUT("Flow Control = TX PAUSE frames only.\r\n");
1530 }
1531 /*
1532 * For transmitting PAUSE frames ONLY.
1533 *
1534 * LOCAL DEVICE | LINK PARTNER
1535 * PAUSE | ASM_DIR | PAUSE | ASM_DIR | Result
1536 *-------|---------|-------|---------|--------------------
1537 * 1 | 1 | 0 | 1 | e1000_fc_rx_pause
1538 */
1539 else if ((mii_nway_adv_reg & NWAY_AR_PAUSE) &&
1540 (mii_nway_adv_reg & NWAY_AR_ASM_DIR) &&
1541 !(mii_nway_lp_ability_reg & NWAY_LPAR_PAUSE) &&
1542 (mii_nway_lp_ability_reg & NWAY_LPAR_ASM_DIR)) {
1543 hw->fc.current_mode = e1000_fc_rx_pause;
1544 DEBUGOUT("Flow Control = RX PAUSE frames only.\r\n");
1545 } else {
1546 /*
1547 * Per the IEEE spec, at this point flow control
1548 * should be disabled.
1549 */
1550 hw->fc.current_mode = e1000_fc_none;
1551 DEBUGOUT("Flow Control = NONE.\r\n");
1552 }
1553
1554 /*
1555 * Now we need to do one last check... If we auto-
1556 * negotiated to HALF DUPLEX, flow control should not be
1557 * enabled per IEEE 802.3 spec.
1558 */
1559 ret_val = mac->ops.get_link_up_info(hw, &speed, &duplex);
1560 if (ret_val) {
1561 DEBUGOUT("Error getting link speed and duplex\n");
1562 goto out;
1563 }
1564
1565 if (duplex == HALF_DUPLEX)
1566 hw->fc.current_mode = e1000_fc_none;
1567
1568 /*
1569 * Now we call a subroutine to actually force the MAC
1570 * controller to use the correct flow control settings.
1571 */
1572 ret_val = e1000_force_mac_fc_generic(hw);
1573 if (ret_val) {
1574 DEBUGOUT("Error forcing flow control settings\n");
1575 goto out;
1576 }
1577 }
1578
1579 out:
1580 return ret_val;
1581 }
1582
1583 /**
1584 * e1000_get_speed_and_duplex_copper_generic - Retrieve current speed/duplex
1585 * @hw: pointer to the HW structure
1586 * @speed: stores the current speed
1587 * @duplex: stores the current duplex
1588 *
1589 * Read the status register for the current speed/duplex and store the current
1590 * speed and duplex for copper connections.
1591 **/
1592 s32 e1000_get_speed_and_duplex_copper_generic(struct e1000_hw *hw, u16 *speed,
1593 u16 *duplex)
1594 {
1595 u32 status;
1596
1597 DEBUGFUNC("e1000_get_speed_and_duplex_copper_generic");
1598
1599 status = E1000_READ_REG(hw, E1000_STATUS);
1600 if (status & E1000_STATUS_SPEED_1000) {
1601 *speed = SPEED_1000;
1602 DEBUGOUT("1000 Mbs, ");
1603 } else if (status & E1000_STATUS_SPEED_100) {
1604 *speed = SPEED_100;
1605 DEBUGOUT("100 Mbs, ");
1606 } else {
1607 *speed = SPEED_10;
1608 DEBUGOUT("10 Mbs, ");
1609 }
1610
1611 if (status & E1000_STATUS_FD) {
1612 *duplex = FULL_DUPLEX;
1613 DEBUGOUT("Full Duplex\n");
1614 } else {
1615 *duplex = HALF_DUPLEX;
1616 DEBUGOUT("Half Duplex\n");
1617 }
1618
1619 return E1000_SUCCESS;
1620 }
1621
1622 /**
1623 * e1000_get_speed_and_duplex_fiber_generic - Retrieve current speed/duplex
1624 * @hw: pointer to the HW structure
1625 * @speed: stores the current speed
1626 * @duplex: stores the current duplex
1627 *
1628 * Sets the speed and duplex to gigabit full duplex (the only possible option)
1629 * for fiber/serdes links.
1630 **/
1631 s32 e1000_get_speed_and_duplex_fiber_serdes_generic(struct e1000_hw *hw,
1632 u16 *speed, u16 *duplex)
1633 {
1634 DEBUGFUNC("e1000_get_speed_and_duplex_fiber_serdes_generic");
1635
1636 *speed = SPEED_1000;
1637 *duplex = FULL_DUPLEX;
1638
1639 return E1000_SUCCESS;
1640 }
1641
1642 /**
1643 * e1000_get_hw_semaphore_generic - Acquire hardware semaphore
1644 * @hw: pointer to the HW structure
1645 *
1646 * Acquire the HW semaphore to access the PHY or NVM
1647 **/
1648 s32 e1000_get_hw_semaphore_generic(struct e1000_hw *hw)
1649 {
1650 u32 swsm;
1651 s32 ret_val = E1000_SUCCESS;
1652 s32 timeout = hw->nvm.word_size + 1;
1653 s32 i = 0;
1654
1655 DEBUGFUNC("e1000_get_hw_semaphore_generic");
1656
1657 /* Get the SW semaphore */
1658 while (i < timeout) {
1659 swsm = E1000_READ_REG(hw, E1000_SWSM);
1660 if (!(swsm & E1000_SWSM_SMBI))
1661 break;
1662
1663 usec_delay(50);
1664 i++;
1665 }
1666
1667 if (i == timeout) {
1668 DEBUGOUT("Driver can't access device - SMBI bit is set.\n");
1669 ret_val = -E1000_ERR_NVM;
1670 goto out;
1671 }
1672
1673 /* Get the FW semaphore. */
1674 for (i = 0; i < timeout; i++) {
1675 swsm = E1000_READ_REG(hw, E1000_SWSM);
1676 E1000_WRITE_REG(hw, E1000_SWSM, swsm | E1000_SWSM_SWESMBI);
1677
1678 /* Semaphore acquired if bit latched */
1679 if (E1000_READ_REG(hw, E1000_SWSM) & E1000_SWSM_SWESMBI)
1680 break;
1681
1682 usec_delay(50);
1683 }
1684
1685 if (i == timeout) {
1686 /* Release semaphores */
1687 e1000_put_hw_semaphore_generic(hw);
1688 DEBUGOUT("Driver can't access the NVM\n");
1689 ret_val = -E1000_ERR_NVM;
1690 goto out;
1691 }
1692
1693 out:
1694 return ret_val;
1695 }
1696
1697 /**
1698 * e1000_put_hw_semaphore_generic - Release hardware semaphore
1699 * @hw: pointer to the HW structure
1700 *
1701 * Release hardware semaphore used to access the PHY or NVM
1702 **/
1703 void e1000_put_hw_semaphore_generic(struct e1000_hw *hw)
1704 {
1705 u32 swsm;
1706
1707 DEBUGFUNC("e1000_put_hw_semaphore_generic");
1708
1709 swsm = E1000_READ_REG(hw, E1000_SWSM);
1710
1711 swsm &= ~(E1000_SWSM_SMBI | E1000_SWSM_SWESMBI);
1712
1713 E1000_WRITE_REG(hw, E1000_SWSM, swsm);
1714 }
1715
1716 /**
1717 * e1000_get_auto_rd_done_generic - Check for auto read completion
1718 * @hw: pointer to the HW structure
1719 *
1720 * Check EEPROM for Auto Read done bit.
1721 **/
1722 s32 e1000_get_auto_rd_done_generic(struct e1000_hw *hw)
1723 {
1724 s32 i = 0;
1725 s32 ret_val = E1000_SUCCESS;
1726
1727 DEBUGFUNC("e1000_get_auto_rd_done_generic");
1728
1729 while (i < AUTO_READ_DONE_TIMEOUT) {
1730 if (E1000_READ_REG(hw, E1000_EECD) & E1000_EECD_AUTO_RD)
1731 break;
1732 msec_delay(1);
1733 i++;
1734 }
1735
1736 if (i == AUTO_READ_DONE_TIMEOUT) {
1737 DEBUGOUT("Auto read by HW from NVM has not completed.\n");
1738 ret_val = -E1000_ERR_RESET;
1739 goto out;
1740 }
1741
1742 out:
1743 return ret_val;
1744 }
1745
1746 /**
1747 * e1000_valid_led_default_generic - Verify a valid default LED config
1748 * @hw: pointer to the HW structure
1749 * @data: pointer to the NVM (EEPROM)
1750 *
1751 * Read the EEPROM for the current default LED configuration. If the
1752 * LED configuration is not valid, set to a valid LED configuration.
1753 **/
1754 s32 e1000_valid_led_default_generic(struct e1000_hw *hw, u16 *data)
1755 {
1756 s32 ret_val;
1757
1758 DEBUGFUNC("e1000_valid_led_default_generic");
1759
1760 ret_val = hw->nvm.ops.read(hw, NVM_ID_LED_SETTINGS, 1, data);
1761 if (ret_val) {
1762 DEBUGOUT("NVM Read Error\n");
1763 goto out;
1764 }
1765
1766 if (*data == ID_LED_RESERVED_0000 || *data == ID_LED_RESERVED_FFFF)
1767 *data = ID_LED_DEFAULT;
1768
1769 out:
1770 return ret_val;
1771 }
1772
1773 /**
1774 * e1000_id_led_init_generic -
1775 * @hw: pointer to the HW structure
1776 *
1777 **/
1778 s32 e1000_id_led_init_generic(struct e1000_hw *hw)
1779 {
1780 struct e1000_mac_info *mac = &hw->mac;
1781 s32 ret_val;
1782 const u32 ledctl_mask = 0x000000FF;
1783 const u32 ledctl_on = E1000_LEDCTL_MODE_LED_ON;
1784 const u32 ledctl_off = E1000_LEDCTL_MODE_LED_OFF;
1785 u16 data, i, temp;
1786 const u16 led_mask = 0x0F;
1787
1788 DEBUGFUNC("e1000_id_led_init_generic");
1789
1790 ret_val = hw->nvm.ops.valid_led_default(hw, &data);
1791 if (ret_val)
1792 goto out;
1793
1794 mac->ledctl_default = E1000_READ_REG(hw, E1000_LEDCTL);
1795 mac->ledctl_mode1 = mac->ledctl_default;
1796 mac->ledctl_mode2 = mac->ledctl_default;
1797
1798 for (i = 0; i < 4; i++) {
1799 temp = (data >> (i << 2)) & led_mask;
1800 switch (temp) {
1801 case ID_LED_ON1_DEF2:
1802 case ID_LED_ON1_ON2:
1803 case ID_LED_ON1_OFF2:
1804 mac->ledctl_mode1 &= ~(ledctl_mask << (i << 3));
1805 mac->ledctl_mode1 |= ledctl_on << (i << 3);
1806 break;
1807 case ID_LED_OFF1_DEF2:
1808 case ID_LED_OFF1_ON2:
1809 case ID_LED_OFF1_OFF2:
1810 mac->ledctl_mode1 &= ~(ledctl_mask << (i << 3));
1811 mac->ledctl_mode1 |= ledctl_off << (i << 3);
1812 break;
1813 default:
1814 /* Do nothing */
1815 break;
1816 }
1817 switch (temp) {
1818 case ID_LED_DEF1_ON2:
1819 case ID_LED_ON1_ON2:
1820 case ID_LED_OFF1_ON2:
1821 mac->ledctl_mode2 &= ~(ledctl_mask << (i << 3));
1822 mac->ledctl_mode2 |= ledctl_on << (i << 3);
1823 break;
1824 case ID_LED_DEF1_OFF2:
1825 case ID_LED_ON1_OFF2:
1826 case ID_LED_OFF1_OFF2:
1827 mac->ledctl_mode2 &= ~(ledctl_mask << (i << 3));
1828 mac->ledctl_mode2 |= ledctl_off << (i << 3);
1829 break;
1830 default:
1831 /* Do nothing */
1832 break;
1833 }
1834 }
1835
1836 out:
1837 return ret_val;
1838 }
1839
1840 /**
1841 * e1000_setup_led_generic - Configures SW controllable LED
1842 * @hw: pointer to the HW structure
1843 *
1844 * This prepares the SW controllable LED for use and saves the current state
1845 * of the LED so it can be later restored.
1846 **/
1847 s32 e1000_setup_led_generic(struct e1000_hw *hw)
1848 {
1849 u32 ledctl;
1850 s32 ret_val = E1000_SUCCESS;
1851
1852 DEBUGFUNC("e1000_setup_led_generic");
1853
1854 if (hw->mac.ops.setup_led != e1000_setup_led_generic) {
1855 ret_val = -E1000_ERR_CONFIG;
1856 goto out;
1857 }
1858
1859 if (hw->phy.media_type == e1000_media_type_fiber) {
1860 ledctl = E1000_READ_REG(hw, E1000_LEDCTL);
1861 hw->mac.ledctl_default = ledctl;
1862 /* Turn off LED0 */
1863 ledctl &= ~(E1000_LEDCTL_LED0_IVRT |
1864 E1000_LEDCTL_LED0_BLINK |
1865 E1000_LEDCTL_LED0_MODE_MASK);
1866 ledctl |= (E1000_LEDCTL_MODE_LED_OFF <<
1867 E1000_LEDCTL_LED0_MODE_SHIFT);
1868 E1000_WRITE_REG(hw, E1000_LEDCTL, ledctl);
1869 } else if (hw->phy.media_type == e1000_media_type_copper) {
1870 E1000_WRITE_REG(hw, E1000_LEDCTL, hw->mac.ledctl_mode1);
1871 }
1872
1873 out:
1874 return ret_val;
1875 }
1876
1877 /**
1878 * e1000_cleanup_led_generic - Set LED config to default operation
1879 * @hw: pointer to the HW structure
1880 *
1881 * Remove the current LED configuration and set the LED configuration
1882 * to the default value, saved from the EEPROM.
1883 **/
1884 s32 e1000_cleanup_led_generic(struct e1000_hw *hw)
1885 {
1886 s32 ret_val = E1000_SUCCESS;
1887
1888 DEBUGFUNC("e1000_cleanup_led_generic");
1889
1890 if (hw->mac.ops.cleanup_led != e1000_cleanup_led_generic) {
1891 ret_val = -E1000_ERR_CONFIG;
1892 goto out;
1893 }
1894
1895 E1000_WRITE_REG(hw, E1000_LEDCTL, hw->mac.ledctl_default);
1896
1897 out:
1898 return ret_val;
1899 }
1900
1901 /**
1902 * e1000_blink_led_generic - Blink LED
1903 * @hw: pointer to the HW structure
1904 *
1905 * Blink the LEDs which are set to be on.
1906 **/
1907 s32 e1000_blink_led_generic(struct e1000_hw *hw)
1908 {
1909 u32 ledctl_blink = 0;
1910 u32 i;
1911
1912 DEBUGFUNC("e1000_blink_led_generic");
1913
1914 if (hw->phy.media_type == e1000_media_type_fiber) {
1915 /* always blink LED0 for PCI-E fiber */
1916 ledctl_blink = E1000_LEDCTL_LED0_BLINK |
1917 (E1000_LEDCTL_MODE_LED_ON << E1000_LEDCTL_LED0_MODE_SHIFT);
1918 } else {
1919 /*
1920 * set the blink bit for each LED that's "on" (0x0E)
1921 * in ledctl_mode2
1922 */
1923 ledctl_blink = hw->mac.ledctl_mode2;
1924 for (i = 0; i < 4; i++)
1925 if (((hw->mac.ledctl_mode2 >> (i * 8)) & 0xFF) ==
1926 E1000_LEDCTL_MODE_LED_ON)
1927 ledctl_blink |= (E1000_LEDCTL_LED0_BLINK <<
1928 (i * 8));
1929 }
1930
1931 E1000_WRITE_REG(hw, E1000_LEDCTL, ledctl_blink);
1932
1933 return E1000_SUCCESS;
1934 }
1935
1936 /**
1937 * e1000_led_on_generic - Turn LED on
1938 * @hw: pointer to the HW structure
1939 *
1940 * Turn LED on.
1941 **/
1942 s32 e1000_led_on_generic(struct e1000_hw *hw)
1943 {
1944 u32 ctrl;
1945
1946 DEBUGFUNC("e1000_led_on_generic");
1947
1948 switch (hw->phy.media_type) {
1949 case e1000_media_type_fiber:
1950 ctrl = E1000_READ_REG(hw, E1000_CTRL);
1951 ctrl &= ~E1000_CTRL_SWDPIN0;
1952 ctrl |= E1000_CTRL_SWDPIO0;
1953 E1000_WRITE_REG(hw, E1000_CTRL, ctrl);
1954 break;
1955 case e1000_media_type_copper:
1956 E1000_WRITE_REG(hw, E1000_LEDCTL, hw->mac.ledctl_mode2);
1957 break;
1958 default:
1959 break;
1960 }
1961
1962 return E1000_SUCCESS;
1963 }
1964
1965 /**
1966 * e1000_led_off_generic - Turn LED off
1967 * @hw: pointer to the HW structure
1968 *
1969 * Turn LED off.
1970 **/
1971 s32 e1000_led_off_generic(struct e1000_hw *hw)
1972 {
1973 u32 ctrl;
1974
1975 DEBUGFUNC("e1000_led_off_generic");
1976
1977 switch (hw->phy.media_type) {
1978 case e1000_media_type_fiber:
1979 ctrl = E1000_READ_REG(hw, E1000_CTRL);
1980 ctrl |= E1000_CTRL_SWDPIN0;
1981 ctrl |= E1000_CTRL_SWDPIO0;
1982 E1000_WRITE_REG(hw, E1000_CTRL, ctrl);
1983 break;
1984 case e1000_media_type_copper:
1985 E1000_WRITE_REG(hw, E1000_LEDCTL, hw->mac.ledctl_mode1);
1986 break;
1987 default:
1988 break;
1989 }
1990
1991 return E1000_SUCCESS;
1992 }
1993
1994 /**
1995 * e1000_set_pcie_no_snoop_generic - Set PCI-express capabilities
1996 * @hw: pointer to the HW structure
1997 * @no_snoop: bitmap of snoop events
1998 *
1999 * Set the PCI-express register to snoop for events enabled in 'no_snoop'.
2000 **/
2001 void e1000_set_pcie_no_snoop_generic(struct e1000_hw *hw, u32 no_snoop)
2002 {
2003 u32 gcr;
2004
2005 DEBUGFUNC("e1000_set_pcie_no_snoop_generic");
2006
2007 if (hw->bus.type != e1000_bus_type_pci_express)
2008 goto out;
2009
2010 if (no_snoop) {
2011 gcr = E1000_READ_REG(hw, E1000_GCR);
2012 gcr &= ~(PCIE_NO_SNOOP_ALL);
2013 gcr |= no_snoop;
2014 E1000_WRITE_REG(hw, E1000_GCR, gcr);
2015 }
2016 out:
2017 return;
2018 }
2019
2020 /**
2021 * e1000_disable_pcie_master_generic - Disables PCI-express master access
2022 * @hw: pointer to the HW structure
2023 *
2024 * Returns 0 (E1000_SUCCESS) if successful, else returns -10
2025 * (-E1000_ERR_MASTER_REQUESTS_PENDING) if master disable bit has not caused
2026 * the master requests to be disabled.
2027 *
2028 * Disables PCI-Express master access and verifies there are no pending
2029 * requests.
2030 **/
2031 s32 e1000_disable_pcie_master_generic(struct e1000_hw *hw)
2032 {
2033 u32 ctrl;
2034 s32 timeout = MASTER_DISABLE_TIMEOUT;
2035 s32 ret_val = E1000_SUCCESS;
2036
2037 DEBUGFUNC("e1000_disable_pcie_master_generic");
2038
2039 if (hw->bus.type != e1000_bus_type_pci_express)
2040 goto out;
2041
2042 ctrl = E1000_READ_REG(hw, E1000_CTRL);
2043 ctrl |= E1000_CTRL_GIO_MASTER_DISABLE;
2044 E1000_WRITE_REG(hw, E1000_CTRL, ctrl);
2045
2046 while (timeout) {
2047 if (!(E1000_READ_REG(hw, E1000_STATUS) &
2048 E1000_STATUS_GIO_MASTER_ENABLE))
2049 break;
2050 usec_delay(100);
2051 timeout--;
2052 }
2053
2054 if (!timeout) {
2055 DEBUGOUT("Master requests are pending.\n");
2056 ret_val = -E1000_ERR_MASTER_REQUESTS_PENDING;
2057 goto out;
2058 }
2059
2060 out:
2061 return ret_val;
2062 }
2063
2064 /**
2065 * e1000_reset_adaptive_generic - Reset Adaptive Interframe Spacing
2066 * @hw: pointer to the HW structure
2067 *
2068 * Reset the Adaptive Interframe Spacing throttle to default values.
2069 **/
2070 void e1000_reset_adaptive_generic(struct e1000_hw *hw)
2071 {
2072 struct e1000_mac_info *mac = &hw->mac;
2073
2074 DEBUGFUNC("e1000_reset_adaptive_generic");
2075
2076 if (!mac->adaptive_ifs) {
2077 DEBUGOUT("Not in Adaptive IFS mode!\n");
2078 goto out;
2079 }
2080
2081 mac->current_ifs_val = 0;
2082 mac->ifs_min_val = IFS_MIN;
2083 mac->ifs_max_val = IFS_MAX;
2084 mac->ifs_step_size = IFS_STEP;
2085 mac->ifs_ratio = IFS_RATIO;
2086
2087 mac->in_ifs_mode = false;
2088 E1000_WRITE_REG(hw, E1000_AIT, 0);
2089 out:
2090 return;
2091 }
2092
2093 /**
2094 * e1000_update_adaptive_generic - Update Adaptive Interframe Spacing
2095 * @hw: pointer to the HW structure
2096 *
2097 * Update the Adaptive Interframe Spacing Throttle value based on the
2098 * time between transmitted packets and time between collisions.
2099 **/
2100 void e1000_update_adaptive_generic(struct e1000_hw *hw)
2101 {
2102 struct e1000_mac_info *mac = &hw->mac;
2103
2104 DEBUGFUNC("e1000_update_adaptive_generic");
2105
2106 if (!mac->adaptive_ifs) {
2107 DEBUGOUT("Not in Adaptive IFS mode!\n");
2108 goto out;
2109 }
2110
2111 if ((mac->collision_delta * mac->ifs_ratio) > mac->tx_packet_delta) {
2112 if (mac->tx_packet_delta > MIN_NUM_XMITS) {
2113 mac->in_ifs_mode = true;
2114 if (mac->current_ifs_val < mac->ifs_max_val) {
2115 if (!mac->current_ifs_val)
2116 mac->current_ifs_val = mac->ifs_min_val;
2117 else
2118 mac->current_ifs_val +=
2119 mac->ifs_step_size;
2120 E1000_WRITE_REG(hw, E1000_AIT, mac->current_ifs_val);
2121 }
2122 }
2123 } else {
2124 if (mac->in_ifs_mode &&
2125 (mac->tx_packet_delta <= MIN_NUM_XMITS)) {
2126 mac->current_ifs_val = 0;
2127 mac->in_ifs_mode = false;
2128 E1000_WRITE_REG(hw, E1000_AIT, 0);
2129 }
2130 }
2131 out:
2132 return;
2133 }
2134
2135 /**
2136 * e1000_validate_mdi_setting_generic - Verify MDI/MDIx settings
2137 * @hw: pointer to the HW structure
2138 *
2139 * Verify that when not using auto-negotiation that MDI/MDIx is correctly
2140 * set, which is forced to MDI mode only.
2141 **/
2142 s32 e1000_validate_mdi_setting_generic(struct e1000_hw *hw)
2143 {
2144 s32 ret_val = E1000_SUCCESS;
2145
2146 DEBUGFUNC("e1000_validate_mdi_setting_generic");
2147
2148 if (!hw->mac.autoneg && (hw->phy.mdix == 0 || hw->phy.mdix == 3)) {
2149 DEBUGOUT("Invalid MDI setting detected\n");
2150 hw->phy.mdix = 1;
2151 ret_val = -E1000_ERR_CONFIG;
2152 goto out;
2153 }
2154
2155 out:
2156 return ret_val;
2157 }
Mirror of AROS' svn.